KR20090044573A - Method of fabricating semiconductor device - Google Patents

Method of fabricating semiconductor device Download PDF

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Publication number
KR20090044573A
KR20090044573A KR1020070110713A KR20070110713A KR20090044573A KR 20090044573 A KR20090044573 A KR 20090044573A KR 1020070110713 A KR1020070110713 A KR 1020070110713A KR 20070110713 A KR20070110713 A KR 20070110713A KR 20090044573 A KR20090044573 A KR 20090044573A
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KR
South Korea
Prior art keywords
photoresist
pattern
photoresist pattern
resist
semiconductor device
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Application number
KR1020070110713A
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Korean (ko)
Inventor
고성우
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070110713A priority Critical patent/KR20090044573A/en
Publication of KR20090044573A publication Critical patent/KR20090044573A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, forming a photoresist pattern on an etched layer formed on a semiconductor substrate; Reflowing the silylated photoresist pattern by baking the photoresist pattern using a silylating agent and then baking at a temperature above a glass transition temperature; And performing an O 2 plasma process on the reflowed photoresist pattern. According to the method of the present invention, it is possible to improve the CD uniformity deterioration phenomenon of the fine contact hole due to the resist uniformity defect caused by the use of the thick photoresist film during the reflow of the photoresist film.

Resist Reflow, Silylation, Pattern Formation

Description

Method of manufacturing a semiconductor device {Method of Fabricating Semiconductor Device}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to the CD uniformity deterioration of fine contact holes due to poor resist uniformity caused by the use of a thick photoresist film during reflow of the photoresist pattern. It is related with the manufacturing method of the semiconductor element which can be improved.

In forming a contact hole, which is one of the semiconductor fine pattern forming processes, a resist reflow process or the like may be introduced when it is necessary to form a fine contact hole having a resolution higher than that of an exposure apparatus. The resist reflow process refers to a process of forming a photoresist pattern having a resolution equivalent to that of an exposure apparatus by performing an exposure process and a development process, and then applying thermal energy above the glass transition temperature of the resist so that the photoresist is thermally flowed. do. At this time, the already formed pattern is heat-flowed in the direction of reducing the original size by the supplied thermal energy to finally obtain a fine pattern required for the integration process. By introducing such a resist reflow process, it is possible to form a fine pattern below the resolution of the exposure equipment. However, in the resist reflow process, the resist flows rapidly at a specific temperature, particularly at a temperature higher than the glass transition temperature of the photoresist resin. There is a problem in that the profile of the (profile) can be bent or collapsed, and when the excessive flow occurs, the pattern (over flow) appears to be embedded (see Fig. 1a). This is because most of the resists are very sensitive to the applied heat, resulting in poor thermal regulation or excessive heat flow when the flow time is longer than the set point. This phenomenon occurs because the amount of polymer that can be flowed in the upper layer, the central layer and the lower layer in the formed contact hole is different. In the upper layer and the lower layer, the amount of polymer that can flow is relatively smaller than that of the center. There is less flow and the pattern formed after the flow is bent. In order to solve this problem, conventionally, a method of increasing the temperature uniformity of a baking oven to which heat is applied or precisely controlling the time maintained in the baking oven is used. Problems such as not being able to solve the problem, and also by adjusting the oven can not improve the shape of the curved pattern as described above still remains.

In addition, by using a resist having a thickness of 0.5 μm or more, a contact hole is formed in a width much larger than a desired CD (critical dimension), and then a resist reflow is performed to form a contact hole of a desired CD. In this case, a thick resist The use of a film results in deterioration of resist uniformity and reflow profile, thereby degrading the CD uniformity of the contact hole pattern (see FIGS. 1B and 1C). Therefore, even if the desired target CD is matched by using a resist reflow, since the profile is poor, the CD of the actual contact hole formed after etching the lower anti-reflection film is larger than the desired CD. Accordingly, even after etching the etched layer, such CD change is transferred as it is, which may cause CD uniformity deterioration when the resist reflow process is applied to the micro contact hole pattern (FIGS. 2A to 2). 2g).

The present invention has been made to improve the above problems in the conventional semiconductor device manufacturing method, and provides a method for obtaining a pattern having a CD having a desired width through a resist reflow process using a lower thickness photoresist film. For the purpose of

In order to achieve the above object, the present invention

Forming a photoresist pattern on the etched layer formed on the semiconductor substrate;

Silylating the photoresist pattern using a silylating agent, and then baking at a temperature above the glass transition temperature of the photoresist to reflow the sililated photoresist pattern; And

It provides a method of forming a fine pattern of a semiconductor device comprising the step of performing an O 2 plasma treatment process on the reflowed photoresist pattern.

According to the method of the present invention, it is possible to prevent CD uniformity deterioration of the fine contact hole due to poor resist uniformity due to the use of a thick photoresist film during reflow of the photoresist film.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3A to 3H are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to the present invention.

3A and 3B, an etched layer 200, a hard mask layer 210, and a lower anti-reflection film 220 are formed on a semiconductor substrate, and a photoresist film 230 having a thickness of 4,000 to 5,000 μs is sequentially formed. After forming, the first photoresist pattern 235 is formed by exposure and development.

In this case, the photoresist film includes a chemically amplified resin, and is formed using, for example, a composition made of a polymer including a polymerization repeating unit represented by the following Chemical Formula 1.

In the above, R is an acid sensitive protecting group, n is an integer selected from 10 to 500. The acid-sensitive protecting group is not particularly limited, but tertiary-butyl, tetrahydropyran-2-yl, 2-methyl tetrahydropyran-2-yl, tetrahydrofuran-2-yl, 2-methyl tetrahydrofuran- 2-yl, 1-methoxypropyl, 1-methoxy-1-methylethyl, 1-ethoxypropyl, 1-ethoxy-1-methylethyl, 1-methoxyethyl, 1-ethoxyethyl, tertiary -Butoxyethyl, 1-isobutoxyethyl, 2-acetylment-1-yl, etc. are preferable.

In addition, it may further comprise a soft bake and / or post bake step after exposure to exposure to an exposure source, which is preferably carried out at a temperature in the range of 70 to 200 ° C. . The exposure is 0.1 to 100 mJ / using VUV (157 nm), ArF (193 nm), KrF (248 nm), EUV (13 nm), E-beam, X-ray or ion beam as the exposure source. It is preferably carried out with an exposure energy of 2 cm 2. In addition, the development may be carried out using an alkaline developer, the alkali developer is preferably 0.01 to 5% by weight of aqueous tetramethylammonium hydroxide (TMAH) solution.

The first photoresist pattern 235 formed by exposure and development produces a poly (hydroxystyrene) having a hydroxy group that is easy to react with the silylating agent, as shown in Scheme 1 below.

Referring to FIG. 3C, the first photoresist pattern 235 may be silized using a silylating agent under normal temperature and normal pressure. The silylating agent may be hexamethyl disilazane (HMDS), trimethylsilyldimethyl amine (TMSDMA), trimethylsilyldiethyl amine (TMSDEA), tetramethyl disilazane (TMDS). ) And dimethylsilylethylamine (DMSDMA) and the like, and the silylation is preferably performed under a pressure of 10 to 100 Torr and a temperature of 50 to 150 ° C.

The silicon component penetrates into the surface of the photoresist pattern by such sillation, and the Si-O bond occurs because the -OH reactor of the photoresist film and the Si group of the silylating agent react as shown in Scheme 2 below. The silicide film 240 is formed on the photoresist pattern 235.

Referring to FIG. 3D, the second photoresist pattern 235 ′ having a desired width CD is formed by baking at a temperature higher than or equal to the glass transition temperature of the used photoresist film. At this time, the baking temperature is different depending on the type of photoresist used, but is preferably a temperature in the range of 200 to 220 ℃. As described above, if the reflow process is performed after silicide of the photoresist film, the same effect can be obtained by using a resist having a thickness much lower than the photoresist film used in the conventional reflow. The uniformity defect of the pattern to be prevented can be prevented.

Referring to FIG. 3E, when an O 2 plasma process is performed on the silicide film 240, Si and O 2 of the silicide film 240 react to form a silicon oxide material such as SiO 2, and a photoresist. Regardless of the profile of the film, the bottom antireflective film is etched to the desired CD target. That is, only a portion where the lower anti-reflection film is exposed may be etched regardless of the reflow profile of the photoresist film. The O 2 plasma process is preferably performed by adding an oxygen flow rate of 10 to 50 sccm under conditions of a pressure of 10 to 30 mTorr and a voltage of 500 to 800 W.

3F to 3H, after removing the second photoresist pattern 235 ′, the lower hard mask layer 210 is etched using the lower anti-reflection film pattern 225 as an etch stop layer to etch the hard mask layer pattern 215. ) And the lower etching layer 200 is etched using the hard mask layer pattern 215 as an etching prevention layer to form an etching layer pattern 205 having a CD having a desired width. In this case, when the etching layer is a polysilicon layer, an aluminum layer or a titanium nitride layer, the etching process may be performed using a chlorine-based plasma, for example, Cl 2 and BCl 3 gases. When the etched layer is a tungsten layer, an oxide film, and a nitride film, it is preferably performed using a fluorine-based plasma such as CF 4 , C 4 F 8, and C4F 6 gas.

Through such a series of processes, it is possible to prevent the CD uniformity deterioration of the micro contact hole due to the poor pattern uniformity and the poor resist reflow profile caused by using a thick photoresist film.

1A to 1C are photographs showing deterioration of CD uniformity caused by a conventional resist reflow process.

2A to 2G are schematic views illustrating a process of reducing the width of the photoresist pattern by a conventional resist reflow process.

3A to 3H are schematic views showing a process of reducing the width of the photosensitive film pattern by the resist reflow process of the present invention.

<Description of the symbols for the main parts of the drawings>

100,200; Etched layers 105,205; Etching Layer Pattern,

110,210; Hardmask layer, 115,215; Hardmask Layer Pattern,

120,220; Bottom antireflective film, 125,225; Bottom anti-reflective pattern,

130,230; Photoresist film, 135,235; A first photoresist pattern,

235 '; A second photoresist pattern 240; Silylation Film

Claims (5)

Forming a photoresist pattern on the etched layer formed on the semiconductor substrate; Silylating the photoresist pattern using a silylating agent, and then baking at a temperature above the glass transition temperature of the photoresist to reflow the sililated photoresist pattern; And Performing an O 2 plasma treatment process on the reflowed photoresist pattern. The method of claim 1, The photoresist film is a method of manufacturing a semiconductor device, characterized in that having a thickness in the range of 4,000 to 5,000 kPa. The method of claim 1, Said silylating agent is one selected from the group consisting of hexamethyldisilazane, trimethylsilyldimethylamine, trimethylsilyldiethylamine, tetramethyldisilazane, dimethylsilylethylamine and combinations thereof Manufacturing method. The method of claim 1, The silylation is a method of manufacturing a semiconductor device, characterized in that carried out under a pressure of 10 to 100 Torr and temperature conditions of 50 to 150 ℃. The method of claim 1, The O 2 plasma treatment process is performed by applying an oxygen flow rate of 10 to 50 sccm under a pressure of 10 to 30 mTorr and a voltage of 500 to 800 W.
KR1020070110713A 2007-10-31 2007-10-31 Method of fabricating semiconductor device KR20090044573A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8877634B2 (en) 2012-04-05 2014-11-04 Samsung Electronics Co., Ltd. Methods of forming a fine pattern on a substrate and methods of forming a semiconductor device having a fine pattern
CN107104044A (en) * 2017-05-12 2017-08-29 京东方科技集团股份有限公司 A kind of preparation method of method for making its electrode and array base palte
CN112201749A (en) * 2020-09-27 2021-01-08 昕原半导体(上海)有限公司 Preparation method of resistive random access memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8877634B2 (en) 2012-04-05 2014-11-04 Samsung Electronics Co., Ltd. Methods of forming a fine pattern on a substrate and methods of forming a semiconductor device having a fine pattern
CN107104044A (en) * 2017-05-12 2017-08-29 京东方科技集团股份有限公司 A kind of preparation method of method for making its electrode and array base palte
CN112201749A (en) * 2020-09-27 2021-01-08 昕原半导体(上海)有限公司 Preparation method of resistive random access memory

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