KR20090044396A - Method of fabricating the nonvolatile memory device having charge trapping layer - Google Patents

Method of fabricating the nonvolatile memory device having charge trapping layer Download PDF

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KR20090044396A
KR20090044396A KR1020070110482A KR20070110482A KR20090044396A KR 20090044396 A KR20090044396 A KR 20090044396A KR 1020070110482 A KR1020070110482 A KR 1020070110482A KR 20070110482 A KR20070110482 A KR 20070110482A KR 20090044396 A KR20090044396 A KR 20090044396A
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layer
charge trap
trap layer
forming
film
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Korean (ko)
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김용탑
주문식
박기선
박재영
이기홍
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

Abstract

본 발명의 전하트랩층을 갖는 불휘발성 메모리소자의 제조방법은, 기판 위에 터널링층을 형성하는 단계와, 터널링층 위에 전하트랩층을 형성하는 단계와, 터널링층의 일부 표면이 노출되도록 전하트랩층의 일부를 제거하는 단계와, 전하트랩층이 제거된 부분에 측면차단막을 형성하는 단계와, 전하트랩층 및 측면차단막 위에 차폐층을 형성하는 단계와, 그리고 차폐층 위에 컨트롤게이트전극을 형성하는 단계를 포함한다.A method of manufacturing a nonvolatile memory device having a charge trap layer according to the present invention may include forming a tunneling layer on a substrate, forming a charge trap layer on the tunneling layer, and exposing a portion of the surface of the tunneling layer. Removing a portion of the substrate, forming a side blocking film in the portion where the charge trap layer is removed, forming a shielding layer on the charge trap layer and the side blocking film, and forming a control gate electrode on the shielding layer. It includes.

불휘발성 메모리소자(NVM), 전하트랩층, 수평 전하 누설, 리텐션특성 NVM, charge trap layer, horizontal charge leakage, retention characteristics

Description

전하트랩층을 갖는 불휘발성 메모리소자의 제조방법{Method of fabricating the nonvolatile memory device having charge trapping layer}Method of fabricating the nonvolatile memory device having charge trapping layer

본 발명은 불휘발성 메모리소자에 관한 것으로서, 특히 전하트랩층을 갖는 불휘발성 메모리소자의 제조방법에 관한 것이다.The present invention relates to a nonvolatile memory device, and more particularly to a method of manufacturing a nonvolatile memory device having a charge trap layer.

불휘발성 메모리소자로 사용되고 있는 플로팅게이트 구조는 요구되는 성능에 부합하지 못하는 집적도로 인하여 한계를 나타내고 있으며, 이에 따라 최근에는 전하트랩층(charge trapping layer)을 갖는 불휘발성 메모리소자에 대한 관심이 증폭되고 있다. 전하트랩층을 갖는 불휘발성 메모리소자는, 기존의 플로팅게이트 대신에 전하트랩층을 채용하고 있다. 이와 같이 전하트랩층을 갖는 불휘발성 메모리소자의 예로는 SONOS(Silicon-Oxide-Nitride-Oxide-Silicon) 구조나 MANOS(Metal-Al2O3-Nitride-Oxide-Silicon) 구조가 있다.Floating gate structures, which are used as nonvolatile memory devices, have limitations due to the degree of integration that does not meet the required performance. Accordingly, interest in nonvolatile memory devices having a charge trapping layer has recently been amplified. have. A nonvolatile memory device having a charge trap layer employs a charge trap layer instead of a conventional floating gate. Examples of the nonvolatile memory device having the charge trap layer include a silicon-oxide-nitride-oxide-silicon (SONOS) structure or a metal-al 2 O 3 -nitride-oxide-silicon (MANOS) structure.

전하트랩층은 실리콘기판 내의 채널영역에 있다가 일정 조건하에서 터널링층을 관통하여 유입되는 전하(charge)들을 저장시키기 위한 층이다. 일반적으로 전하트랩층으로서 실리콘-댕글링 본드(Si-dangling bond)가 높은 실리콘-리치(Si-rich) 실리콘나이트라이드막을 사용한다. 그러나 이 경우, 석출 실리콘상의 연속적인 도전라인 형성에 따른 전하 손실(charge loss), 또는 높은 트랩 밀도에서 기인되는 전하 뜀(charge hopping) 현상으로 인해 수평방향으로의 전하 손실이 발생된다. 일반적으로 프로그램 동작에 의해 전하트랩층 내로 트랩된 전하가 손실되면, 이는 데이터 저장능력, 즉 리텐션(retention) 특성을 열화시킨다.The charge trap layer is a layer for storing charges flowing through the tunneling layer in a channel region in the silicon substrate under a predetermined condition. In general, a silicon-rich silicon nitride film having a high Si-dangling bond is used as the charge trap layer. In this case, however, charge loss in the horizontal direction occurs due to charge loss due to continuous conductive line formation on the precipitated silicon, or charge hopping due to high trap density. In general, if the charge trapped into the charge trap layer by the program operation is lost, this degrades the data storage capacity, that is, retention characteristics.

본 발명이 해결하고자 하는 과제는, 전하트랩층 내에 트랩되어 있는 전하들의 수평방향으로의 손실을 억제하여 리텐션 특성의 열화가 방지되도록 하는 전하트랩층을 갖는 불휘발성 메모리소자의 제조방법을 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a nonvolatile memory device having a charge trap layer which prevents degradation of retention characteristics by suppressing loss of charges trapped in the charge trap layer in a horizontal direction. will be.

본 발명의 일 실시예에 따르면, 기판 위에 터널링층을 형성한다. 터널링층 위에 전하트랩층을 형성한다. 터널링층의 일부 표면이 노출되도록 전하트랩층의 일부를 제거한다. 전하트랩층이 제거된 부분에 측면차단막을 형성한다. 전하트랩층 및 측면차단막 위에 차폐층을 형성한다. 그리고 차폐층 위에 컨트롤게이트전극을 형성한다.According to an embodiment of the present invention, a tunneling layer is formed on the substrate. A charge trap layer is formed on the tunneling layer. A portion of the charge trap layer is removed to expose some surfaces of the tunneling layer. A side blocking film is formed on the portion where the charge trap layer is removed. A shielding layer is formed on the charge trap layer and the side blocking film. The control gate electrode is formed on the shielding layer.

전하트랩층의 일부를 제거하는 단계는, 전하트랩층 위에 전하트랩층의 일부 표면을 노출시키는 개구부를 갖는 마스크막패턴을 형성하는 단계와, 마스크막패턴을 식각마스크로 터널링층의 일부 표면이 노출되도록 전하트랩층의 노출부분을 제거하는 단계와, 그리고 마스크막패턴을 제거하는 단계를 포함할 수 있다.Removing a portion of the charge trap layer may include forming a mask layer pattern having an opening on the charge trap layer to expose a portion of the surface of the charge trap layer, and exposing the mask layer pattern with an etch mask to expose a portion of the surface of the tunneling layer. The method may include removing the exposed portion of the charge trap layer and removing the mask layer pattern.

전하트랩층의 일부를 제거하는 단계는, 기판 위에 전하트랩층이 인접하는 전하트랩층들과 일정 간격 이격되는 블록 형태가 되도록 수행할 수 있다.The removing of the portion of the charge trap layer may be performed such that the charge trap layer on the substrate is in the form of a block spaced apart from the adjacent charge trap layers.

측면차단막을 형성하는 단계는, 전하트랩층이 제거된 부분이 채워지도록 측면차단막용 절연막을 형성하는 단계와, 그리고 전하트랩층의 상부면이 노출되도록 측면차단막용 절연막을 평탄화시키는 단계를 포함할 수 있다.Forming the sidewalls may include forming an insulating film for the sidewalls so that the portion where the charge trap layer has been removed is filled, and planarizing the insulating film for the sidewalls so that the top surface of the chargetrap layer is exposed. have.

측면차단막은 옥사이드막으로 형성할 수 있다.The side blocking film may be formed of an oxide film.

전하트랩층의 측면에 측면차단막을 배치시킴으로써, 전하트랩층 내의 전하들이 측면 방향으로 누설되는 것이 억제되며, 이에 따라 불휘발성 메모리소자의 리텐션 특성을 향상시킬 수 있다.By disposing the side blocking film on the side of the charge trap layer, leakage of charges in the charge trap layer in the lateral direction can be suppressed, thereby improving retention characteristics of the nonvolatile memory device.

본 발명의 일 실시예에 따른 전하트랩층을 갖는 불휘발성 메모리소자의 제조방법은, 전하트랩층을 블록 형태로 형성시킨 후에, 인접하는 전하트랩층들 사이의 공간 내에 측면차단막을 형성시킴으로써 전하트랩층 내의 전하들이 수평방향으로 누설되는 현상을 억제시킨다는 점에 그 특징이 있다. 이와 같은 과정을 도 1 내지 도 5를 참조하여 설명하면 다음과 같다.In the method of manufacturing a nonvolatile memory device having a charge trap layer according to an embodiment of the present invention, after forming the charge trap layer in a block form, a charge trap is formed by forming a side blocking film in a space between adjacent charge trap layers. Its characteristic is that it suppresses the leakage of charges in the horizontal direction. Such a process will be described with reference to FIGS. 1 to 5 as follows.

도 1을 참조하면, 실리콘기판과 같은 기판(100)에 소자분리막(110)을 형성한다. 이를 위해 기판(100)의 소자분리영역에 트랜치를 형성하고, 이 트랜치 내부를 소자분리용 절연막을 채운다. 소자분리용 절연막으로는 스핀온절연막(SOD; Spin On Dielectric)이나 또는 고밀도플라즈마(HDP; High Density Plasma) 산화막을 사용할 수 있다. 다음에 기판(100) 위에 터널링층(120)을 형성한다. 터널링층(120)은 적어도 20Å 이상의 두께를 갖는 옥사이드막으로 형성한다. 옥사이드막 형성을 위해서는 열산화방법이나 라디컬산화(radical oxidation)방법을 사용할 수 있다.Referring to FIG. 1, an isolation layer 110 is formed on a substrate 100 such as a silicon substrate. For this purpose, a trench is formed in the device isolation region of the substrate 100, and the trench is filled with an insulating film for device isolation. As an insulating film for device isolation, a spin on dielectric (SOD) or high density plasma (HDP) oxide film may be used. Next, a tunneling layer 120 is formed on the substrate 100. The tunneling layer 120 is formed of an oxide film having a thickness of at least 20 GPa. In order to form an oxide film, a thermal oxidation method or a radical oxidation method may be used.

도 2를 참조하면, 터널링층(120) 위에 전하트랩층(130)을 형성한다. 전하트랩층(130)의 두께는 대략 20Å 내지 100Å이 되도록 한다. 전하트랩층(130)은 스토 이키오메트릭(stoicheometric) 실리콘나이트라이드(Si3N4)막 또는 실리콘-리치(silicon-rich) 실리콘나이트라이드(SixNy)막이나, 그 조합으로 형성한다. 다른 예에서, 전하트랩층(130)은, 하프늄옥사이드(HfO2)막, 지르코늄옥사이드(ZrO2)막, 하프늄알루미늄옥사이드(HfAlO)막, 하프늄실리콘옥사이드(HfSiO)막, 지르코늄알루미늄옥사이드(ZrAlO)막, 지르코늄실리콘옥사이드(ZrSiO)막 등의 산화물로 형성할 수도 있다. 이와 같은 전하트랩층(130)은 원자층증착(ALD; Atomic Layer Deposition)방법이나, 또는 화학기상증착(CVD; Chemical Vapor Deposition)방법을 사용하여 형성할 수 있다. 전하트랩층(130)을 형성한 후에는 전하트랩층(130) 위에 마스크막패턴(140)을 형성한다. 마스크막패턴(140)은 전하트랩층(130)의 일부표면을 노출시키는 개구부들(142)을 갖는다. 마스크막패턴(140)은 포토레지스트막으로 형성할 수 있다.Referring to FIG. 2, the charge trap layer 130 is formed on the tunneling layer 120. The thickness of the charge trap layer 130 is approximately 20 kPa to 100 kPa. The charge trap layer 130 is formed of a stoicheometric silicon nitride (Si 3 N 4 ) film, a silicon-rich silicon nitride (Si x N y ) film, or a combination thereof. . In another example, the charge trap layer 130 may include a hafnium oxide (HfO 2) film, a zirconium oxide (ZrO 2) film, a hafnium aluminum oxide (HfAlO) film, a hafnium silicon oxide (HfSiO) film, a zirconium aluminum oxide (ZrAlO) film, It may also be formed of an oxide such as a zirconium silicon oxide (ZrSiO) film. The charge trap layer 130 may be formed using an atomic layer deposition (ALD) method or a chemical vapor deposition (CVD) method. After the charge trap layer 130 is formed, a mask layer pattern 140 is formed on the charge trap layer 130. The mask layer pattern 140 has openings 142 exposing a portion of the surface of the charge trap layer 130. The mask film pattern 140 may be formed as a photoresist film.

도 3을 참조하면, 마스크막패턴(도 2의 140)을 식각마스크로 전하트랩층(130)의 노출부분에 대한 식각을 수행한다. 이 식각은 전하트랩층(130)과 터널링층(120)의 충분한 식각선택비를 이용하여 수행할 수 있다. 이 식각에 의해, 전하트랩층(130)의 노출부분이 제거되고, 이 부분에서는 터널링층(120)의 표면이 노출된다. 따라서 전하트랩층(130)은 블록(block)형태가 된다. 즉 전하트랩층(130)은 사방에서 인접하는 전하트랩층들과 일정간격 이격되도록 배치된다. 다음에 마스크막패턴(140)을 제거한 후, 전하트랩층(130)이 제거된 부분이 채워지도록 전면에 측면차단막용 절연막(152)을 형성한다. 측면차단막용 절연막(152)은 옥사이드막으로 형 성한다. 다른 예에서, 측면차단막용 절연막(152)은 테오스(TEOS)막으로 형성할 수 있다.Referring to FIG. 3, the exposed portion of the charge trap layer 130 is etched using the mask layer pattern 140 (FIG. 2) as an etching mask. This etching may be performed using a sufficient etching selectivity of the charge trap layer 130 and the tunneling layer 120. By this etching, the exposed portion of the charge trap layer 130 is removed, and the surface of the tunneling layer 120 is exposed in this portion. Therefore, the charge trap layer 130 is in the form of a block. That is, the charge trap layer 130 is disposed to be spaced apart from the charge trap layers adjacent to each other at regular intervals. Next, after the mask film pattern 140 is removed, the insulating film 152 for sidewalls is formed on the entire surface to fill the portion where the charge trap layer 130 is removed. The insulating film 152 for side blocking films is formed of an oxide film. In another example, the insulating layer 152 for sidewalls may be formed of a TEOS film.

도 4를 참조하면, 측면차단막용 절연막(도 3의 152)에 대한 평탄화를 수행한다. 이 평탄화는 화학적기계적폴리싱(CMP; Chemical Mechanical Polishing)방법을 사용하여 전하트랩층(130)의 상부면이 노출될 때까지 수행한다. 즉 측면차단막용 절연막(152)과 전하트랩층(130) 사이의 선택비가 충분한 점을 이용하여, 전하트랩층(130)을 정지막으로 사용한다. 이와 같은 평탄화를 수행하면, 전하트랩층(130)의 측면을 둘러싸는 측면차단막(150)이 형성되며, 이 측면차단막(150)에 의해 전하트랩층(130)의 측면은 인접하는 다른 전하트랩층(130)들과 절연된다. 따라서 전하트랩층(130) 내의 실리콘상 석출이나 전하 뜀 현상으로 인한 수평방향으로의 전하 손실 현상은 측면차단막(150)에 의해 그 발생이 억제된다.Referring to FIG. 4, planarization of the insulating film for side blocking films 152 of FIG. 3 is performed. This planarization is performed until the top surface of the charge trap layer 130 is exposed using a chemical mechanical polishing (CMP) method. That is, the charge trap layer 130 is used as the stop film by using a point where the selectivity between the insulating film 152 for the side blocking film and the charge trap layer 130 is sufficient. When the planarization is performed, a side blocking film 150 surrounding the side of the charge trap layer 130 is formed, and the side of the charge trap layer 130 is adjacent to another charge trap layer by the side blocking film 150. 130 is insulated from. Therefore, the occurrence of charge loss in the horizontal direction due to deposition of silicon phase or charge skipping in the charge trap layer 130 is suppressed by the side blocking film 150.

도 5를 참조하면, 전하트랩층(130) 및 측면차단막(150) 위에 차폐층(blocking layer)(160)을 형성한다. 차폐층(160)은 대략 50Å 내지 300Å 두께의 알루미늄옥사이드(Al2O3)막으로 형성한다. 다른 예에서 차폐층(160)은 화학기상증착(CVD)방법을 이용한 실리콘옥사이드막으로 형성할 수도 있다. 차폐층(160)을 형성한 후에는 급속열처리(RTP; Rapid Thermal Processing)를 수행하여 밀집화(densification)시킬 수 있다.Referring to FIG. 5, a blocking layer 160 is formed on the charge trap layer 130 and the side blocking layer 150. The shielding layer 160 is formed of an aluminum oxide (Al 2 O 3 ) film having a thickness of approximately 50 Pa to 300 Pa. In another example, the shielding layer 160 may be formed of a silicon oxide film using a chemical vapor deposition (CVD) method. After the shielding layer 160 is formed, rapid thermal processing (RTP) may be performed to densification.

다음에 차폐층(160) 위에 컨트롤게이트전극(170)을 형성한다. 컨트롤게이트전극(170)은 n형 불순물이 고농도, 예컨대 1×1019 내지 5×1020 atoms/㎤로 도핑된 폴리실리콘막으로 형성한다. 다른 예에서, 컨트롤게이트전극(170)은 일함수(work function)가 4.5eV 이상인 금속게이트, 예컨대 탄탈륨나이트라이드(TaN)막으로 형성한다. 다음에 컨트롤게이트전극(170) 위에 워드라인의 비저항을 낮추기 위해 저저항층(180)을 형성한다. 컨트롤게이트전극(170)을 폴리실리콘막으로 형성한 경우, 저저항층(180)은 텅스텐실리사이드(WSi)막이나, 텅스텐나이트라이드(WN)막/텅스텐실리사이드(WSi)막으로 형성한다. 컨트롤게이트전극(170)을 금속막으로 형성한 경우, 저저항층(180)은 폴리실리콘막/텅스텐나이트라이드(WN)막/텅스텐실리사이드(WSi)막으로 형성한다. 다음에 도면에 나타내지는 않았지만, 통상의 패터닝을 수행하여 측면차단막(150)에 의해 측면이 절연되는 전하트랩층(150)을 갖는 게이트스택을 형성한다. 그리고 기판(100) 내에 불순물영역(미도시) 형성을 위한 이온주입을 수행한다.Next, the control gate electrode 170 is formed on the shielding layer 160. The control gate electrode 170 is formed of a polysilicon film doped with a high concentration of n-type impurities, for example, 1 × 10 19 to 5 × 10 20 atoms / cm 3. In another example, the control gate electrode 170 is formed of a metal gate such as a tantalum nitride (TaN) film having a work function of 4.5 eV or more. Next, a low resistance layer 180 is formed on the control gate electrode 170 to lower the specific resistance of the word line. When the control gate electrode 170 is formed of a polysilicon film, the low resistance layer 180 is formed of a tungsten silicide (WSi) film or a tungsten nitride (WN) film / tungsten silicide (WSi) film. When the control gate electrode 170 is formed of a metal film, the low resistance layer 180 is formed of a polysilicon film / tungsten nitride (WN) film / tungsten silicide (WSi) film. Next, although not shown in the drawing, a conventional patterning is performed to form a gate stack having a charge trap layer 150 insulated from the side by the side blocking layer 150. In addition, ion implantation is performed to form an impurity region (not shown) in the substrate 100.

도 1 내지 도 5는 본 발명에 따른 전하트랩층을 갖는 불휘발성 메모리소자의 제조방법을 설명하기 위하여 나타내 보인 단면도들이다.1 to 5 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a charge trap layer according to the present invention.

Claims (5)

기판 위에 터널링층을 형성하는 단계;Forming a tunneling layer over the substrate; 상기 터널링층 위에 전하트랩층을 형성하는 단계;Forming a charge trap layer on the tunneling layer; 상기 터널링층의 일부 표면이 노출되도록 상기 전하트랩층의 일부를 제거하는 단계;Removing a portion of the charge trap layer to expose a portion of the surface of the tunneling layer; 상기 전하트랩층이 제거된 부분에 측면차단막을 형성하는 단계;Forming a side blocking layer on a portion where the charge trap layer is removed; 상기 전하트랩층 및 측면차단막 위에 차폐층을 형성하는 단계; 및Forming a shielding layer on the charge trap layer and the side blocking layer; And 상기 차폐층 위에 컨트롤게이트전극을 형성하는 단계를 포함하는 전하트랩층을 갖는 불휘발성 메모리소자의 제조방법.A method of manufacturing a nonvolatile memory device having a charge trap layer comprising forming a control gate electrode on the shielding layer. 제1항에 있어서, 상기 전하트랩층의 일부를 제거하는 단계는,The method of claim 1, wherein the removing of the portion of the charge trap layer comprises: 상기 전하트랩층 위에 상기 전하트랩층의 일부 표면을 노출시키는 개구부를 갖는 마스크막패턴을 형성하는 단계;Forming a mask layer pattern on the charge trap layer, the mask layer pattern having an opening that exposes a portion of the surface of the charge trap layer; 상기 마스크막패턴을 식각마스크로 상기 터널링층의 일부 표면이 노출되도록 상기 전하트랩층의 노출부분을 제거하는 단계; 및Removing the exposed portion of the charge trap layer to expose a portion of the surface of the tunneling layer using the mask layer pattern as an etch mask; And 상기 마스크막패턴을 제거하는 단계를 포함하는 전하트랩층을 갖는 불휘발성 메모리소자의 제조방법.A method of manufacturing a nonvolatile memory device having a charge trap layer, the method comprising removing the mask film pattern. 제1항에 있어서,The method of claim 1, 상기 전하트랩층의 일부를 제거하는 단계는, 상기 기판 위에 전하트랩층이 인접하는 전하트랩층들과 일정 간격 이격되는 블록 형태가 되도록 수행하는 전하트랩층을 갖는 불휘발성 메모리소자의 제조방법.The removing of the portion of the charge trap layer may include performing a charge trap layer on the substrate such that the charge trap layer is formed in a block spaced apart from adjacent charge trap layers by a predetermined distance. 제1항에 있어서, 상기 측면차단막을 형성하는 단계는,The method of claim 1, wherein the forming of the side barrier layer, 상기 전하트랩층이 제거된 부분이 채워지도록 측면차단막용 절연막을 형성하는 단계; 및Forming an insulating film for sidewalls so that the portion where the charge trap layer is removed is filled; And 상기 전하트랩층의 상부면이 노출되도록 상기 측면차단막용 절연막을 평탄화시키는 단계를 포함하는 전하트랩층을 갖는 불휘발성 메모리소자의 제조방법.And planarizing the insulating film for sidewalls so that the upper surface of the charge trap layer is exposed. 제1항에 있어서,The method of claim 1, 상기 측면차단막은 옥사이드막으로 형성하는 전하트랩층을 갖는 불휘발성 메모리소자의 제조방법.The side blocking film is a manufacturing method of a nonvolatile memory device having a charge trap layer formed of an oxide film.
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