KR20090038155A - Cyclic redundancy check system and method thereof - Google Patents

Abstract

A CRC(Cyclic Redundancy Check) system and a method thereof are provided to implement the fast operation speed through the parallel processing. A CRC system comprises an input unit(100), an N-byte separation unit(200), a processing unit(300), an information data determining unit(400), and an output unit(500). The input unit receives the information data and outputs to the N-byte separation unit. The N-byte separation unit includes a continuity maintenance part(210) and divides the information data into the N-byte unit. The processing unit comprises a block operation unit(600(1)~600(n)), and an XOR operation unit(700). The block operation unit comprises an N-byte operation part(800(1)~800(n)) and a zero block operation unit(900(1)~900(n-1)).

Description

Cyclic redundancy inspection system and method {CYCLIC REDUNDANCY CHECK SYSTEM AND METHOD THEREOF}

The present invention relates to a cyclic redundancy inspection system and method. In particular, the present invention relates to a cyclic redundancy inspection system and method having a high operating speed through parallel processing.

Communication error detection methods of wired or wireless communication systems include a parity bit method, a check sum method, and a cyclic redundancy check method.

The parity bit method cannot detect an error when a plurality of bits in the data change at one time. In addition, the method using a checksum has a low probability of error detection by these methods, for example, when an error occurs with +1 in one byte and -1 in another byte.

The cyclic redundancy check method is a method in which the transmitting end attaches extra information, that is, a frame check sequence (FCS), after the least significant bit (LSB) of the original data.

The frame check sequence (FCS) adds a predetermined length of information having a value of 0 after the least significant bit of the original data, and divides the data into a binary generator by using a predefined generator.

For example, consider the case where the original data is 11100110 and the generator is 11001. If the generator is 5 bits with 11001, 4 bits with a value of 0 are added after the least significant bit of the original data. That is, the modified original data is 111001100000. Thereafter, the modified original data 111001100000 is binary divided into a predefined generator 11001. The rest is 0110. At this time, the remaining value is a frame check sequence (FCS).

When transmitting the original data 11100110, the transmitter adds and transmits 0110, which is a frame check sequence (FCS). That is, the transmitting end transmits 111001100110.

In order to detect an error of the received information data 111001100110, the receiving end binary divides the information data with a generator that is predefined at the transmitting end. If the result of binary division is '0', then success. Otherwise, it is treated as an error.

The cyclic redundancy test method is simple and has low overhead for error detection and good error detection performance, which is why WLAN, UWB, RFID and wireless sensor network (WSN) It is widely used in wireless communication systems such as) and wired communication systems such as Ethernet.

The conventional cyclic redundancy test method is described in hardware language (hardware-based) when the platform design was calculated in a parallel manner. This is because, when written in a software-based language, the processor load is increased relative to other functional blocks, which degrades the performance of the entire system.

With the recent development of semiconductor process technology, multi-processor system-on-chip (MP SoC), which has several processors and a large amount of memory on one chip, has emerged as the core of non-memory. Software-based cyclic redundancy inspection method is in the spotlight.

The most typical of these methods is the use of a cyclic redundancy table, which enables high speed in the conventional method using a 1-bit shift register. They store cyclic redundancy check values calculated in advance in a table, and perform cyclic redundancy check in units of 1 byte, 4 bytes, or 8 bytes instead of bits. However, these methods also depend on the data to be processed next and are serialized, and thus there is a limit in reducing the processing time of the cyclic redundancy check.

One of the trends of current wireless communication systems is the high transmission speed. For example, a wireless LAN system aims at a transmission rate of several hundred megabits (Mbps), and an ultra-wideband system aims at a transmission rate of several gigabytes (Gbps). Therefore, the cyclic redundancy inspection system mounted in such a system should also operate at high speed.

In order for the cyclic redundancy inspection system to have a high processing capacity, the clock driving the clock must be faster or parallel processing is possible. The clock speed is limited by the level of device technology, so the increase is limited.

Accordingly, the technical problem to be achieved by the present invention is to provide a cyclic redundancy inspection system and method having a fast operation speed through parallel processing.

According to one aspect of the invention, a cyclic redundancy inspection system is provided. The cyclic redundancy inspection system includes a partitioning unit for dividing the information data into units of N bytes (N > 0 or more natural numbers); And a processing unit for performing operations on the divided N bytes of information data by performing operations on the divided N bytes of information data, respectively, by n blocks (n> 0 or more natural numbers).

According to another feature of the present invention, a cyclic redundancy inspection method is provided. Cyclic surplus inspection method includes the steps of (a) receiving information data; (b) dividing the information data into units of N bytes; And (c) obtaining a cyclic redundancy value for (n x N) bytes.

According to the present invention, it is possible to provide a cyclic redundancy inspection system and method having a high operating speed through parallel processing.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, without excluding other components unless specifically stated otherwise. In addition, the terms “… unit”, “… unit”, “module”, etc. described in the specification mean a unit that processes at least one function or operation, which may be implemented by hardware or software or a combination of hardware and software. have.

Now, the cyclic redundancy inspection system and method according to an embodiment of the present invention will be described in detail with reference to the drawings.

1 is a conceptual diagram of a cyclic redundancy inspection system and method according to an embodiment of the present invention.

The cyclic redundancy inspection system and method according to an embodiment of the present invention divides the received information data into blocks of a specific length, performs calculation for each block in a plurality of calculation units, and then performs a cyclic redundancy check by combining them. do.

Since the general cyclic redundancy check method is based on binary division, continuous operation from the most significant bit (MSB) to the least significant bit (LSB) of information data is required.

In the cyclic redundancy check system and method according to an embodiment of the present invention, n block operators process N-byte data in parallel, find an operation value of a zero block according to the position of the N-byte, and then perform an exclusive OR operation thereof. (Hereinafter, 'exclusive OR' is referred to as 'XOR operation').

That is, the cyclic redundancy inspection system and method according to an embodiment of the present invention does not perform continuous operation from the most significant bit (MSB) to the least significant bit (LSB) of information data, and transmits the information data to each of the plurality of calculation units for each block of a specific length. Allocate and compute to perform parallel processing.

Specifically, the cyclic redundancy inspection system and method according to an embodiment of the present invention performs operations on N bytes of data in parallel in the n block calculators for (n x N) bytes of information data.

를 제너레이터

로 이진 나눗 셈한 연산값은

이다. When the cyclic redundancy check value is obtained through continuous operation as in the general cyclic redundancy check method, (nx N) bytes of data

Generator

The binary division by

to be.

However, the cyclic redundancy test value may be expressed as shown in Equation 1 below through successive operations.

[Equation 1]

는 N 바이트 단위로 나누어져

,

,...

의 XOR 연산으로 이루어진다. 이때,

,

,...

는 각각 자신에게 할당된 N 바이트 이외에는 0의 값을 가진다. 식 1과 같이, (n x N) 바이트의 데이터

를 제너레이터

로 이진 나눗셈한 연산값은

는, 각각의

,

,...

를 제너레이터

로 이진 나눗셈한 연산값의 XOR 연산값과 같다.

Is divided into N bytes

,

, ...

Consists of an XOR operation. At this time,

,

, ...

Each has a value of 0, except for the N bytes allocated to it. As in Equation 1, (nx N) bytes of data

Generator

The binary division by

Of each

,

, ...

Generator

Is equal to the XOR operation of the binary division.

에 대해, 자신에게 할당된 N 바이트 이외에는 0의 값을 가지는

,

,...

로 분할한다. Cyclic redundancy inspection system and method according to an embodiment of the present invention using (1), (nx N) bytes of data

Has a value of 0 other than the N bytes allocated to it.

,

, ...

Split into

,

,...

에 대한 이진 나눗셈 연산을 수행한다. 이때, n 개의 블록 연산부는 각 블록 연산부에 할당된 N 바이트에 대한 연산을 수행한 후, N 바이트 하위의 0 의 값을 가지는 제로 블록에 대한 연산을 수행한다.Then, in n block operations

,

, ...

Perform a binary division operation on. In this case, the n block operations units perform operations on N bytes allocated to each block operation unit, and then perform operations on zero blocks having a value of 0 below N bytes.

의 경우는 할당 받은 N 바이트 하위에서 0 의 값을 가지는 제로 블록이 없다. 따라서,

의 경우는 N 바이트에 대한 연산만을 수행한다. That is, the operation of each block operation unit performs an operation on the allocated N bytes, and then performs an operation on the zero block having a value of 0 below the N bytes. However, the lowest N bytes allocated

In the case of, there is no zero block with a value of 0 below the allocated N bytes. therefore,

In the case of, only operation on N bytes is performed.

Then, the cyclic redundancy check value for the data of (n x N) bytes is obtained through XOR operation of the operation values of the n block operations units.

에 대한 순환잉여검사 값 C 는, (n x N) 바이트의 데이터 중 최상위 N 바이트를 할당 받고, 할당 받은 N 바이트 하위에서 0 의 값을 가지는 ((n-1) x N) 바이트의 제로 블록을 가지는

에 대한 연산값 C₁', 최상위 N 바이트를 제외하고 가장 상위의 N 바이트를 할당 받고, 할당 받은 N 바이트 하위에서 0 의 값을 가지는 ((n-2) x N) 바이트의 제로 블록을 가지는

에 대한 연산값 C₂', . . . 최하위에서 두 번째 N 바이트를 할당 받고, 할당 받은 N 바이트 하위에서 0 의 값을 가지는 N 바이트의 제로 블록을 가지는

에 대한 연산값 C_{n -1}' 및 최하위 N 바이트를 할당 받은

에 대한 연산값 C_n 의 XOR 연산으로 구해진다. In short, (nx N) bytes of information data

The cyclic redundancy check value C for is given the highest N bytes of (nx N) bytes of data and has a zero block of ((n-1) x N) bytes with a value of 0 below the allocated N bytes.

The operation value for C ₁ ', which is allocated the highest N bytes except the most significant N bytes, and has a zero block of ((n-2) x N) bytes with a value of 0 below the allocated N bytes.

Calculated value for C ₂ ',. . . Is allocated the lowest N second bytes, and has N bytes of zero blocks

Assigned the operation value C _{n -1} 'and least significant N bytes for

It is obtained by XOR operation of operation value C _n for.

2 is a schematic diagram of a cyclic redundancy inspection system according to an embodiment of the present invention.

The information data is divided in units of N bytes, and the divided N byte data is allocated to the block operation unit together with a zero block having a value of 0 below the corresponding N bytes.

Each block operation unit receives N byte data and a lower zero block, and first performs operations on the N byte data to obtain C _n (n = 1, 2, ... n), which is a result of the N byte operation. At this time, the operation for N bytes is performed in units of 4 bytes, and after (N / 4) iterations, C _n (n = 1, 2, ... n) values are obtained.

The block operator performs an operation on the zero block after performing an operation on N bytes. In this case, since the block operation unit allocated the lowest N bytes does not include the zero block, the block operation unit does not perform the zero block operation.

The block operators except for the last block calculator calculate C _n '(n = 1,2, ... n-1) using a cyclic redundancy check table, that is, a zero block table, in which operation values are stored in advance.

XOR operation unit calculates zero-zero blocks with block table value _{C n '(n = 2,3,} .., n-1) and the calculated value of the last block computing section C _n Performs an XOR operation on, and the result is defined as C. Equation 2 shows an operation value C for (nx N) byte information data.

[Equation 2]

In the case where all of the information data has been calculated by operation of (n x N) bytes, the operation value C at this time becomes a cyclic redundancy check value of all the information data. However, if the information data is not finished in one (nx N) byte operation, the operation value C for this (nx N) byte is XORed with the most significant 4 bytes of the next (nx N) byte to be processed. Maintain continuity with the information data that follows.

The time taken to process 4 bytes is defined as S ₄ cycles. Therefore, it takes (N / 4) x S ₄ cycles to process N bytes in 4 byte units. In addition, the zero block operation is performed using the zero block table, and the time taken to perform the XOR operation with the most significant 4 bytes of the next (nx N) bytes is defined as Z cycles.

(N / 4) x S ₄ cycles in parallel processing of N-byte data in the block operation unit and zero block operations in each block operation unit and Z cycles in order to perform XOR operation to combine the results thereof are (nx N). Occurs once each time a byte of data is processed.

These [((N / 4) x S ₄ ) + Z] cycles are repeated until the end of the information data, where C of the final result is the cyclic redundancy check value of the entire information data.

Accordingly, the rotation delay time required to calculate the cyclic redundancy check value for the entire information data L bytes is expressed by Equation 3 below.

[Equation 3]

Referring to Equation 3, when the length L of the information data is constant, the rotation delay time is inversely proportional to the number n of the block operation units and the length N of the data processed by the block operation unit.

3 is a block diagram of a cyclic redundancy inspection system according to an embodiment of the present invention.

According to FIG. 3, the cyclic redundancy inspection system includes an input unit 100, an N-byte division unit 200, a processing unit 300, an information data determination unit 400, and an output unit 500, and the processing unit 300 includes: Block computing units 600 (1) to 600 (n) and an XOR operator 700 are included. In this case, each configuration will be described below.

The input unit 100 receives the information data and outputs the received information data to the N-byte divider 200.

The N byte divider 200 includes a continuity maintainer 210 and divides the information data in units of N bytes. N bytes represent the length of data that each block operation unit calculates. When the length of the information data to be subjected to the cyclic redundancy check is L bytes, each block operation unit is allocated the information data in units of N bytes to perform the operation in parallel.

When the number of block arithmetic units is n, the length L bytes of the information data becomes a multiple of (n x N) bytes. If the length of the information data is not a multiple of (n x N) bytes, 0 is filled in the upper portion of the information data so that the information data is a multiple of (n x N) bytes. In this case, N is a length that can be set by the user and is selected in multiples of four.

When the information data L byte is composed of a plurality of (nx N) bytes, the continuity maintaining unit 210 calculates this time so that the (nx N) byte operation value calculated this time maintains continuity with the next (nx N) byte operation. Performs an XOR operation with the most significant 4 bytes of the (nx N) byte to be processed next with one (nx N) byte operation value C.

The processor 300 performs an operation on (n × N) bytes in parallel in a plurality of calculators. The processor 300 includes n block calculators 600 (1) to 600 (n) and an XOR calculator 700, and the block calculators 600 (1) to 600 (n) are N byte calculators 800 ( 1) to 800 (n)) and zero block calculators 900 (1) to 900 (n-1). In this case, since the block operator 600 (n) to which the lowest N byte data is allocated does not include the zero block, the block operator 600 (n) does not include the zero block operator.

Each of the block operation units 600 (1) to 600 (n) receives a zero block having a value of 0 for the N-byte data allocated to the byte and the lower byte of the allocated N-byte, and performs an operation on the received data.

The N byte calculators 800 (1) to 800 (n) perform operations on the allocated N bytes, and the zero block calculators 900 (1) to 900 (n-1) perform the N byte calculators 800 (1). Based on the operation value of) ~ 800 (n)), the operation is performed on the zero block below N bytes. Detailed configurations of the N byte calculators 800 (1) to 800 (n) and the zero block calculators 900 (1) to 900 (n-1) will be described in detail with reference to FIGS. 4 to 7.

XOR operation unit 700 Performs an XOR operation based on the operation values of the block operation units 600 (1) to 600 (n) to obtain an operation value for (nx N) bytes, and calculates an operation value for (nx N) bytes. It is transmitted to the information data determination unit 400.

The information data determination unit 400 determines whether the operation on the entire information data is completed by the operation on the (n × N) bytes of the processing unit 300. When the operation on the information data L byte is completed, the information data determination unit 400 transmits the operation value received from the processing unit 300 to the output unit 500. On the other hand, when the operation on the information data L byte is not completed, the information data determination unit 400 transmits the operation value received from the processing unit 300 to the continuity maintaining unit 210 of the N byte division unit 200.

The output unit 500 outputs an operation value received from the information data determination unit 400.

4 is a conceptual diagram of an operation performed by an N-byte operation unit according to an embodiment of the present invention, and FIG. 5 is a block diagram of an N-byte operation unit according to an embodiment of the present invention.

Referring to FIG. 4, the N-byte operation unit reads data in units of 32 bits (4 bytes) from the upper part with respect to the allocated N bytes, and for this purpose, the cyclic redundancy check value for 8 bits (1 byte) is preliminarily. It has four calculated values table.

로 이진 나눗셈한 256가지를 각각 1킬로바이트(KByte) 크기의 2⁵⁶ 연산 값 테이블, 2⁴⁸ 연산값 테이블, 2⁴⁰ 연산값 테이블, 2³² 연산값 테이블에 저장해두고 해당하는 8비트에 대한 결과를 검색하여 연산하는데 소모되는 시간을 줄인다.That is, the N byte arithmetic unit (random 8-bit data x 2 ⁵⁶ ), (arbitrary 8-bit data x 2 ⁴⁸ ), (arbitrary 8-bit data x 2 ⁴⁰ ), (arbitrary 8-bit data x 2 ³² ), respectively Generator

256 binary divisions are stored in 2 ⁵⁶ arithmetic value tables, 2 ⁴⁸ arithmetic values tables, 2 ⁴⁰ arithmetic values tables, and 2 ³² arithmetic values tables each 1 kilobyte (KByte) in size, and retrieve the result for the corresponding 8 bits. To reduce the time it takes to compute.

에 이번에 연산을 수행할 32비트(4바이트)의 데이터

를 더해서 연산대상 값

를 결정한다.If the N byte operation unit previously performed 32 bit (4 byte) operation, the result value of the previous operation is

32 bits (4 bytes) of data at this time

Calculation Target Value

Determine.

를 8비트(1바이트)씩 4개

로 분리되고, 각 8 비트에 해당하는 연산값 테이블의 순환잉여검사 값을 연산값 테이블에서 차례로 불러온다. 각 8 비트에 대한 연산값은

,

,

,

로 32비트(4바이트)의 값을 가진다. 식 4는 각 8비트에 대한 연산값을 나타낸 식이다.After that, the N byte arithmetic unit

4 x 8 bits (1 byte)

Separated by, the cyclic redundancy check value of the operation value table corresponding to each 8 bit is read in order from the operation value table. The operation value for each 8 bits is

,

,

,

It has a value of 32 bits (4 bytes). Equation 4 shows an operation value for each 8 bits.

[Equation 4]

, ,

,

는 XOR 연산되고, XOR 연산의 결과인

는 N 바이트 연산부에서 다음에 연산될 4 바이트 데이터

와 다 시 XOR 연산되어 이상에서 설명한 과정이 반복된다. 이때,

는 4 바이트뿐만 아니라 8 바이트, 16 바이트 등으로 확장 가능하다. Four 32-bit math values

, ,

,

Is an XOR operation, which is the result of the XOR operation

Is the 4 byte data to be computed next in the N byte operation unit.

XOR operation is repeated and the process described above is repeated. At this time,

Can be extended to 8 bytes, 16 bytes, etc. as well as 4 bytes.

5 is a block diagram of an N-byte calculation unit according to an embodiment of the present invention.

The cyclic redundancy check system according to the embodiment of the present invention includes n N-byte arithmetic units, and since the n N-byte arithmetic units are all the same, only the first N-byte arithmetic unit 800 (1) will be described here for convenience of description.

Referring to FIG. 5, the N byte calculator 800 (1) includes an input unit 810, a 4 byte divider 820, a processor 830, an N byte data determiner 840, and an output unit 850. The processor 830 includes an 8-bit divider 860, a 2 ⁵⁶ arithmetic unit 870 (1), a 2 ⁴⁸ arithmetic unit 870 (2), a 2 ⁴⁰ arithmetic unit 870 (3), and a 2 ³² arithmetic unit 870. (4)) and an XOR operator 880.

The input unit 810 receives N bytes of data and outputs the received N bytes of data to the 4-byte divider 820.

The 4 byte divider 820 includes a continuity maintainer 821, and divides the N byte data in units of 4 bytes. Four bytes indicate the length of data calculated by the processing unit 830. The continuity maintaining unit 821 stores the operation value of the processing unit 830 with the next 4 bytes and XOR so that the operation value of the processing unit 830 maintains continuity with the next data of the value calculated by the processing unit 830 among the N bytes of data. Perform the operation.

The processor 830 performs four 4 byte operations on four 2 ⁵⁶ operation units 870 (1), 2 ⁴⁸ operation units 870 (2), 2 ⁴⁰ operation units 870 (3), and 2 ³² operation units 870 ( 4)) in parallel.

The processor 830 is an 8-bit divider 860, 2 ⁵⁶ calculators 870 (1), 2 ⁴⁸ calculators 870 (2), 2 ⁴⁰ calculators 870 (3), 2 ³² calculators 870 (4 ) And XOR operator 880, each of 2 ⁵⁶ operator 870 (1), 2 ⁴⁸ operator 870 (2), and 2 ⁴⁰ operator 870 (3), respectively. ) To 891 (4)) and an 8-bit arithmetic value search unit 872 (1) to 872 (4).

The 8-bit divider 860 divides 32 bits (4 bytes) received from the 4-byte divider 820 into four units of 8-bit units, and divides each 8 bit into 2 ⁵⁶ arithmetic units 870 (1) and 2 ^48. The data is transmitted to the calculation unit 870 (2), the 2 ⁴⁰ calculation unit 870 (3), and the 2 ³² calculation unit 870 (4).

At this time, the 32 bits are sequentially performed from the most significant 8 bits to the least significant 8 bits, such as 2 ⁵⁶ arithmetic unit 870 (1), 2 ⁴⁸ arithmetic unit 870 (2), 2 ⁴⁰ arithmetic unit 870 (3), and 2 ³² arithmetic unit 870 (4)).

The ⁵⁶ operator 870 (1) receives the most significant 8 bits of the 32 bits from the 8 bit divider 860, and outputs an operation value thereof to the XOR operator 880. The 2 ⁵⁶ arithmetic unit 870 (1) includes a 2 ⁵⁶ arithmetic value table 871 (1) and an 8-bit arithmetic value search unit 872 (1).

로 이진 나눗셈한 256 가지의 순환잉여검사 값을 저장하고 있다. 2 ⁵⁶ Arithmetic value table 871 (1) is a generator that defines (arbitrary 8-bit data x 2 ⁵⁶ ).

We store 256 different cyclic redundancy test values divided by binary.

The 8-bit arithmetic value search unit 872 (1) retrieves the cyclic redundancy check value for the input 8-bit using 2 ⁵⁶ arithmetic value table 871 (1), and retrieves the retrieved cyclic redundancy check value from the XOR operation unit ( 880).

2 ⁴⁸ operator 870 (2) receives the second upper 8 bits of the 32 bits from the 8-bit divider 860, and outputs the operation value for this to the XOR operator 880. The 2 ⁴⁸ arithmetic unit 870 (2) includes a 2 ⁴⁸ arithmetic value table 871 (2) and an 8-bit arithmetic value searching unit 872 (2).

로 이진 나눗셈한 256 가지의 순환잉여검사 값을 저장하고 있다. 2 ⁴⁸ Calculated Value Table 871 (2) is a generator that defines (arbitrary 8-bit data x 2 ⁴⁸ ).

We store 256 different cyclic redundancy test values divided by binary.

The 8-bit arithmetic value search unit 872 (2) retrieves the cyclic redundancy check value for the input 8-bit using 2 ⁴⁸ arithmetic value table 871 (2), and retrieves the retrieved cyclic redundancy check value from the XOR operator ( 880).

The ⁴⁰ operation unit 870 (3) receives the third upper 8 bits of the 32 bits from the 8 bit division unit 860, and outputs an operation value thereof to the XOR operation unit 880. The 2 ⁴⁰ arithmetic unit 870 (3) includes a 2 ⁴⁰ arithmetic value table 871 (3) and 2 ⁴⁰ 8-bit arithmetic value searching unit 872 (3).

로 이진 나눗셈한 256 가지의 순환잉여검사 값을 저장하고 있다. 2 ⁴⁰ Arithmetic value table 871 (3) is a generator that defines (arbitrary 8-bit data x 2 ⁴⁰ )

We store 256 different cyclic redundancy test values divided by binary.

The 8-bit arithmetic value search unit 872 (3) retrieves the cyclic redundancy check value for the input 8-bit using 2 ⁴⁰ arithmetic value table 871 (3), and retrieves the found cyclic redundancy check value. 880).

2 ³² operator 870 (4) receives the lowest 8 bits of 32 bits from the 8-bit divider 860, and outputs the cyclic redundancy check value to the XOR operator 880. The 2 ³² arithmetic unit 870 (4) includes a 2 ³² arithmetic value table 871 (4) and a 2 ³² 8 bit arithmetic value searching unit 872 (4).

로 이진 나눗셈한 256 가지의 순환잉여검사 값이 저장되어 있다. 2 ³² Arithmetic value table 871 (4) is a generator that defines (arbitrary 8-bit data x2 ³² ).

256 cyclic redundancy check values stored in binary are stored.

The 8-bit arithmetic value search unit 872 (4) retrieves the cyclic redundancy check value for the input 8-bit using 2 ³² arithmetic value table 871 (4), and retrieves the retrieved cyclic redundancy check value from the XOR operation unit ( 880).

The XOR operator 880 is 32 bits respectively from 2 ⁵⁶ operator 870 (1), 2 ⁴⁸ operator 870 (2), 2 ⁴⁰ operator 870 (3) and 2 ³² operator 870 (4). Receive a cyclic redundancy check value of 4 bytes and perform XOR operation. Thereafter, the result value of the XOR operation is output to the N-byte data determination unit 840.

The N-byte data determination unit 840 determines whether the operation on the N-byte data is finished by the 4-byte operation of the processor 830. When the operation on the N byte data is completed, the N byte data determination unit 840 transfers the XOR operation value received from the processing unit 830 to the output unit 850. On the other hand, when the operation on the N byte data is not completed, the N byte data determination unit 840 transfers the XOR operation value received from the processing unit 830 to the continuity maintaining unit 821 of the 4 byte division unit 820. .

The output unit 850 outputs an operation value received from the N-byte data determination unit 840.

6 is a conceptual diagram of an operation performed by a zero block calculator according to an embodiment of the present invention, and FIG. 7 is a block diagram of a zero block calculator according to an embodiment of the present invention.

Block operation units 600 (1) to 600 (n-1), except for the last block operation unit 600 (n), calculate a cyclic redundancy check value for the allocated N-byte data and then operate on the lower zero block. do.

The lengths of the following zero blocks are fixed to each of the block computing units 600 (1) to 600 (n-1) according to the positions of the allocated N-byte data. That is, a zero block of fixed size is followed by four bytes of C _n (n = 1,2,3, ...), the result of N byte data operation, and the cyclic redundancy check value (C _n ') is also fixed. It can be stored as a zero block operation value table.

Referring to FIG. 6, the block operation unit 600 (1) performing the operation on the most significant N bytes obtains the N byte operation value C ₁ allocated by the N byte operation unit 800 (1), and calculates the N byte operation value. Performs an XOR operation on C ₁ with a zero block of ((n-1) x N) bytes.

Then, ((n-1) x N) bytes have the upper four bytes based on the N byte operation value C ₁ , and the remaining [((n-1) x N)-4] bytes have a value of 0. Have

바이트의 제로 블록)에 대한 연산값 테이블을 가지면 메모리가 너무 커지므로(약 17GByte), 1 바이트씩 나눈 결과 (C_n1', C_n2', C_n3', C_n4')를 1 KByte 크기의 연산값 테이블 4 개에 저장한다. At this time, if it has a zero block operation value table for the high 4 bytes, that is (random 4 byte data

Having an operation table for zero blocks of bytes) makes the memory too large (approximately 17 GBytes), so the result of dividing by one byte (C _n1 ', C _n2 ', C _n3 ', C _n4 ') is 1 KByte in size. Stored in four value tables.

By performing an XOR operation of cyclic redundancy check values of the N-byte data C _n to block high-order 4 bytes of the N bytes of sub-zero and, dividing the XOR operation value by one byte, called the zero block operation values table one by one from the upper XOR When the operation is performed, the zero block operation value C _n '(n = 1, 2, 3, ... n-1) is obtained.

7 is a block diagram of a zero block calculator according to an exemplary embodiment of the present invention.

In the cyclic redundancy inspection system according to the embodiment of the present invention, except for the last block calculator 600 (n), the block calculators 600 (1) to 600 (n-1) include a zero block calculator and a zero block calculator. Since is the same except for the value stored in the zero block operation value table, only the first zero block operation unit 900 (1) will be described here.

Referring to FIG. 7, the zero block calculator 900 (1) includes an input unit 910, a four byte divider 920, a first byte zero block calculator 930 (1), and a second byte zero block calculator 930. (2)), a third byte zero block calculator 930 (3), a fourth byte zero block calculator 930 (4), an XOR operator 940, and an output unit 950.

The input unit 910 receives an operation value of the N-byte operation unit 800 (1), and performs an XOR operation with the zero block of the upper 4 bytes according to the allocated N-byte position. Thereafter, the result of performing the XOR operation is output ((n-1) x N) bytes to the 4-byte divider 920.

The 4 byte divider 920 divides the upper 4 bytes of the input ((n-1) x N) bytes into units of 1 byte, and divides each 1 byte into the first byte of the first byte zero block calculator 930. (1)), the second byte zero block calculator 930 (2), the third byte zero block calculator 930 (3), and the fourth byte zero block calculator 930 (4).

The first byte zero block operation unit 930 (1) receives the most significant 1 byte from the 4 byte division unit 920, and outputs an operation value thereof to the XOR operation unit 940. The first byte zero block operation unit 930 (1) includes a zero block operation value table 931 (1) and an operation value retrieval unit 932 (1).

바이트의 제로 블록을 정해진 제너레이터

로 나눗셈한 순환잉여검사 값을 저장하고 있다. The zero block arithmetic table 931 (1) is a random one-byte data

Generator defined for zero blocks of bytes

The cyclic redundancy test value divided by is stored.

The arithmetic value search unit 932 (1) retrieves the cyclic redundancy check value for the input 1 byte using the zero block arithmetic value table 931 (1), and retrieves the retrieved cyclic redundancy check value. Will output

The second byte zero block operation unit 930 (2) receives the second upper 1 byte from the 4 byte division unit 920, and outputs an operation value thereof to the XOR operation unit 940. The second byte zero block operation unit 930 (2) includes a zero block operation value table 931 (2) and an operation value retrieval unit 932 (2).

바이트의 제로 블록을 정해진 제너레이터

로 나눗셈한 순환잉여검사 값을 저장하고 있다. The zero block arithmetic value table 931 (2) is an arbitrary one-byte data.

Generator defined for zero blocks of bytes

The cyclic redundancy test value divided by is stored.

The arithmetic value search unit 932 (2) retrieves the cyclic redundancy check value for the input 1 byte using the zero block arithmetic value table 931 (2), and retrieves the retrieved cyclic redundancy check value. Will output

The third byte zero block operation unit 930 (3) receives the third upper 1 byte from the 4 byte division unit 920, and outputs an operation value thereof to the XOR operation unit 940. The third byte zero block operation unit 930 (3) includes a zero block operation value table 931 (3) and an operation value retrieval unit 932 (3).

바이트의 제로 블록을 정해진 제너레이터

로 나눗셈한 순환잉여검사 값을 저장하고 있다. The zero block arithmetic value table 931 (3) is a random one-byte data

Generator defined for zero blocks of bytes

The cyclic redundancy test value divided by is stored.

The arithmetic value search unit 932 (3) retrieves the cyclic redundancy check value for the input 1 byte using the zero block arithmetic value table 931 (3), and retrieves the retrieved cyclic redundancy check value. Will output

The fourth byte zero block operation unit 930 (4) receives the fourth upper 1 byte from the 4 byte division unit 920, and outputs an operation value thereof to the XOR operation unit 940. The fourth byte zero block operation unit 930 (4) includes a zero block operation value table 931 (4) and an operation value retrieval unit 932 (4).

바이트의 제로 블록을 정해진 제너레이터

로 나눗셈한 순환잉여검사 값을 저장하고 있다. The zero block arithmetic table 931 (4) is a random one-byte data

Generator defined for zero blocks of bytes

The cyclic redundancy test value divided by is stored.

The arithmetic value search unit 932 (4) retrieves the cyclic redundancy check value for the input 1 byte using the zero block arithmetic value table 931 (4), and retrieves the retrieved cyclic redundancy check value. Will output

The XOR operator 940 includes a first byte zero block operator 930 (1), a second byte zero block operator 930 (2), a third byte zero block operator 930 (3), and a fourth byte zero. Receive a cyclic redundancy check value of each 4 bytes from the block operator 930 (4), and performs an XOR operation. Thereafter, the result value of the XOR operation is transferred to the output unit 950.

The output unit 950 outputs an operation value received from the XOR operator 940.

Now, the cyclic redundancy inspection method according to an embodiment of the present invention will be described in detail.

8 is a view schematically showing a cyclic redundancy inspection method according to an embodiment of the present invention.

Upon receiving the information data (S101), the received information data is divided into N bytes (S102). The n block arithmetic units each perform N bytes, and perform operations on (n x N) bytes (S103).

Thereafter, when an operation value for (n x N) bytes is derived, it is determined whether the operation on the information data is completed using the (n x N) byte operation (S104). When the operation on the information data is completed by the (n x N) byte operation, the derived operation value is determined as the cyclic redundancy operation value for the received information data (S104).

On the other hand, when the operation on the information data is not completed, the process (S106) for maintaining the continuity with the subsequent information data is performed next, and then the operation on (n x N) bytes is performed again.

9 is a view showing in detail the cyclic redundancy inspection method according to an embodiment of the present invention.

Upon receiving the information data (S201), the received information data is divided into N bytes (S202). Subsequently, the n block arithmetic units each perform N bytes.

The n block arithmetic units perform operations on N bytes allocated to them and zero blocks below the N bytes. In this case, the block calculator that is allocated the last N bytes does not include the zero block.

Therefore, after dividing the received information data into N bytes, it is determined whether each N byte is the last N byte among the allocated N bytes (S203). If the allocated N bytes are the last N bytes, only N byte operations are performed (S204). However, if the allocated N bytes are not the last N bytes, after performing an N byte operation (S205), the operation for the zero block is performed (S206). Thereafter, an XOR operation is performed on the result value performed by each block operation unit (S207).

When the XOR operation value is derived, it is determined whether the operation on the information data is completed (S208). When the operation on the information data is completed by the (n x N) byte operation, the derived operation value is determined as a cyclic redundancy operation value for the received information data (S209).

On the other hand, when the operation on the information data is not completed, the next XOR operation is performed with 4 consecutive bytes (S210), and the operation on N bytes is performed.

10 is a diagram illustrating a method of calculating an N byte according to an embodiment of the present invention.

When the N byte arithmetic unit receives the N bytes allocated to itself, the N bytes are divided into 4 byte units (S301). Thereafter, 4 bytes are divided into 8 bit units (S302), and an operation value for each 8 bit is searched using an operation value table (S303). Thereafter, an XOR operation is performed on an operation value for each 8 bit (S304).

When the XOR operation value is derived, it is determined whether the operation on the N byte data is completed (S305). When the operation on the N byte data is completed by the 4-byte operation, the derived operation value is determined as the operation value on the received N byte data (S306).

On the other hand, if the operation on the N byte data is not completed, the next XOR operation is performed with 4 consecutive bytes (S307), and the operation for 4 bytes is performed.

11 is a diagram illustrating a zero block calculation method according to an embodiment of the present invention.

The operation value of the N-byte operation unit is input (S401). Thereafter, the input operation value is XORed with the upper 4 bytes of the zero block.

Thereafter, the XOR operation value of 4 bytes is divided by 1 byte unit (S403), and the zero block operation value for the divided 1 byte is searched (S404).

An XOR operation is performed on each divided zero block operation value in operation S405, and a determination is made as a zero block operation value in operation S406.

The embodiments of the present invention described above are not implemented only through the apparatus and the method, but may be implemented through a program for realizing a function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded. Implementation may be easily implemented by those skilled in the art from the description of the above-described embodiments.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

1 is a conceptual diagram of a cyclic redundancy inspection system and method according to an embodiment of the present invention.

2 is a schematic diagram of a cyclic redundancy inspection system according to an embodiment of the present invention.

3 is a block diagram of a cyclic redundancy inspection system according to an embodiment of the present invention.

4 is a conceptual diagram of an operation performed by an N-byte calculation unit according to an embodiment of the present invention.

5 is a block diagram of an N-byte calculation unit according to an embodiment of the present invention.

6 is a conceptual diagram of an operation performed by a zero block calculator according to an embodiment of the present invention.

7 is a block diagram of a zero block calculator according to an exemplary embodiment of the present invention.

8 is a view schematically showing a cyclic redundancy inspection method according to an embodiment of the present invention.

9 is a view showing in detail the cyclic redundancy inspection method according to an embodiment of the present invention.

10 is a diagram illustrating a method of calculating an N byte according to an embodiment of the present invention.

11 is a diagram illustrating a zero block calculation method according to an embodiment of the present invention.

Claims (13)

A divider for dividing the information data into units of N bytes (N > 0 or more natural numbers); And Each of the n block arithmetic units (n> 0 or more natural numbers) includes a processing unit performing an operation on the divided N bytes of information data and performing an operation on (n x N) bytes of information data. Cyclic Surplus Inspection System. The method of claim 1, Each of the n block calculators, An N-byte operation unit that performs an operation on the divided N-byte information data; And The divided N-byte information data lower byte on the basis of a result value of the N-byte calculator includes a zero block calculator that performs an operation on a zero block having a value of 0. Cyclic Surplus Inspection System. The method of claim 2, The processing unit, And an XOR operation unit performing an XOR operation on the operation values of the n block operations units. Cyclic Surplus Inspection System. The method of claim 3, An information data determination unit that determines whether the operation on the information data is completed by (n x N) byte operations of the processing unit; And Further comprising a continuity maintaining unit for performing an XOR operation with the lower data of the (n x N) bytes calculated in the processing unit and the result value of the processing unit Cyclic Surplus Inspection System. The method of claim 4, wherein The N byte calculation unit, A 4-byte divider for dividing the allocated N bytes in units of 4 bytes; And It includes a 4-byte processing unit for performing a cyclic redundancy check operation for the 4 bytes Cyclic Surplus Inspection System. The method of claim 5, The 4 byte processing unit, An 8-bit divider for dividing the 4 bytes received from the 4-byte divider into 8-bit data; And A plurality of 8-bit unit operation unit for calculating the cyclic redundancy check operation value of the divided 8-bit unit data Cyclic Surplus Inspection System. The method of claim 6, The cyclic redundancy check operation value of the 8-bit unit data in the 8-bit splitter is calculated using an operation value table in which the cyclic redundancy check value is stored. The method of claim 7, wherein Further comprising an N byte data determination unit for determining whether the operation on the N byte data is completed by the four byte operation of the 4-byte processing unit Cyclic Surplus Inspection System. The method of claim 8, The zero block calculator, A zero block 4 byte partition unit which performs an XOR operation with the upper 4 bytes of the zero block based on the operation result value of the N byte operation unit, and divides the upper 4 bytes of the result value of the XOR operation in units of 1 byte; A first byte zero block operation unit for calculating a cyclic redundancy check operation value for the most significant 1 byte divided by the zero block 4 byte division unit; A second byte zero block operation unit for calculating a cyclic redundancy check operation value for the second upper 1 byte divided by the zero block 4 byte division unit; A third byte zero block operation unit for calculating a cyclic redundancy check operation value for the third upper 1 byte divided by the zero block 4 byte division unit; And And a fourth byte zero block operation unit for calculating a cyclic redundancy check operation value for the fourth upper 1 byte divided by the zero block 4 byte division unit. Cyclic Surplus Inspection System. The method of claim 9, A first byte zero block operation unit, a second byte zero block operation unit, a third byte zero block operation unit, and a fourth byte zero block operation unit Surplus Inspection System. (a) receiving information data; (b) dividing the information data into units of N bytes; And (c) obtaining a cyclic redundancy value for (n x N) bytes. Cyclic surplus test method. The method of claim 11, In step (c), (i) performing an operation on N bytes of information data divided in step (b); (ii) performing an operation on a zero block in which the divided N-byte information data lower byte has a value of 0 based on the operation value of step (i); And (iii) performing an XOR operation on the operation value of step (ii) to obtain a cyclic redundancy operation value for (n x N) bytes. Cyclic surplus test method. The method of claim 12, (d) determining whether the operation on the information data is completed by operating on (n x N) bytes in the step (c); And (e) if it is determined in step (d) that the operation on the information data has not been completed, performing the operation for maintaining the continuity of the information data consecutive to the (n x N) bytes; Cyclic surplus test method.

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