KR20090036974A - Flash memory device - Google Patents

Abstract

A flash memory device is provided to process a short circuit block as a valid block by cutting a short circuit block with a repair fuse. A block switch selects a word line of the memory cell to be programmed in response to a row address from the outside. The block switch supplies a program voltage(Vpgm) or a pass voltage(Vpass) to the selected word line. One cell block is compose of a plurality of cell strings(200, 201.), a plurality of the bit line(BLe, BLo.), a plurality of word lines, a drain selection transistor(210) connected between the bit line and the cell string, and a common source line. A plurality of memory cells(231, 232, 233) sharing a single word line forms one page, and the drain selection transistor shares the drain select line(DSL). The source selection transistor shares a source selection line(SSL).

Description

Flash memory device

The present invention relates to a flash memory device, and more particularly, to a flash memory device capable of suppressing disturb during read operation using a self-boosting method.

With the recent development of the mobile and multi-media industries, it is possible to program and erase electrically, and to store flash data without erasing data even when power is not supplied. Demand is soaring. In addition, in order to develop a large-capacity memory capable of storing a large number of data, high integration technologies of memory cells have been developed.

Commercially available flash memories are classified into NOR type and NAND type according to the arrangement of the unit cells. In the case of the quinoa type, a channel hot electron (CHE) injection program mechanism is used, and the programming speed is high and the random access characteristic is excellent due to the characteristics of the cell array structure, but it has a disadvantage in terms of integration. On the other hand, the NAND type uses the F-N tunneling program mechanism, which results in slower program speeds and poor random access characteristics. Therefore, the NAND type can be used for mass storage devices in which random access time is not important.

1 is a diagram illustrating a cell string structure of a NAND flash memory device.

One string 100 includes a drain select transistor 110, a source select transistor 120, and a plurality of memory cells 131, 132, and 133. The memory cells 131, 132, and 133 are connected in series to a common drain / source region. The drain select transistor 110 is disposed between the bit line BL and the memory cells 131, 132, and 133, and the source select transistor 120 is disposed between the common source line CSL and the memory cells 131, 132, and 133. ) Is placed. Gates of the drain select transistor 110 are connected to each other by a drain select line DSL, and gates of the source select transistor 120 are connected to each other by a source select line SSL. The drain select transistor 110 and the source select transistor 120 are conventional MOS transistors, and the memory cells 131, 132, and 133 are formed of floating gate transistors.

The memory cells 131, 132, and 133 may be in an erased state or a programmed state. Memory cells in the erased state have a threshold voltage distribution that is relatively low, such as less than 0V. Memory cells in the programmed state, on the other hand, have a threshold voltage distribution that is relatively high, for example higher than 0V.

A read operation for determining which state the memory cell is in is typically performed in page units. For example, in order to determine the state of the memory cell transistor 132, first, the bit line BL of the cell string 100 having the selected memory cell transistor 132 is precharged to a size of, for example, 1V to 2V. precharge). Next, the drain select transistor 110 and the source select transistor 120 are turned on so that an electrical passage is formed in the selected cell string. In addition, a pass voltage Vpass is applied to the word lines of the remaining unselected memory cell transistors 131 and 133 so as to be turned on regardless of the states of the remaining memory cells 131 and 133. As the pass voltage Vpass increases, the amount of current flowing increases, which is advantageous in terms of sensing. However, when the pass voltage Vpass increases, a read in which the memory cell transistors 131 and 133 that are not selected unnecessarily in the read process is programmed. Read disturb may occur. A bias of a read voltage Vread, for example, 0V is applied to the word line of the selected memory cell transistor 132.

Except for the selected memory cell 132, since all the other transistors of the cell string 100 are turned on, current flows through the cell string 100 in accordance with the selected memory cell 132. It will not flow. When the selected memory cell 132 is in an erased state, since the selected memory cell 132 is turned on, current flows through the entire cell string 100, thereby discharging the charges charged in the bit line BL. The precharged voltage drops to 0V. On the other hand, when the selected memory cell 132 is in a programmed state, since the selected memory cell 132 is turned off, no current flows in the cell string 100, and accordingly, the voltage precharged to the bit line BL. This remains the same. As described above, it may be determined whether the selected memory cell 132 is in an erased state or a programmed state according to whether or not the voltage precharged to the bit line BL has fallen to 0V.

On the other hand, the NAND flash memory has a high pass voltage for all other word lines except the word line of the memory cell to be programmed in order to prevent slight program disturbance of the cells other than the cell to be programmed during the program operation. Vpass) is applied. However, despite this method, there is still a slight program interference, which has been a limiting factor of the number of programs of the NAND flash memory. In particular, during programming, a high program voltage of 15V to 20V is applied to a word line to which a cell to be programmed is connected. In this case, other memory cells that share the word line and do not want to program may also be programmed due to the high word line voltage. .

In order to prevent this, a self-boosting method is provided in which a ground voltage (0 V) is applied to a bit line of a memory cell to be programmed and a supply voltage (Vcc) is applied to a bit line of a memory cell that is not programmed. Used. In this voltage state, the selected transistor is turned on and the ground voltage is transferred to the channel of the memory cell to be programmed to perform the program operation. The select transistor of the unselected bit line is turned off to turn off all memory cells connected to the unselected bit line. It becomes a floating state. Using the self-boosting method, the program prevention voltage can be obtained by simply applying the power supply voltage (Vcc) to the bit line, thereby reducing the program disturbance.

This self-boosting scheme can also be used for read operations.

In the read operation using self-boosting, a voltage equal to or greater than the power supply voltage Vcc is applied to the unselected bit line and the unselected source line, and the selected source line is grounded. Boosting the channel of the memory cell to which the pass voltage is applied to the gate among the memory cells connected to the unselected bit line reduces the potential difference between the gate and the channel, thereby suppressing the occurrence of the read disturb phenomenon. That is, even if a high pass voltage of 5.5V or more is applied to the gate of the memory cell, only a bias equal to the difference between the pass voltage and the power supply voltage Vcc is applied, thereby preventing unwanted programming by the pass voltage during a read operation. do.

In order to perform the self-boosting read operation smoothly, the common source line CSLe of the even bit line BLe and the common source line CSLo of the odd bit line BLO are separated from each other. That is, when the selected memory cell is connected to the even bit line, when all the memory cells 440 connected to the odd bit line BLo are erased, the power supply voltage Vcc applied to the odd bit line BLo. The bias may be discharged through the common source line CSL. However, when the common source line of the even bit line and the common source line of the odd bit line are separated, the common source line CSLe of the even bit line BLe is grounded, but the common source line of the odd bit line BLo is grounded. CSLo is a phenomenon in which the voltage applied to the odd bit line BLo is discharged through the common source line CSLo by applying a bias equal to or greater than the power supply voltage Vcc applied to the odd bit line BLo. This will not happen.

However, in the case of using the self-boosting read method, the common source line CSLe of the even bit line and the common source line CSLo of the odd bit line are caused by a defect generated during the source line or the wiring process. If a short occurs between the source line and the bit line of the even or odd bit line, the self-boosting method may not be used, and chip failure may occur. As semiconductor memory devices are highly integrated, the cell size is reduced, and the gap between the bit line and the source line or the gap between the source line and the source line is also reduced, and this short circuit problem is inevitable, and the yield is seriously degraded.

An object of the present invention is to provide a NAND flash memory device such that chip failure does not occur even if a short circuit occurs between a common source line or between a source line and a bit line.

In accordance with one aspect of the present invention, a flash memory device includes a plurality of cell strings including a drain select transistor, a plurality of cell transistors, and a source select transistor connected in series, and a plurality of cell strings connected with the cell strings. A memory cell array having a plurality of memory cell blocks each including first and second bit lines; And a block switch for selecting a memory block to be driven among the plurality of memory blocks and applying a driving voltage to the selected memory block, wherein a source select transistor of a cell string connected to the first bit line is connected to a first source line. The source select transistor of the cell string connected to the second bit line is connected to a second source line, and the first source line and the second source line are switched by the block switch, respectively.

In the present invention, the block switch includes a block selection circuit for applying a block selection signal for selecting a memory block to be driven and a switching operation for applying a predetermined voltage through a global word line to a word line in the memory block. It may include pass transistors to perform.

The block selection circuit may include a block repair fuse for repairing a block in which a failure occurs.

The pass transistors may include a drain select transistor, a source select transistor, a cell select transistor, a first source line select transistor, and a second source line select transistor.

A gate of the first source line transistor may be connected to a block word line, a drain thereof may be connected to a global first source line, and a source may be connected to a local first source line.

A gate of the second source line transistor may be connected to a block word line, a drain thereof may be connected to a second global source line, and a source may be connected to a second local source line.

The first and second source lines may be connected to different block switches, respectively.

According to the present invention, an even source line connected to an even bit line and an odd source line connected to an odd bit line are divided into block units, and connected to a block switch to between an even source line and an odd source line or between a source line and a bit line. When a short circuit occurs, the block repair fuse of the block in which the short circuit occurs can be processed as an invalid block, thereby eliminating the problem that a chip failure occurs and the entire chip becomes unusable.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

In order to perform the self-boosting read operation, a voltage equal to or greater than the power supply voltage Vcc is applied to the unselected bit line and the unselected source line, and the selected source line is grounded. However, shorts may occur between the even common source line CSLe and the odd common source line CSLo or between the source line and the bit line due to a defect generated during the source line forming process or the metal wiring line forming process. In this case, the self-boosting method cannot be used and chip failure will occur. According to the present invention, a chip failure is performed by forming an even common source line CSLe as a block source line and an odd common source line CSLo as a block source line, and treating a block in which a short circuit occurs as an invalid block by block repair. It prevented the occurrence and improved the production yield.

2 is a view schematically showing the configuration of a NAND flash memory device.

The NAND flash memory device includes a plurality of cell blocks and a block switch for selecting a block to be driven among the plurality of cell blocks.

The block switch selects a word line of a memory cell to be programmed in response to a row address input from the outside, and the program voltage Vpgm or the pass voltage Vpass transferred from the word line driving circuit (not shown). Is applied to the selected word line. The block switch will be described in detail later.

One cell block includes a plurality of cell strings 200 and 201 .., a plurality of bit lines (BLe, BLo ..), a plurality of word lines, a cell string connected in series while a plurality of memory cells share a source / drain. And a drain select transistor 210 connected between the bit line and the bit line, and a source select transistor 220 connected between the cell string and the common source line. A plurality of memory cells 231, 232, and 233 sharing one word line constitute one page. The drain select transistor 210 shares the drain select line DSL, and the source select transistor 220 shares the source select line SSL. The source select transistor 220 of each cell string is connected to a common source line. Although two bit lines and cell strings are shown in the drawing, a plurality of the bit lines and cell strings are disposed in the memory cell block.

Meanwhile, in the process of performing a read operation on the memory cell transistors of the even bit line BLe by using a self boosting method, all of the memory cell transistors connected to the odd bit line BLo are erased. In this case, that is, when all of the cell transistors connected to the odd bit line BLo are conducted, the power source voltage Vcc applied to the odd bit line BLo may be discharged to the common source line CSL which is grounded. Therefore, in order to prevent this, the common source line CSLo connected to the odd bit line BLO is separated from the common source line CSLe connected to the even bit line BLe. The common source line CSLe connected to the selected even bit line BLe is grounded, and the power source voltage Vcc applied to the odd bit line BLO is applied to the common source line CSLo connected to the odd bit line BLO. ) Apply voltage of magnitude.

In particular, the separated common source lines CSLe and CSLo are connected to a block switch and switched by a pass transistor in the block switch. In the block switch, a fuse (not shown) is provided to repair a bad block when it occurs. If a short occurs between the even common source line CSLe and the odd common source line CSLo, or between the common source line CSLe and CSLo and the bit lines BLe and BLo, By using a block repair fuse inside the block switch, the block can be treated as an invalid block, thereby preventing the entire chip from being used by preventing other blocks that do not have a short circuit.

3 is a diagram illustrating the structure of a block switch of a NAND flash memory device.

The block switch outputs a block select signal that turns on the pass transistors of the selected block and turns off the pass transistors of the unselected block. The block switch generates a block select signal with a potential higher than the voltage input through the global word line to stably transfer the voltage input from the predecoder (not shown) through the global word line. Thus, the selected block is supplied with a select voltage or a non-select voltage through a plurality of global word lines, a plurality of pass transistors and word lines. On the other hand, since the pass transistor is turned off in the unselected block, no voltage is transmitted through the plurality of global word lines, and the word lines remain floating.

The block switch includes a block selection circuit 310 and a pass transistor 320.

The pass transistor 320 performs a switching operation for applying a predetermined voltage through the global word line GWL to the word line WL in the cell block 330. The pass transistor 320 includes a drain select transistor 321, a cell select transistor 322, a source select transistor 323, an even common source line transistor 324, and an odd common source line transistor 325. It is composed.

The block selection circuit 310 includes a control logic circuit 311, a precharge circuit 312, and a discharge circuit 313.

The control logic circuit 311 includes NAND gates 311a and 311b. When the input pre-decoded signals XA, XB, XC, and XD are all at a high level, the NAND gate 311a outputs a low level logic signal LOG. When any one of the pre-decoded signals XA, XB, XC, and XD is at a low level, the NAND gate 311a outputs a high level logic signal LOG.

When both the logic signal LOG and the program control signal PGM are at a high level, the NAND gate 311b outputs the block select signal BSel at a low level. When either one of the logic signal LOG and the program control signal PGM is at the low level, the NAND gate 311b outputs the block select signal BSel at a high level. The program control signal PGM is maintained at a low level only during the set precharge period, and then goes back to a high level. A drain of the nMOS transistor N1 is connected to an output terminal of the NAND gate 311b, and a source of the nMOS transistor N1 is connected to the block word line BLKWL. The nMOS transistor N1 is turned on or off in response to the precharge control signal PRE input to its gate. The precharge control signal PRE is enabled during the precharge operation. When the nMOS transistor N1 is turned on, the block select signal BSel is transferred to the block word line BLKWL.

The precharge circuit 312 includes a switching circuit and a clipping circuit.

The switching circuit includes nMOS transistors N3 and N4. The drain of the nMOS transistor N3 is connected to the input voltage Vpp and its source is connected to the drain of the nMOS transistor N4. The source of the nMOS transistor N4 is connected to the block word line BLKWL. The address coding signals GA and GB are input to the gates of the nMOS transistors N3 and N4, respectively. The address coding signals GA and GB are signals for selecting memory cells whose program is controlled by the block switch 310. When the nMOS transistors N3 and N4 are turned on, the block word line BLKWL is precharged to the operating voltage level Vpp. The clipping circuit includes nMOS transistors N5 and N6. When the voltage level of the block word line BLKWL rises above the set voltage level, the nMOS transistors N5 and N6 maintain the voltage level of the block word line BLKWL at the set voltage level.

The discharge circuit 313 includes a NAND gate 313a and an nMOS transistor N2. The NAND gate 313a outputs a control signal CTL in response to the block select signal BSel and the enable signal EN. When both the block select signal BSel and the enable signal EN are at the high level, the NAND gate 313a outputs the control signal CTL at the low level. When either one of the block selection signal BSel and the enable signal EN is at the low level, the NAND gate 313a outputs the control signal CTL to the high level. The enable signal EN is a signal maintained at a high level when the block switch 310 operates.

The control signal CTL is input to the gate of the nMOS transistor N2, and the drain of the nMOS transistor N2 is connected to the block word line BLKWL and the source is connected to ground, respectively. When the nMOS transistor N2 is turned on, the block word line BLKWL is discharged to the ground level.

The control logic circuit 311 includes a block repair fuse 311c for a block repair. The block repair fuse 311c is capable of physically cutting externally when a bad block occurs. If a short circuit occurs between the even source line and the odd source line or between the source line and the bit line during the self-boosting read operation, the block repair fuse 311c of the block is cut. When the block repair fuse 311c is cut off, the logic signal LOG cannot be transmitted to the NAND gate 311b, so the NAND gate 311b outputs a low level block select signal BSel, and the NAND gate ( 313a outputs a high level control signal CTL. Therefore, since the discharge transistor N2 is always turned on, the block does not operate.

Gates of the pass transistor 320 made of high voltage nMOS transistors are connected to the block word line BLKWL. The pass transistors are turned on when the block word line BKWL is precharged to the operating voltage level Vpp. The drain and the source of the nMOS transistor 321 are connected to the global drain select line GDSL and the local drain select line DSL, respectively. A drain and a source of the nMOS transistor 322 are connected to the global word line GWL and the local word line WL, respectively. The drain and the source of the nMOS transistor 323 are connected to the global source select line GSSL and the local source select line SSL, respectively. The drain and the source of the nMOS transistor 324 are connected to the global even source line GSLe and the local even source line SLe, and the drain and the source of the nMOS transistor 325 are local to the global odd source line GSLo and the local. It is connected to the odd source line SLo, respectively.

As such, the even source line connected to the even bit line and the odd source line connected to the odd bit line are divided into block units and connected to the block switch to cause a short circuit between the even source line and the odd source line or between the source line and the bit line. In this case, by cutting the block repair fuse of the block in which the short circuit occurs, the chip can be treated as an invalid block, thereby eliminating the problem that a chip failure occurs and the entire chip becomes unusable.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

1 is a diagram illustrating a cell string structure of a NAND flash memory device.

2 is a diagram illustrating a configuration of a NAND flash memory device.

3 is a diagram illustrating the structure of a block switch of a NAND flash memory device.

Claims (7)

The memory cell block includes a plurality of cell strings formed by connecting a drain select transistor, a plurality of cell transistors, and a source select transistor in series, and a plurality of first and second bit lines connected to the cell strings. Connected memory cell arrays; And A block switch for selecting a memory block to be driven among the plurality of memory blocks and applying a driving voltage to the selected memory block; A source select transistor of a cell string connected to the first bit line is connected to a first source line, a source select transistor of a cell string connected to the second bit line is connected to a second source line, And the first source line and the second source line are each switched by the block switch. The method of claim 1, wherein the block switch, A block selection circuit for applying a block selection signal for selecting a memory block to be driven; And pass transistors for performing a switching operation to apply a predetermined voltage through a global word line to a word line in the memory block. The method of claim 2, And the block selection circuit includes a block repair fuse for repairing a block in which a failure occurs. The method of claim 2, The pass transistors, A flash memory device comprising a drain select transistor, a source select transistor, a cell select transistor, a first source line select transistor, and a second source line select transistor. The method of claim 4, wherein And a gate is connected to a block word line, a drain thereof is connected to a global first source line, and a source is connected to a local first source line. The method of claim 4, wherein And a gate is connected to a block word line, a drain thereof is connected to a second global source line, and a source is connected to a second local source line. The method of claim 1, And the first and second source lines are connected to different block switches, respectively.

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