KR20090032785A - Apparatus for corelating pgs signal - Google Patents

Abstract

A GPS signal correlation apparatus is provided to reduce the software operation quantity of a main process unit by processing a part of operations for the GPS signal correlation. A GPS signal correlation apparatus includes an RF module(10) and a main process unit(20). An RF module includes an RF processing unit(12) and a first signal converter(13). The RF processing unit converts the GPS signal into the digital intermediate frequency. The first signal converter blocks digital data into the prescribed unit and converts the data into one value. The main processor unit operates the start-up phase of a carrier at each block. The main processor unit includes a second signal converter(21). The second signal converter outputs I and Q correlation values.

Description

JPOS signal correlator {APPARATUS FOR CORELATING PGS SIGNAL}

The present invention relates to an apparatus for calculating a correlation of a GPS signal, and more particularly, a correlation value may be determined using a preset map according to data and a phase difference included in the GPS signal using a preset map. The present invention relates to a GPS signal correlator capable of reducing the time required for correlation computation by reducing the amount of software computation.

In general, a GPS (Global Positioning Syster) receiver is applied to determine a position of an object by receiving a GPS signal including time information and position information from a satellite, and detecting and recognizing information included in the GPS signal. In order to improve the accuracy of the positioning, the GPS receiver must be able to compensate the phase error of the carrier accurately, for this purpose, it is essential to consider such a phase error in the correlation calculation of the GPS signal.

In general, a GPS (Global Positioning System) receiver acquires and tracks satellite signals received from a large number of GPS satellites, and calculates the distance between satellites and receivers, extracts navigation data, and uses geometric trigonometry. Estimate the position of the receiver. Compensation for the frequency and phase of the replica carrier and the delay of the replica C / A code by correlating the received GPS satellite signal with the radiation signal generated by the receiver for signal acquisition and tracking. It is essential to do.

The GPS receiver can be broadly classified into a hardware GPS receiver and a software GPS receiver. A typical software GPS receiver is a RF module composed of hardware that down converts a GPS signal of an RF frequency band received from an antenna to an intermediate frequency (IF) band and digitizes it, and a digital intermediate frequency signal is correlated with a radiation signal. It consists of a signal processing unit consisting of software that performs signal acquisition and tracking, and extracts navigation data using these results and estimates navigation solutions. The signal processor may be implemented in software in the GPS receiver main process unit.

This software GPS receiver, unlike the hardware, cannot perform parallel operation because the signal processing unit is composed of software, and must perform processes such as correlation calculation, signal tracking, navigation data extraction, and navigation solution estimation of intermediate frequencies. Therefore, in order to secure positional information and time information in real time, high-speed data transmission and calculation of several tens of mega samples per second (MSPS) is required in a signal processing unit composed of software. In particular, the signal processor is heavily loaded with correlation operations that require a large amount of data processing.

Therefore, the software GPS receiver has an excessively large amount of data to be calculated by the main process unit, and requires high-speed computation to obtain real-time position information. Therefore, a load that is added to the signal processing unit is very large. This may make it impossible to obtain real-time location information by the GPS receiver and may lead to an increase in manufacturing cost due to the replacement of a high-performance processor to implement a signal processor.

The present invention relates to a GPS signal correlator that can reduce the load of the software processing by the main process unit of the GPS receiver, thereby reducing the load on the main process unit and improving the accuracy of the position signals obtained.

The present invention as a means for solving the above technical problem,

The RF processor converts the GPS signal received from the antenna into a digital intermediate frequency signal consisting of two bits, and blocks the two bits of digital data in a predetermined unit and performs mapping by using a first predetermined map. An RF module having a first signal converter converting the blocked data into a single value; And

A second step of calculating a start phase of a carrier for each block and outputting I and Q correlation values through mapping using a value converted by the first signal converter and a second preset map having the start phase as an index; Main process unit with signal converter

It provides a GPS signal correlation device comprising a.

Preferably, the first signal converter comprises: a blocker for blocking the bitstream of the digital intermediate frequency signal in units of 2 bytes; An intermediate frequency removing unit for removing the intermediate frequency components by mixing the intermediate frequencies included in the blocked digital intermediate frequency signal and an integration unit for generating the single value by summing the digital data from which the intermediate frequency components are removed. have.

The first signal converter may be implemented in the form of FPGA in the RF module.

The apparatus of claim 1, wherein the second signal converter comprises: a carrier DCO for calculating a starting phase of a carrier for each block; And a second map that stores preset I and Q correlation values according to the value converted by the first signal converter and the start phase calculated by the carrier DCO. The second map may output I and Q correlation values through a mapping using the value converted by the first signal converter and the starting phase calculated by the carrier DCO as an index.

According to the present invention, it is possible to reduce the amount of software calculation of the main process unit by processing a part of the calculation necessary for the correlation of the GPS signal in the RF module.

In addition, this improves the processing speed of the GPS signal, and has the effect of obtaining more accurate location information and time information from the GPS signal.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiment of this invention is provided in order to demonstrate this invention more completely to the person skilled in the art to which this invention belongs. Therefore, it should be noted that the shape and size of the components shown in the drawings may be exaggerated for more clear explanation.

1 is a block diagram of a GPS correlation apparatus according to an embodiment of the present invention.

Referring to FIG. 1, the GPS correlation device according to the embodiment of the present invention largely includes an RF module 10 and a main process unit 20.

The RF module 10 includes an RF processor 12 for converting a GPS signal received from an antenna into a continuous digital intermediate frequency signal of 2 bits, and blocks the 2 bits of digital data in a predetermined unit, It may include a first signal converter 13 for converting the blocked data into a value through mapping using a first preset map.

The main process unit 20 calculates a start phase for each preset block interval, and uses a value converted by the first signal converter 13 and a second preset map having the start phase as an index. It may include a second signal converter 21 for outputting the I and Q correlation values through the mapping. The first signal converter 13 may be implemented in the form of a field-programmable gate array (FPGA) that can be designed by a user in an RF module. In addition, the I and Q correlation values output from the second signal converter 21 are transmitted to the correlation and navigation information calculator 22 to compensate for the phase error of the carrier, thereby generating accurate position information and time information. Can be.

FIG. 2 is a block diagram showing a first signal converter (13 in FIG. 1) in the GPS correlation apparatus according to the embodiment of the present invention.

Referring to FIG. 2, the first signal converter 13 according to an embodiment of the present invention blocks the bitstream of the digital intermediate frequency signal output from the RF processor (12 of FIG. 1) in units of two bytes. The intermediate unit 131, an intermediate frequency removing unit 132a for removing an intermediate frequency component by mixing intermediate frequencies with each of the 2-bit digital data included in the blocked data, and summing digital data from which the intermediate frequency components have been removed, It may include a first map 132 having an integration unit 132b for generating the one value.

3 is an exemplary diagram illustrating an example of a data block formed by the blocker 131 illustrated in FIG. 2.

As shown in FIG. 3, the intermediate frequency signal converted by the RF processing unit 12 in the RF module (10 in FIG. 1) is two bits of digital data including one bit representing a sign and one bit representing a magnitude. Has a continuously connected form. In one embodiment of the present invention, the two-bit digital data blocks a continuous digital intermediate frequency signal in units of blocks having a predetermined size, for example, eight digital data (16 bits total = 2 bytes total) consisting of 2 bits. . The blocked digital data is then integrated by a totalizer (132b in FIG. 2) into a single value, and the blocks are grouped again into a predetermined number of units so that the phase error is determined by the carrier DCO (211 in FIG. 4) for each unit. Can be calculated.

4 is a block diagram illustrating a detailed configuration of the second signal converter 21 of FIG. 1.

Referring to FIG. 4, a second signal converter (21 in FIG. 1) according to an embodiment of the present invention includes a carrier DCO 211 for calculating a start phase of a carrier for each block, and the first signal converter. And a second map 212 that stores a value converted by (13 of FIG. 1) and a preset I and Q correlation value according to the starting phase calculated by the carrier DCO.

Hereinafter, the operation and effects of the present invention will be described in more detail with reference to FIGS. 1 to 4.

The GPS signal of the RF frequency transmitted from the GPS satellite is received by the antenna ANT, and the received GPS signal is transmitted to the RF module 10. The amplifier 11 (low noise amplifier or gain control amplifier) in the RF module 10 amplifies the received GPS signal with an appropriate gain, and the amplified GPS signal is transmitted to the RF processor 12.

The RF processor 12 converts the GPS signal of the RF frequency into a signal of the intermediate frequency IF through frequency mixing, and then converts the GPS signal converted to the intermediate frequency through a digital sampling into a digital signal. In this case, as shown in FIG. 2, the converted digital GPS signal may have a form in which two bits of digital data consisting of one bit representing a code and one bit representing a size are continuously connected. The digital GPS signal generated by the RF processor 12 is transmitted to the first signal converter 13 in the RF module 10.

The first signal converter 13 blocks the digital GPS signal such that a predetermined number of two bits of digital data is included in the digital GPS signal. This blocking process may be performed by the blocking unit 131. For example, as shown in FIG. 2, the blocker 131 may block eight digital data into one block in a digital GPS signal in which two bits of digital data are continuously connected. That is, the blocker 131 blocks the input digital GPS signal in units of eight two-bit digital data. Therefore, one block includes 16 bits (2 bytes) in total. The digital GPS signal blocked by the first signal converter 13 is transmitted to the first map 132 in the first signal converter 13.

The first map 132 may be understood as a map that maps eight digital data included in one block of the blocked digital GPS signal to one value. For the mapping by the first map 132, first, the intermediate frequency component is removed from the digital GPS signal blocked by the intermediate frequency removing unit 132a included in the first map 132. The intermediate frequency remover 132a mixes intermediate frequency components with the digital GPS signal to downconvert the intermediate frequency to baseband. The digital GPS signal from which the intermediate frequency is removed by the intermediate frequency remover 132a is transmitted to the integration unit 132b.

The integrating unit 132b maps the blocks including the digital GPS signal from which the intermediate frequency component is removed by the intermediate frequency removing unit 132a to one value. For example, the adder 132b adds eight digital data included in one block to generate one value. In this case, the one value for mapping one block constituting the digital GPS signal may be generated by mapping the sum of the sum of eight digital data in the block to another value according to the sum of the sum values. . One value corresponding to this one block may be one of the indices used for the second mapping made by the second signal converter 21. As described above, since the eight digital data are converted into one value by the first signal converter 13, the signal output from the first signal converter 13 is a signal whose sampling frequency is reduced to 1/8. do. Since this sampling frequency is reduced, i.e., the down-converted signal is transmitted to the main process unit 20, the throughput of the main process unit 20 can be significantly reduced.

The second map 212 in the main process unit 20 previously stores I (Inphase) and Q (Quadrature-phase) correlation values according to the index value. As one of the index values of the second map 212, the down-converted value output from the first signal converter 13 may be used.

Meanwhile, the carrier DCO 211 may be applied to remove different Doppler for each satellite. The carrier DCO 211 calculates a start phase of a carrier for each block in which the digital data is blocked. The starting phase calculated by the carrier DCO 211 is transferred to the second map 212, which may use this starting phase as one of the index values.

Finally, the second map 212 corresponds to this index by using one value output by the first signal converter 13 and the starting phase calculated by the carrier DCO 211 as an index. Output the I and Q correlation values. That is, the second map 212 is a mapping using a preset map of one value output by the first signal converter 13 which is two indices and the start phase calculated by the carrier DCO 211. Outputs I correlation and Q correlation through.

The main process unit 20 uses the I and Q correlation values output from the second signal converter 21 to perform correlation and navigation to obtain navigation information by GPS satellites, that is, location information and time information. The information calculating unit 22 may further include. The correlation and navigation information calculation unit 22 may obtain accurate position and time information by compensating for the phase error using the I and Q correlation values output from the second signal converter 21.

As described above, according to the present invention, a part of the calculation required for correlation of the GPS signal may be processed in the RF module 10. That is, the first signal converter 13 in the RF module 10 performs data blocking, frequency downconversion, and indexing with one value for correlation, thereby reducing the amount of processed data. By transferring to the main processor 20, the load of the main processor 20 can be significantly reduced. In addition, since I and Q correlation values are obtained using a mapping technique through a map, the processing speed of the GPS signal may be improved, and more accurate location information and time information may be obtained from the GPS signal.

1 is a block diagram of a GPS correlation apparatus according to an embodiment of the present invention.

2 is a block diagram showing a detailed configuration of a first signal converter according to an embodiment of the present invention.

3 is an exemplary diagram showing an example of a data block formed by a blocker according to an embodiment of the present invention.

4 is a block diagram illustrating a detailed configuration of a second signal converter according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10: RF module 11: amplifier

12: RF processor 13: first signal converter

131: block unit 132: first map

132a: Intermediate Frequency Rejector 132b: Integrator

20: main process unit 21: second signal conversion section

211: carrier DCO 212: second map

22: correlation and navigation information calculation unit

Claims (4)

The RF processor converts the GPS signal received from the antenna into a digital intermediate frequency signal consisting of two bits, and blocks the two bits of digital data in a predetermined unit and performs mapping by using a first predetermined map. An RF module having a first signal converter converting the blocked data into a single value; And A second step of calculating a start phase of a carrier for each block and outputting I and Q correlation values through mapping using a value converted by the first signal converter and a second preset map having the start phase as an index; Main process unit with signal converter GPS signal correlation device comprising a. The method of claim 1, wherein the first signal converter, A blocker for blocking the bitstream of the digital intermediate frequency signal in units of 2 bytes; A first frequency unit having an intermediate frequency remover for mixing an intermediate frequency included in the blocked digital intermediate frequency signal to remove an intermediate frequency component, and an adder configured to add the digital data from which the intermediate frequency component is removed to generate the single value; GPS signal correlator comprising a map. The method of claim 1, wherein the first signal converter, GPS signal correlator, characterized in that implemented in the form of FPGA in the RF module. The method of claim 1, wherein the second signal converter, A carrier DCO for calculating a starting phase of a carrier for each block; A second map for storing a preset I and Q correlation value according to the value converted by the first signal converter and the start phase calculated by the carrier DCO, And the second map outputs I and Q correlation values through mapping using the value converted by the first signal converter and the start phase calculated by the carrier DCO as an index. .

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