KR20090031193A - Method of forming silicon nitride at low temperature, charge trap memory device comprising crystalline nano dots formed using the same and method of manufacturing charge trap memory device - Google Patents

Abstract

A method of forming silicon nitride at low temperature, charge trap memory device comprising crystalline nano dots formed using the same and method of manufacturing charge trap memory device are provided to prevent the increment of the leakage current even though the thickness of the nitride film is thin. The substrate is loaded in the chamber of the silicon nitride deposition apparatus(100). The silicon nitride deposition apparatus includes a filament. The temperature of filament is increased to the dissociation temperature of the reaction gas(110). The reaction gas for the silicon nitride formation is supplied to the chamber(120). Therefore, the crystalline silicon nitride is formed in the top of the substrate. At this time, the temperature of filament is maintained by 1400°C-2000°C. The pressure of the chamber maintains in the number torr~ several tens torr.

Description

Method of forming silicon nitride at low temperature, charge trap memory device comprising crystalline nano dots formed using the same and method of manufacturing charge trap memory device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low temperature silicon nitride forming method, a charge trap type memory device comprising a crystalline nano dot formed by the method, and a manufacturing method thereof.

Silicon nitride films have good dielectric constant and good oxidation resistance. As a result, silicon nitride films are applied to microelectronic devices, for example as barrier layers or gate insulating layers.

When the crystalline silicon nitride film is used as the gate insulating film, the dielectric constant of the gate is increased, and impurities in the gate material can be prevented from diffusing to the substrate.

A silicon nitride film is formed on Si (100). The silicon nitride film is mainly formed by plasma-enhanced CVD or low-pressure CVD.

However, the silicon nitride film formed in this way is structurally amorphous. Thick amorphous silicon nitride films have a moderately low leakage current. However, when the thickness of the amorphous silicon nitride film becomes thin, for example, 50 mA or less, the leakage current may increase.

On the other hand, when a doped polysilicon gate exists on the Si (100) substrate, and SiO2 is present as a gate insulating film between the doped polysilicon gate and the Si (100) substrate, a doped material is removed from the doped polysilicon gate. It may be diffused to the Si (100) substrate through SiO2. This diffusion problem increases as the thickness geometry of the gate insulating layer decreases, and as a result, device characteristics may deteriorate in the channel region.

On the other hand, when the gate insulating layer is amorphous silicon nitride, it is possible to prevent the doping material, for example, boron from diffusing into the Si (100) substrate. However, since the interface between the gate and the Si (100) substrate becomes amorphous silicon nitride, electron flow may be interrupted in the channel of the active semiconductor device, which deteriorates the characteristics of the semiconductor device than when SiO 2 is used as the gate insulating film. Can be.

On the other hand, when the SiO2 film is used as the gate insulating film and the thickness thereof is thin, it is difficult to reduce the thickness of the SiO2 film because the leakage current beyond the allowable value increases due to electron tunneling between the gate and the drain of the transistor.

However, since the silicon nitride film has a bulk dielectric constant larger than that of the SiO 2 film, a thick silicon nitride having the same capacitance density as the thin SiO 2 film can be used.

However, as described above, the silicon nitride formed by the method known to date is structurally amorphous, and when the thickness thereof is thin, the leakage current may be increased.

The technical problem to be solved by the present invention is to improve the above-described conventional problems, it is possible to prevent the flow of electrons in the channel of the active semiconductor device, and to prevent the leakage current increases even if the thickness is thin. The present invention provides a low temperature silicon nitride forming method capable of forming a crystalline silicon nitride film or nano dots even on a low temperature substrate on which crystalline silicon nitride could not be formed.

Another technical problem of the present invention is to provide a charge trapping memory device including a crystalline nano dot formed by this method and a method of manufacturing the same.

In order to solve the above technical problem, the present invention provides a first step of loading a substrate into a chamber of a silicon nitride deposition apparatus including a filament, the temperature of the filament to a predetermined temperature that can dissociate the reaction gas to be introduced And a third step of supplying a reaction gas for forming silicon nitride to the chamber, wherein the temperature of the filament is maintained at 1400 ° C.-2000 ° C., and the pressure of the chamber in the third step is By maintaining torr-tens of torr, a silicon nitride forming method for forming crystalline silicon nitride on the substrate is provided.

In this forming method, the substrate may be maintained at 500 ° C-700 ° C.

The pressure of the chamber may be 4torr-40torr.

The reaction gas is a first source gas for supplying silicon (Si) and a second source gas for supplying nitrogen (N), and the first source gas is monosilane (SiH 4), disilane, trisilane, or tetra May be silane.

When the first source gas is 20% mono silane and the second source gas is ammonia gas (NH 3), the flow ratio of the first and second source gases is 1:50, 1: 100. Or 1: 200.

In order to achieve the above technical problem, the present invention is a charge trapping memory device including a tunneling film, a charge trap layer, a charge blocking layer and a gate electrode sequentially stacked on a substrate, the charge trap layer is crystalline silicon Provided is a charge trapping memory device that is nitride.

The charge trap layer may be a crystalline silicon nitride nano dot layer.

The crystalline silicon nitride nano dot layer may be polycrystalline.

The tunneling film may be amorphous.

In order to achieve the above another technical problem, the present invention provides a method for manufacturing a charge trap type memory device having a gate stack including a charge trap means,

Forming a tunneling film on a substrate, forming crystalline silicon nitride on the tunneling film by the charge trapping means, forming a charge blocking layer covering the crystalline silicon nitride, and forming a gate electrode on the charge blocking layer. It provides a method of manufacturing a charge trapping memory device comprising the step of forming.

The crystalline silicon nitride may be formed using a hot wire vapor deposition apparatus. In this case, the crystalline silicon nitride may be formed according to the silicon nitride forming method provided to achieve the technical problem.

The crystalline silicon nitride may be formed of the crystalline silicon nitride nano dots.

The crystalline silicon nitride nano dots may be polycrystalline.

According to the present invention, the crystalline nanoparticles formed in the gas phase are deposited on a substrate, whereby a crystalline silicon nitride film or nano dots can be formed even on a low temperature substrate in which the crystalline silicon nitride film or nano dots cannot be formed. Therefore, it is possible to prevent the diffusion of impurities and to reduce the leakage current occurring in the amorphous silicon nitride.

Hereinafter, a method of forming a silicon nitride film according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of layers or regions illustrated in the drawings are exaggerated for clarity. However, the embodiments of the present invention may be modified in various forms, and the scope of the present invention should not be construed as being limited to the embodiments described below.

1 shows a film deposition apparatus used in the method for forming a crystalline silicon nitride film according to an embodiment of the present invention. The film deposition apparatus shown in FIG. 1 is a hot wire vapor deposition apparatus (Hot Wire CVD).

Referring to FIG. 1, the film deposition apparatus 5 includes a chamber 1, and includes a gas inlet 3, a gas outlet 4, and a filament 21. Through the gas injection port 3, a source gas such as a reaction gas, an atmosphere gas, or the like is injected into the chamber 1. When the silicon nitride film is formed in the chamber 5, the reaction gas may be 20% silane (SiH 4) gas and ammonia gas (NH 3). And the atmosphere gas may be H2. The gas inside the chamber 1 is discharged out of the chamber 1 through the gas outlet 4. Heat is released to dissociate the reaction gas injected from the filament 21 into the chamber 1. To this end, the filament 21 may be maintained at a predetermined temperature. For example, when the reaction gas is introduced to form a crystalline silicon nitride film in the chamber 1, the filament 21 may be maintained at 1400 ° C-2000 ° C, preferably 1700 ° C. As the filament 21 used to dissociate the reaction gas at high temperature, a single metal such as tungsten (W) coated with graphite may be used, but an alloy may be used. The alloy may be an alloy of a metal heating element such as molybdenum (Mo), platinum (Pt), tantalum (Ta), iridium (Ir), and the like. The filament 21 may have a single line, a twisted shape, or any shape. And the number of filaments 21 may be one or more.

The film deposition apparatus 5 also includes an electrode 22, a substrate holder 41 holding the substrate 40 during film deposition, a heater 10 and a power source 24. Voltage is applied from the power source 23 to the filament via the electrode 22. The filament 21 and the electrode 22 are collectively referred to as a hot-wire 30. Thin films or nano dots may be formed on the substrate 40. For example, a crystalline silicon nitride layer or crystalline silicon nitride nano dots may be formed on the substrate 40. This will be described later. The substrate holder 41 may hold substrates of various sizes. The heater 10 maintains the substrate 40 at a constant temperature during film deposition. For example, while the crystalline silicon nitride film is formed, the heater 10 maintains the temperature of the substrate at 500 ° C-700 ° C. The power supply 24 supplies electric power to the heater 10 and can apply constant AC and DC voltages.

Next, a method of forming crystalline silicon nitride (hereinafter, the method of the present invention) using the above-described film deposition apparatus 5 will be described with reference to FIG.

Referring to FIG. 2, the method of the present invention first loads a substrate 40 into a chamber 1 (100). At this time, the pressure of the chamber 1 may be maintained at several tens of mtorr, for example, about 10 ⁻² torr. The substrate 40 may be a (100) silicon substrate. Thereafter, hydrogen gas (H 2) may be injected into the atmosphere gas for preventing the filament 21 from being oxidized. The substrate 40 and the filament 21 may be kept at a predetermined distance suitable for forming a crystalline silicon nitride film or crystalline silicon nitride nanodots on the substrate 40, for example, the substrate 40 and the filament 21. The distance between) may be about 6.5 cm. When other conditions are constant, the distance between the substrate 40 and the filament 21 may be adjusted to form a crystalline silicon nitride film or the crystalline silicon nitride nano dots on the substrate 40.

Next, the temperature of the filament 21 is raised to be enough to dissociate the reaction gas to be injected (110). For example, when the reaction gas for forming silicon nitride is introduced, the filament 21 may be increased to 1400 ° C-2000 ° C, preferably 1700 ° C.

Next, the reaction gas is supplied to the chamber 1 through the gas inlet 3 (120). The reaction gas may be a source gas required to form a silicon nitride film. In this case, the pressure in the chamber 1 may be maintained at several tens of torr at several torrs, and the substrate 40 may be maintained at 500 ° C-700 ° C. For example, the pressure of the chamber 1 may be 4 torr to 40 torr.

The source gas is for supplying silicon (Si), and may be monosilane, disilane, trisilane, tetrasilane, or the like, and may be ammonia gas (NH 3) for supplying nitrogen (N). At this time, the flow rate of the source gas is maintained so that the ratio of 20% silane gas and ammonia gas (SiH 4 (20%): NH 3) is 1:50, 1: 100 or 1: 200. Here, the ammonia flow rate can be kept constant at 200 sccm.

The introduced reaction gas is dissociated while passing through the filament 21. The dissociated reaction gas is condensed in the gas phase to form nuclei of silicon nitride and become crystalline nanoparticles.

On the other hand, the degree of supersaturation of the introduced reaction gas is lowered due to the pressure condition of the chamber 1. When the degree of super saturation is low, dissociation of the introduced reaction gas does not occur in the region where the temperature around the filament 21 is lower, for example, the temperature is lower than 1700 ° C., and nucleation of the dissociated reaction gas is not performed.

The nanoparticles thus formed are deposited on the substrate 40 to form a crystalline silicon nitride film. In this case, the deposition time may be about 30 minutes. However, the deposition time is not limited to 30 minutes. The deposition time may be shorter than 30 minutes, for example several seconds. Since the crystalline silicon nitride film is formed as a result of sufficient deposition of the crystalline silicon nitride nano dot particles on the substrate 40, the crystalline silicon nitride nano dots may be formed on the substrate 40 even by controlling the deposition time.

In HWCVD, nanoparticles are formed, and thin films are formed by nanoparticles in N. M. Hwang, I. D. Jeon and D. Y. Kim, J. Ceram. Process. Res., 1, 33 (2000).

Next, experiments performed by the present inventors with respect to the above-described method for forming crystalline silicon nitride will be described.

First, the inventors conducted the first and second experiments to know the influence of the chamber pressure and the temperature of the filament on the composition ratio of silicon nitride.

The first experiment was carried out according to the silicon nitride forming method described above. At this time, 20% of silane gas and ammonia gas were used as the reaction gas. The ratio of the silane gas and the ammonia gas (SiH 4 (20%): NH 3) was maintained at 1: 200, the chamber pressure was 4 torr, and the substrate temperature was maintained at 700 ° C.

The second experiment was the same as the first experiment, but the pressure of the chamber was slightly increased from 4 tor to 40 torr.

3 and 4 are X-ray diffraction analysis results showing the results of the first and second experiments, respectively.

3 and 4, as the reaction pressure of the chamber is changed, it can be seen that the tendency of the composition ratio of silicon nitride according to the change in the filament temperature varies.

Next, the present inventors carried out the third and fourth experiments to determine the effect of the filament temperature change while keeping the chamber pressure constant.

In the third experiment, 5 sccm of 20% silane gas (SiH 4 (20%)) and 200 sccm of ammonia gas were used, and the flow ratio of silane gas and ammonia gas was maintained at 1: 200. In addition, crystalline silicon nitride, for example, Si 3 N 4 was formed while maintaining the filament temperature at 1430 ° C, the substrate temperature at 700 ° C, and the pressure at 4torr.

The execution conditions of the fourth experiment are the same as the third experiment except that the filament temperature is maintained at 1730 ° C.

5 and 6 show high resolution transmission electron micrographs of the crystalline silicon nitrides formed in the third and fourth experiments, respectively.

5 and 6, it can be seen that the silicon nitride formed in the third and fourth experiments, for example, Si3N4, is crystalline, and has different sizes and densities and different thicknesses of the crystal grains.

From these results, it can be seen that the change in filament temperature affects the grain size, grain density and film thickness.

Next, the present inventors carried out the fifth experiment in which the silicon nitride was formed by increasing the chamber pressure from 4 tor to 40 torr only with the other conditions being the same in the fourth experiment.

7 shows a high resolution transmission electron micrograph of a silicon nitride, such as Si 3 N 4, formed in the fifth experiment.

Referring to FIG. 7, it can be seen that the silicon nitride formed by the fifth experiment is also crystalline. In addition, when the crystallinity of the silicon nitride formed on the natural oxide film of the substrate is viewed, it can be seen that the crystallinity of the silicon nitride formed in the thin portion of the natural oxide film is consistent with the direction of the silicon wafer used as the substrate.

This result of FIG. 7 means that by growing silicon nitride directly on the silicon substrate from which the natural oxide film has been removed, silicon nitride having the same crystal direction as that of the silicon substrate can be formed. Thus, when the silicon substrate is single crystal, single crystal silicon nitride can be formed.

In addition, comparing FIG. 6 and FIG. 7, it can be seen that when all the conditions are the same, when the chamber pressure is increased, the crystal grain density becomes higher, and the crystalline region showing the crystallographically identical direction becomes wider.

Meanwhile, the temperature of the substrate on which silicon nitride is formed in FIGS. 5, 6, and 7 is 700 ° C. This temperature is such that when atoms or molecules in the gas phase reach the substrate and silicon nitride forms, crystallinity cannot be made.

However, as can be seen from the results of FIGS. 5 to 7, according to the method of the present invention, it can be seen that the crystal grains are present in the silicon nitride formed on the substrate at 700 ℃.

This is possible because the silicon nitride is not made by atoms or molecules reaching the substrate, but because nanoparticles with crystallinity made from dissociated reactant gases in the gas phase are deposited on the substrate.

Although the results of the experiments of FIGS. 5 to 7 differ in the degree of crystal grains according to each experimental condition, the films or nano dots formed of crystalline silicon nitride are also formed on low temperature substrates where crystalline silicon nitride has never been formed. It can be formed.

Next, a charge trap type memory device (hereinafter, referred to as the memory device of the present invention) including crystalline silicon nitride nano dots according to an embodiment of the present invention will be described.

Referring to FIG. 8, the memory device of the present invention includes a gate stack 50 on a substrate 40. First and second impurity regions 52 and 54 exist on the substrate 40 on both sides of the gate stack 50. One of the first and second impurity regions 52 and 54 is used as a source region and the other as a drain region. The gate stack 50 includes a tunneling film 42, a nano dot layer 44, a charge blocking layer 46, and a gate electrode 48 that are sequentially stacked. The tunneling film 42 may be, for example, a silicon oxide film (SiO 2). In this case, the silicon oxide film may be amorphous. The nano dot layer 44 is a charge trap layer and includes a plurality of nano dots 44a. The nano dots 44a may be crystalline silicon nitride, for example, crystalline Si 3 N 4 nano dots. This nano dot 44a is covered with the charge blocking layer 46. The charge blocking layer 46 prevents the charge trapped in the nano dot layer 44 from leaking to the gate electrode 48.

The charge trapping memory device of the present invention shown in FIG. 8 includes a nano dot layer formed of crystalline silicon nitride as described above as a charge trapping layer. Therefore, it is possible to reduce shallow defects, which is an advantage of crystalline silicon nitride, to obtain a large ETA, and also to reduce an effect of lateral migration, which is an advantage of nano dots.

Next, a method of manufacturing the charge trapping memory device of FIG. 8 will be described with reference to FIGS. 9 to 11.

9, a tunneling film 42 is formed on the substrate 40. The tunneling film 42 may be formed of an amorphous silicon oxide film, for example, an amorphous SiO 2 film. The tunneling film 42 may be formed of another material film suitable for forming the nano dot layer 44 in a subsequent process. After the tunneling film 42 is formed, the substrate 40 is loaded with the above-described hot wire vapor deposition apparatus and held in the substrate holder 41. Thereafter, the hot-wire vapor deposition apparatus is operated according to the above-described conditions to form the crystalline nano dot layer 44 on the tunneling film 42 formed on the substrate 40. Description of the various conditions under which the crystalline nano dot layer 44 may be formed has been described above with reference to the hot-wire vapor deposition apparatus, and thus will be omitted. The crystalline nano dot layer 44 has a nano dot layer 44 includes a plurality of crystalline nano dots 44a. The nano dot 44a may be, for example, crystalline silicon nitride. When the tunneling film 42 is an amorphous silicon oxide film, the crystalline phase of the nano dot 44a may be polycrystalline. When the nano dot layer 44 is a crystalline silicon nitride nano dot layer, an example of the deposition condition may be as follows. However, as described above, the crystalline silicon nano dot layer may be formed under other conditions.

Filament temperature: 1730 ° C, reaction pressure (pressure in a hot vapor deposition apparatus): 40 Torr, gas supply ratio: NH3 / SiH4 = 200, substrate 40 temperature: 700 ° C

After the nano dot layer 44 is formed on the tunneling film 42, the substrate 40 is removed from the hot-wire vapor deposition apparatus, and the film deposition apparatus or the like is used to form the tunneling film 42. Loading is followed by a subsequent film deposition process.

Next, referring to FIG. 10, a charge blocking layer 46 covering the nano dot layer 44 is formed on the tunneling film 42. The charge blocking layer 46 can prevent the charge trapped in the nano dot layer 44 from leaking to the gate electrode 48, and also prevents charge from flowing from the gate electrode 48 to the nano dot layer 44. It may be an insulating material film that can be prevented. For example, the charge blocking layer 46 may be an aluminum oxide layer. The gate electrode 48 is formed on the charge blocking layer 46. The gate electrode 48 may be a doped silicon layer, a metal layer, an conductive alloy layer, or a conductive oxide layer. The mask M1 is formed on the gate electrode 48. The mask M1 defines a region where the gate stack 50 of FIG. 8 is to be formed. The gate electrode 48, the charge blocking layer 46, the nano dot layer 44, and the tunneling layer 42 around the mask M1 are sequentially etched. This etching is performed until the substrate 40 is exposed. As a result of the etching, the gate stack 50 is formed on the substrate 40 as shown in FIG. 11. Thereafter, the mask M1 is removed. After the mask M1 is removed, the first and second impurity regions 52 and 54, that is, the source and drain regions, of the charge trapping memory device of FIG. 8 may be formed according to a conventional process. In this process, a gate spacer (not shown) covering the side surface of the gate stack 50 may be further formed, and the first and second impurity regions 52 and 54 may be formed of a lightly doped drain (LDD) structure. have.

FIG. 12 is a transmission electron microscope (TEM) image of the nano dot layer 44 when the nano dot layer 44 is a crystalline silicon nitride nano dot layer in the method of manufacturing a charge trapping memory device.

Referring to FIG. 12, a plurality of circular objects C1 can be seen, which are nano dots 44a. 13 and 14 are enlarged images of part of FIG. 12, wherein the first area A1 of FIG. 13 and the second and third areas A2 and A3 of FIG. 14 represent nano dots 44a. 13 and 14, the first to third regions A1 to A3 each include a plurality of parallel first to third lines L1 to L3, so that the first to third regions A1 to A3 are distinguished from the peripheral region that is not. Able to know. The first to third lines L1 to L3 represent crystal planes. Accordingly, it can be seen from FIGS. 13 and 14 that the phase of the nano dot 44a is a crystal.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, those skilled in the art will be able to vary the process conditions in the chamber of the method of forming the crystalline silicon nitride film or the crystalline silicon nitride nanodot of the present invention. In addition, the method of the present invention may be applied to the manufacturing method of various semiconductor devices in which a silicon nitride film or crystalline silicon nitride nanodots can be used. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

1 is a cross-sectional view of a hot wire CVD (HWCVD) apparatus used for forming low temperature crystalline silicon nitride chips according to an embodiment of the present invention.

2 is a block diagram showing step by step a method of forming silicon nitride according to an embodiment of the present invention using the apparatus of FIG.

3 and 4 are graphs showing the results of the first and second experiments conducted to know the change in the composition ratio of the crystalline silicon nitride according to the change in the reaction pressure of the chamber.

5 and 6 are High Resolution Transmission Electron Microscopy showing the results of the third and fourth experiments conducted to determine the effect of the filament temperature change on the silicon nitride in the silicon nitride deposition using the apparatus of FIG. HRTEM) picture.

7 is a high resolution transmission electron micrograph showing the results of the fifth experiment with the same conditions as the fourth experiment but the pressure was increased from 4 tor to 40 torr only.

8 is a cross-sectional view of a charge trap type memory device according to an embodiment of the present invention including a crystalline nano dot layer as a charge trap layer.

9 through 11 are cross-sectional views sequentially illustrating a method of manufacturing the memory device of FIG. 8.

12 is a transmission electron micrograph of a crystalline nano dot layer formed in the method of manufacturing the memory device of FIGS. 9 to 11.

13 and 14 are enlarged photographs of part of FIG. 12.

* Description of Signs of Major Parts of Drawings *

1: vacuum chamber: 3: gas inlet

4: gas outlet 5: film deposition apparatus (HWCVD)

10: heater 21: filament

22: electrode 23, 24: power supply

30: Hot Wire 40: Board

       41: substrate holder 42: tunneling film

       44: crystalline nano dot layer 44a: crystalline nano dot

       46: charge blocking layer 48: gate electrode

       52, 54: First and second impurity regions

       C1: circular objects A1 to A3: first to third regions

       L1: line of first region A1 L2: line of second region A2

       L3: Line M1 of the third region A3: Mask

Claims (15)

Loading a substrate into a chamber of a silicon nitride deposition apparatus including a filament; A second step of raising the temperature of the filament to a temperature at which the reaction gas to be introduced can be dissociated; And And supplying a reaction gas for forming silicon nitride to the chamber, The temperature of the filament is maintained at 1400 ℃-2000 ℃, In the third step, the pressure in the chamber is maintained at several torr-torr, And forming crystalline silicon nitride on the substrate. The method of claim 1, wherein the substrate is maintained at 500 ℃-700 ℃. The method of claim 1 wherein the pressure in the chamber is 4 tor-40 torr. The method of claim 1, wherein the reaction gas is a first source gas for supplying silicon (Si) and a second source gas for supplying nitrogen (N), And the first source gas is monosilane (SiH 4), disilane, trisilane, or tetrasilane. The flow rate of claim 4, wherein the first source gas is 20% mono silane and the second source gas is ammonia gas (NH 3). Silicon nitride forming method, characterized in that to maintain: 50, 1: 100 or 1: 200. In the charge trapping memory device comprising a tunneling film, a charge trap layer, a charge blocking layer and a gate electrode sequentially stacked on a substrate, And the charge trap layer is crystalline silicon nitride. The device of claim 6, wherein the charge trap layer is a crystalline silicon nitride nano dot layer. 8. The device of claim 7, wherein the crystalline silicon nitride nano dot layer is polycrystalline. 7. The memory device of claim 6, wherein the tunneling film is amorphous. A method for manufacturing a charge trapping memory device having a gate stack including a charge trapping means, Forming a tunneling film on the substrate; Forming crystalline silicon nitride on the tunneling film by the charge trapping means; Forming a charge blocking layer covering the crystalline silicon nitride; And And forming a gate electrode on the charge blocking layer. The method of claim 10, wherein the crystalline silicon nitride is formed using a hot wire vapor deposition apparatus. The method of claim 11, wherein the crystalline silicon nitride is formed according to the process of claim 1. The method of claim 10, wherein the crystalline silicon nitride is formed of the crystalline silicon nitride nano dots. The method of claim 10, wherein the tunneling film is formed of an amorphous film. The method of claim 13, wherein the crystalline silicon nitride nano dots are polycrystalline.

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