KR20090028502A - Packaged system of semiconductor chips having a semiconductor interposer - Google Patents

Abstract

A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202,203) have a dimension (220,230) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (224,234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.

Description

Semiconductor system and its manufacturing method {PACKAGED SYSTEM OF SEMICONDUCTOR CHIPS HAVING A SEMICONDUCTOR INTERPOSER}

FIELD OF THE INVENTION The present invention relates generally to the field of semiconductor devices and processes, and more particularly to a low profile, vertically integrated package-on-package (PoP) semiconductor system.

When semiconductor chips are to be mounted as substrates or interposers to form state-of-the-art semiconductor packages, the substrates and interposers are generally made of plastic or ceramic materials. Plastic or ceramic materials are particularly preferred when the chip assembly technique uses a flip-chip method that uses solder balls to create an electrical connection between the chip and the substrate / interposer. If the assembled devices are then used or tested under conditions that apply a wide range of temperature or humidity changes to the package, a noticeable failure rate may occur, particularly characterized by cracks in the solder joints and delamination of the package components. .

Driven by the desire to reduce the board area needed to assemble semiconductor devices into electronics such as handheld phones, today's semiconductor devices use mainly vertically stacked chips in a package. Such chip stacks often include significantly different sizes of chips, most of which are assembled by wire bonding techniques on interposers made of plastic or ceramic materials. The stack on the interposer is then assembled onto the substrate using solder balls for interconnection with the exterior components. Reliability failure rates due to solder joint gaps or component stripping, as observed in such devices under temperature cycles and high humidity conditions, are particularly high.

<Overview>

Applicants recognize a large variation in material properties, especially the coefficient of thermal expansion (CTE) between plastic or ceramic and semiconductor materials, as a major source of reliability failure rates observed in devices with chips assembled on plastic interposers. The CTE of ceramic material is 7 to 10 times higher than that of silicon material). CTE mismatches are reduced by using interposers made of semiconductor materials instead of plastics.

Applicants further recognize the need to scale down semiconductor devices in both two and three dimensions, particularly for device stacking and PoP methods for semiconductor devices as well as electronic systems. In Applicants' approach, the resulting system provides improved speed and power capability by minimizing electrical resistance and inductance and replacing wire bonding with flip chip assemblies. A further advantage of semiconductor interposers is the opportunity to configure even active electronic devices and integrated circuits within the surface of the interposer.

One embodiment of the present invention is a semiconductor system having one or more semiconductor interposers with conductive lines of a particular dimension (preferably designed for power distribution) on the first and second surfaces. Conductive vias extend from the first surface to the second surface, with the terminal and attached non-reflow metal stud at the end of the vias, preferably at the first surface There is a copper stud and a gold stud on the second surface. One or more semiconductor chips have dimensions narrower than the interposer dimensions and an activation surface having terminals and non-reflow metal studs. One chip is flip-attached to the first interposer surface and another chip is flip-attached to the second interposer surface so that the interposer dimensions protrude beyond the chip dimensions. The insulating substrate has a third surface and a fourth surface with terminals. The conductive line is between the surface and the conductive vias extending from the third surface to the fourth surface. The reflow body on the terminal of the third substrate surface is connected to the stud on the second surface of the protruding interposer.

The first interposer surface may include individual electronic components or integrated circuits. An encapsulation material may cover a portion of the semiconductor chip, semiconductor interposer, and third substrate surface.

Another embodiment is a method of manufacturing a semiconductor system that includes the manufacture of one or more semiconductor interposers. A semiconductor wafer of a particular thickness has a first surface and a second surface, and conductive lines and optional individual components or circuits are made on the first surface. Via holes are formed to extend downwardly from the first surface to a certain depth. The insulating layer is then laminated over the first and second surfaces, including the sidewalls of the via holes. The semiconductor material is removed from the second wafer surface until the via holes are exposed. Copper is then deposited to fill the holes and form terminals on the first and second surfaces. Non-reflow metal studs are stacked over the terminals. Finally, the wafer is singulated into individual interposers of specific dimensions.

One or more semiconductor chips having dimensions narrower than the interposer dimensions are provided. Semiconductor chips have terminals with active surfaces and non-reflow metal studs. One chip is flip-attached to the first interposer surface so that the interposer dimensions protrude above the chip dimensions. The other chip is attached to the surface of the second interposer surface or the substrate. This insulating substrate has third and fourth surfaces with terminals, conductive lines between the surfaces, and conductive vias extending from the third surface to the fourth surface. The reflow body is laminated on the terminals of the third substrate surface. The reflow bodies are then contacted with a stud on the second surface of the protruding interposer and reflowed to attach the interposer to the substrate.

1 is a schematic cross-sectional view of a system having a flip-assembled semiconductor interposer on a substrate and a semiconductor chip flip-assembled on an interposer, wherein the chip has dimensions narrower than the interposer dimensions.

2 is a schematic cross-sectional view of a system having a flip assembled semiconductor interposer, two semiconductor chips flip assembled on an interposer, the chips having dimensions narrower than the interposer dimensions.

FIG. 3 shows a schematic cross-sectional view of a system similar to the system of FIG. 2 with an enclosure device attached using a solder body.

4 is a schematic cross-sectional view of a system having two semiconductor interposers, two semiconductor chips having dimensions narrower than the interposer dimensions, and a substrate, wherein the chips are flip attached to the interposer, with one substrate attached to the substrate; 2 is attached to the substrate.

1 illustrates a semiconductor system, generally labeled "100", comprising an interposer 101 made of a semiconductor material, a semiconductor chip 102, and a substrate 103 of an insulating material. Although silicon is the preferred semiconductor material, the invention applies to any semiconductor material, such as germanium, silicon germanium, gallium arsenide, or other III-IV and II-IV compounds used in device manufacture.

Interposer 101 has a particular dimension, denoted as "110". In Figure 1, the dimension is the length of the interposer. In another example, the dimension can be the width of the interposer. Moreover, the interposer has a first surface 101a and a second surface 101b. On the first surface 101a and the second surface 101b there are a plurality of conductive lines for electrical communication patterned from a metal layer, such as copper or aluminum, although detailed lines are not shown in FIG. Is indicated. Some lines may be formed as a power bus (low IR drop) for carrying electrical current for high power devices.

The lines contact conductive vias 112 extending from the first surface to the second surface. Vias 112 are metal-filled connections between surface 101a and surface 101b. Preferably they are copper-filled holes with insulating sidewalls to avoid unintended contact with the semiconductor based material. At the end of the via or line is a terminal 113, preferably made of copper.

Many terminals are attached with metal studs made of a metal or alloy with a melting point significantly higher than most semiconductor assembly temperatures (higher than about 900 ° C.). In the example of FIG. 1, the stud 114 on the first interposer surface 101a is preferably made of copper and the stud 115 on the second surface 101b is preferably made of gold. Unlike typical tin-based solders with melting points between about 200 ° C. and 400 ° C., stud metals are often referred to as non-reflow metals. Non-reflow studs can be made smaller in size than solder-type connectors. And smaller stud sizes allow for finer pitch (center-to-center). Stud pitches of less than 125 μm are possible.

Chip 102 in FIG. 1 has dimension 120. Although the chip dimensions 120 may be about the same as the interposer dimensions 110, in order to provide space for additional contact between the interposer 101 and the substrate 103 in a multichip configuration, the interposer dimensions ( It is advantageous to have a dimension 120 that is narrower than 110 (see FIGS. 2, 3 and 4). The chip 102 further has an activation surface 102a that includes a semiconductor device (eg, an integrated circuit) and an input / output terminal 123. Terminal 123 is preferably made of copper and to which a non-reflow metal stud 124 is attached. These studs are made of gold, preferably copper, of a metallurgically suitable surface for direct attachment to interposer stud 114.

As shown in FIG. 1, the chip 102 is attached to the first interposer surface 101 such that the interposer dimension 110 protrudes by a length 140 than the chip dimension 120. The protrusion of the interposer may be symmetrical or asymmetrical around the chip.

The system 100 has a substrate 103 made of an insulating material, having a third surface 103a and a fourth surface 103b. There is a terminal 131 on the third surface 103a and a terminal 133 on the fourth surface 103b. Preferred metals for the terminals are copper having a metallurgically suitable surface (preferably one or more layers of nickel, palladium or gold) for solder attachment. The substrate 103 further has conductive lines between the surfaces. Although detailed lines are not shown in FIG. 1, some portions are indicated by “135”. The substrate 103 also has conductive vias extending from the third surface to the fourth surface and capable of contacting the lines (detailed vias are not shown in FIG. 1, but some portions are indicated by “136”). A body 134 of reflow metal (preferably of tin-based alloy) is present on terminal 131. They enable reliable electrical contact to the stud 115 on the second surface 101b of the interposer 101.

As shown in FIG. 1, the reflow body (solder ball) 150 may be attached to a terminal on the fourth surface 103b. In addition, encapsulation material 160, such as a molding compound, may cover a portion of semiconductor chip 102, semiconductor interposer 101, and third substrate surface 103a. In devices using such encapsulation, the material may be stress-absorbing underfill in the gap between chip 102 and interposer 101 and the gap between interposer 101 and substrate 103, and This serves the dual purpose of protecting the studs 124, 114, and 115.

It should be noted that the use of encapsulation material 160 is optional.

The advantage of using semiconductor materials for interposers lies in minimizing the thermomechanical pressure applied to semiconductor chip 102 due to similar thermal expansion coefficients of the interposer and the chip. As another advantage, the semiconductor interposer facilitates the integration of individual electronic components or a complete integrated circuit at the first interposer surface 101a. Although the detailed components / circuits are not shown in FIG. 1, some are indicated by “116”. Components or circuits included in surface 101a may utilize the fact that interposer 101 has terminals and contacts on both surfaces 101a and 101b and interconnects between the surfaces. (Process steps for manufacturing an interposer with integrated circuits and vias filled with metal are described below).

Advantages of semiconductor interposers having dimensions larger than those of semiconductor chips for assembling electronic systems are evident in FIGS. 2-3 illustrate semiconductor systems 200 and 300 having two semiconductor chips and a semiconductor interposer. In FIG. 3, system 300 assembles to additional device 380 on enclosure component 390.

In FIG. 2, the semiconductor system 200 includes an interposer 201 made of a semiconductor material, a first semiconductor chip 202, a second semiconductor chip 203, and a substrate 204 made of an insulating material. The interposer 201 preferably has a thickness of about 30 μm to 60 μm. In addition, the interposer has a particular dimension, only the portion indicated by "210" is shown in FIG. Moreover, the interposer has a first surface 201a and a second surface 201b. On the first surface 201a and the second surface 201b are a plurality of conductive lines (only portions 214 shown in FIG. 2) for electrical communication, patterned from metal layers such as copper or aluminum.

The lines are in contact with conductive vias 212 extending from the first surface to the second surface. Via 212 is a metal filled connection between surface 201a and surface 201b. Via 212 is preferably a hole filled with copper with an insulating wall to avoid inadvertent contact with the semiconductor based material. At the end of the via or line is a terminal 213, preferably made of copper.

Many terminals are attached with a metal stud made of a metal or alloy having a melting point significantly higher than most semiconductor assembly temperatures (higher than about 900 ° C.). In the example of FIG. 2, the stud 215 on the second surface 201b may be made of copper, or more preferably gold. Non-reflow studs can be manufactured in smaller sizes than reflow (solder type) connectors. And smaller stud sizes allow for finer pitch (center to center), especially when studs are produced from gold in wire bonding. The stud pitch can be less than 125 μm.

The first chip 202 may be as thin as approximately 50 μm. The first chip has a transverse dimension, a portion 220 of which is shown in FIG. 2. In addition, the second chip 203 may be as thin as approximately 50 μm and has a transverse dimension, with a portion 230 shown in FIG. 2. It is advantageous to have dimensions 220 and 230 that are narrower than interposer dimensions 210 to provide space for additional contact between interposer 201 and substrate 203 in a multichip configuration. In some devices, portion 220 may be greater than or equal to portion 210.

The chip 202 further has an activation surface 202a that includes a semiconductor device (eg, an integrated circuit) and an input / output terminal. A non-reflow metal stud 224 is attached to the terminal. Such studs are preferably made of gold and have a height of about 5 μm to 10 μm. The chip 203 further has an activation surface 203a that includes a semiconductor device (eg, an integrated circuit) and an input / output terminal. A non-reflow metal stud 234 is attached to the terminal. Such studs are preferably made of gold and have a height of about 5 μm to 10 μm.

As shown in FIG. 2, the first chip 202 is attached to the first interposer surface 201a so that the interposer dimension 210 protrudes by a certain length than the chip dimension 220. The protrusion of the interposer may be symmetrical or asymmetrical around the chip. The attachment is performed by flipping the chip so that the activating surface 202a of the chip faces the first surface 201a of the interposer. The second chip 203 is attached to the second interposer surface 201b so that the interposer dimension 210 protrudes above the chip dimension 230. The protrusion of the interposer may be symmetrical or asymmetrical around the chip. Attachment is performed by a flip chip method, such that the activation surface 203a faces the second substrate surface 201b. In addition, the passive surface 203b of the second chip is attached to the substrate 204 by an adhesive material 270 that is between about 15 μm and 25 μm thick.

Due to the interposer dimensions protruding at least the dimensions of the second chip, the studs 215 on the second interposer surface 201b remain to be able to connect to the reflow body on the third substrate terminal.

System 200 has a substrate 204 made of an insulating based material of approximately 200 μm to 300 μm having a third surface 204a and a fourth surface 204b. There is a terminal 241 on the third surface 204a and a terminal (not shown in FIG. 2) also on the fourth surface 204b. Preferred metals for the terminals are copper of a suitable metallurgical surface (preferably one or more layers of nickel, palladium or gold) for solder attachment. Substrate 204 may include conductive lines (only portions 242 and 243 shown in FIG. 2) between the surfaces, and conductive vias (some of which may contact the lines and extend from the third surface to the fourth surface). Only 244 and 245). A body 242 of reflow metal (mainly tin-based alloy) is present on some terminals 241. This allows for reliable electrical contact to the stud 215 on the second surface 201b of the interposer 201. The other contact 241 remains available for solder attachment of the external device (see FIG. 3).

As shown in FIG. 2, the reflow body (solder ball) 250 may be attached to a terminal on the fourth surface 204b. The reflow body has a diameter of about 180 μm to 250 μm and may have a center-to-center pitch of approximately 500 μm. In addition, encapsulation material 260, such as a casting compound, may cover portions of semiconductor chips 202 and 203, semiconductor interposer 201, and third substrate surface 204a. The encapsulation material may have a thickness between approximately 40 μm and 70 μm on the first chip 202. In devices using such encapsulation, the material is a double layer of stress buffer underfill in the gap between the chips 202 and 203 and the interposer and the gap between the interposer and the substrate and the protection of the studs 224, 234 and 215. Assist the purpose.

Use of encapsulation material 260 is optional. Since the semiconductor material is used for the interposer, the thermomechanical stress applied to the semiconductor chips 202 and 203 is kept to a minimum. The coefficients of thermal expansion of the interposer and the chip are essentially the same.

The semiconductor properties of the interposer material facilitate the integration of individual electronic components or even a complete integrated circuit at the first interposer surface 201a. 2 shows only a portion 216 of the components. Components or circuits included in surface 201a take advantage of the fact that interposer 201 has terminals and contacts on both surfaces 201a and 201b and interconnects between the surfaces. Can be.

The thickness of a packaged device without wire bonding but including encapsulation material is between 200 μm and 250 μm. The overall thickness of the system 200 including the substrate and the solder balls is between about 650 μm and 750 μm.

The embodiment 300 of the present invention, indicated as "300" in FIG. 3, has the embodiment of FIG. 2 except that the second chip 303 is flipchip attached to the substrate 304 instead of the interposer 301. Similar to (200). In addition, FIG. 3 shows an external device 380 attached to a terminal 341 on the substrate surface 304a by a reflow member 381. In the illustration, the reflow member is selected to have a height of approximately 250 μm to 300 μm, which height is the thickness of the packaged device along the gap (approximately 50 μm) between the encapsulating material of the packaged device and the external device 380. It is a little bigger than that. By way of example, the reflow member may have a pitch (center-to-center) between approximately 620 μm and 700 μm. The enclosure device may have a thickness between approximately 500 μm and 600 μm. System 300 and enclosure device 380 may have an overall thickness between about 1.2 mm and 1.3 mm.

Another embodiment of the present invention shown in FIG. 4 includes a first interposer 401 made of a semiconductor material, a second interposer 402 made of a semiconductor material, a first semiconductor chip 403, and a second semiconductor chip. 404 is a semiconductor system 400 including a substrate 405 made of an insulating material. Although silicon is preferred as the semiconductor material, the present invention applies to any other semiconductor material used for device manufacture.

Each of the interposers 401 and 402 preferably has a thickness between approximately 30 μm and 60 μm and only a specified portion has the particular dimensions shown in FIG. 4. Moreover, each interposer has a first surface (401a and 402a respectively) and a second surface (401b and 402b respectively) with conductive lines (only some 421, 422, 423, 424 are shown in FIG. 4). Vias 425 and 426 filled with conductive metal extend from the first surface to the second surface. The vias are preferably connected to terminals made of copper. 4 shows only some of these terminals 414, labeled “413” on the first interposer and marked “414” on the second interposer.

The semiconductor properties of the interposer material facilitate the integration of the individual electronic components and even the complete integrated circuit within the first interposer surfaces 401a and 402a. Components or circuits included within surface 401a and / or surface 402a include interposers 401 and 402 having terminals and contacts on all surfaces 401a and 401b and surfaces 402a and 402b, It may take advantage of the fact that there is a conductive via interconnect between the surfaces.

Many terminals are attached with metal studs made of a metal or alloy having a melting point that is significantly higher (mostly higher than 900 ° C.) above most semiconductor assembly temperatures. In the example of FIG. 4, studs 415 and 416 on the second interposer surface may be made of copper, or more preferably gold. Stud pitches of less than 125 μm are suitable.

The first chip 403, approximately 25 μm to 50 μm thick, has a narrower horizontal dimension than the interposer dimension. The second chip 404, also approximately 25 μm to 50 μm thick, may have the same or different transverse dimensions as the chip 403, but in a multichip configuration additional contact between the interposer and the interposer or from the interposer to the substrate. It is advantageous to have a dimension that is narrower than the interposer dimension to provide space for.

Chips 403 and 404 have an activation surface with input / output terminals. The terminal is attached with a non-reflow metal stud, which is preferably made of gold and is approximately 5 μm to 10 μm high.

As shown in FIG. 4, the first chip 403 is attached to the first interposer 401 such that the interposer dimensions protrude beyond the chip dimensions by a certain length. The protrusion of the interposer may be symmetrical or asymmetrical around the chip. The attachment is performed by flipping the chip over so that the chip's active surface faces the second surface 401b of the interposer. By this flip attachment, a first subsystem is formed.

The second chip 404 is attached to the second interposer 402 such that the interposer dimensions protrude beyond the chip dimensions by a certain length. The protrusion of the interposer may be symmetrical or asymmetrical around the chip. Attachment is performed by a flip chip method, causing the activation chip surface to face the second substrate surface 402b. By this flip attachment, a second subsystem is formed.

Due to the interposer protruding beyond the dimensions of the first chip and the second chip, the studs 415 of the interposer 401 remain to be connected to the reflow body 417 on the substrate 405. Similarly, studs 416 of interposer 402 remain to be able to connect to reflow body 418 on interposer 401.

System 400 has a substrate 405 made of an insulating material of approximately 200 μm to 300 μm thick. On the substrate surface is a terminal (preferably copper) having a suitable metallurgical surface (preferably one or more layers of nickel, palladium or gold) for solder attachment. The substrate 405 further has conductive lines 451 between the surfaces and conductive vias 452 extending from one surface to the opposite surface. A body 417 of reflow metal (preferably tin-based alloy) is present on some terminals for connection with the interposer. The other terminals have a reflow member which is preferably a tin-based solder ball for attachment to the sheath component 490.

Encapsulating material 460, such as a casting compound, may cover semiconductor chips 403 and 404, one surface of semiconductor 401 and interposer 402, and a portion of the substrate surface. In devices using such encapsulation, the material serves the purpose of protection as well as the dual purpose of stress buffer underfill in the gap between the chip and the interposer.

Use of encapsulation material 460 is optional. The advantage of the semiconductor material used for the interposer is to minimize the thermomechanical stress applied to the semiconductor chips 403 and 404 due to the substantially same coefficient of thermal expansion of the interposer and the chip.

The assembled chip and interposer of FIG. 4, encapsulated in a molding material, has an overall thickness of approximately 150 μm to 190 μm. The complete system 400 has a thickness of approximately 600 μm to 700 μm.

On the terminals of the substrate surface 402a not covered by the encapsulation material, the reflow member 451 may be attached to connect to the external device 480. Members 450 and 451 may have a diameter of about 200 μm and may have a center-to-center pitch of about 500 μm.

Yet another embodiment of the present invention is a method of manufacturing a semiconductor system using a semiconductor interposer. The initial stage of manufacture fabricates a semiconductor interposer. A semiconductor wafer is provided, which is preferably a silicon wafer. The wafer has a first surface, a second surface, and a convenient thickness (eg, 375 μm to 500 μm) for high yield wafer processing. By applying standard front-end wafer process steps, a plurality of conductive lines or individual components, or even an integrated circuit, can be fabricated on the first surface of the wafer.

Prior to the step of depositing the protective overcoat, via the end of the front-end process step sequence, the via holes are formed to a certain depth downward from the first wafer surface. A preferred technique is selective chemical etching, since this technique is a batch process. Alternative methods include laser drilling. The via holes have sidewalls that receive an insulating layer by a process step of forming a protective film over the wafer surface.

Thereafter, starting from the second wafer surface, the semiconductor material is removed until the downward end of the via hole is exposed. The preferred method is mechanical wafer back-grinding. Next, the via holes are filled with metal, preferably by depositing copper. At the end of the filling step, the terminals on the first and second wafer surfaces are formed by stacking and patterning metal (eg, copper) layers.

On the selected terminal, a non-reflow metal stud is stacked. The term non-reflow refers to a metal or alloy that has a melting point significantly higher than most semiconductor assembly temperatures (approximately higher than 900 ° C.). Preferred metals include copper and gold, unlike typical tin-based solders having a melting point of 200 ° C to 400 ° C.

Non-reflow studs can be made smaller in size than solder-type connectors. And, smaller stud sizes allow finer center-to-center pitch, especially when studs are produced from gold or copper balls in wire bonding. Stud pitches of less than 125 μm are suitable. In wire ball technology, the free-air ball preferably has a 1.2 to 1.6 wire diameter. After the attaching and flattening step, the resulting ball diameter is approximately 40 μm to 70 μm for a wire diameter of 12 μm to 33 μm (preferably 18 μm to 25 μm).

In the next process step, the wafer is separated, for example by sawing, into individual interposers having the desired transverse dimensions.

Thereafter, a first semiconductor chip is provided having a terminal that is narrower than the interposer dimension, the activation surface, and a non-reflow metal stud on the activation surface. If required by the assembly system, there is also provided a second semiconductor chip having a narrower dimension than the interposer dimension, an activation surface, and a terminal having a non-reflow metal stud on the activation surface. The dimensions of the second chip may be the same as or different from the dimensions of the first chip.

The first chip is attached to the first interposer surface by flip chip technology, causing the interposer dimension to protrude above the chip dimension. In some devices, the second chip is flipped to the second interposer surface, causing the interposer dimensions to protrude above the chip dimensions, and the studs on the second interposer surface remain connectable to the reflow body on the substrate terminal. . In another device, the second chip is flipped to the substrate, causing the interposer dimensions to protrude above the chip dimensions and leaving the reflow body on the substrate terminal capable of being connected to a stud on the second interposer surface.

An insulated substrate is provided having third and fourth surfaces having terminals, conductive lines distributed between the surfaces, and conductive vias extending from the third surface to the fourth surface and contacting the lines. The reflow body is laminated on the terminals of the third substrate surface. The stud on the second surface of the raised interposer contacts the reflow body on the third substrate surface, and the body is reflowed around the stud to attach the interposer to the substrate.

Optional process steps entail encapsulation of the device for protection and stress reduction purposes. The packaging material, which is preferably a casting compound, encapsulates the chip, the interposer, and a portion of the third substrate surface. Finally, the reflow body, which is preferably a solder ball, can be attached to the terminal on the fourth substrate surface.

Although the present invention has been described with reference to illustrative embodiments, the description is not intended to be understood in a limiting sense. Various modifications and combinations of the illustrative embodiments as well as other embodiments of the present invention will be apparent to those skilled in the art by reference to the present description. Therefore, it is intended that the claimed invention cover any such modifications or embodiments.

Claims (11)

A semiconductor interposer having a dimension and a first surface and a second surface; Conductive lines on the first surface and the second surface; A conductive via extending from the first surface to the second surface in contact with the lines; A terminal having a non-reflow metal stud attached to the via; A first semiconductor chip having an activation surface; A terminal having a non-reflow metal stud on the activation surface; The first chip is flip attached to the first interposer surface; An insulating substrate having a third surface and a fourth surface having terminals; A conductive line between the third and fourth surfaces; Conductive vias extending from the third surface to the fourth surface in contact with the lines; And Reflow body on the terminal of the third substrate surface that is connected to the stud on the second interposer surface Semiconductor system comprising a. The method of claim 1, a) the first interposer surface comprises individual electronic components; b) the first interposer surface comprises an integrated circuit; c) further comprising a reflow body attached to the terminal on the fourth substrate surface; d) further comprising an encapsulation material covering a portion of the semiconductor chip, the semiconductor interposer, and the third substrate surface; e) the non-reflow metal stud on the first interposer surface is made of copper and the non-reflow metal stud on the second interposer surface and the semiconductor chip is gold Made; And f) the conductive interposer lines are suitable for power supply A semiconductor system characterized by one or more of the following. The method according to claim 1 or 2, And further comprising a second semiconductor chip having an activation surface comprising a terminal having a dimension narrower than the interposer dimension and a non-reflow metal stud, the second chip being flip attached to the second interposer surface. And the interposer dimension protrudes beyond the chip dimension and a stud on the second interposer surface remains connectable to the reflow body on the third substrate terminal. The method according to claim 1 or 2, A second semiconductor chip having an activation surface comprising a terminal having a dimension narrower than the interposer dimension and a non-reflow metal stud, the second chip being flip attached to the third substrate surface, The interposer dimension protrudes beyond the chip dimension and the reflow body on the third substrate terminal remains to be connectable to the stud on the second interposer surface. A first semiconductor interposer having a first dimension and a first surface and a second surface; Conductive lines on the first and second surfaces; Conductive vias extending from the first surface to the second surface in contact with the lines; A terminal having a non-reflow metal stud attached to the via; A first semiconductor chip having a dimension narrower than the first interposer dimension and an activation surface; A terminal having a non-reflow metal stud on the activation surface; The first chip is flip-attached to the second surface of the first interposer such that the first interposer dimension protrudes above the chip dimension; A first sus system comprising a; And A second semiconductor interposer having a second dimension and a third surface and a fourth surface; Conductive lines on the third and fourth surfaces; Conductive vias extending from the third surface to the fourth surface in contact with the lines; A terminal having a non-reflow metal stud attached to the via; A second semiconductor chip having an activation surface and a dimension narrower than the second interposer dimension; A terminal having a non-reflow metal stud on the activation surface; The second chip is flip-attached to the fourth surface of the second interposer such that the second interposer dimension protrudes above the chip dimension; Reflow body on the terminal of the first interposer surface connected to the stud on the fourth surface of the protruding second interposer A second subsystem comprising a; An insulating substrate having fifth and sixth surfaces having terminals; A conductive line between the fifth and sixth surfaces; Conductive vias extending from the fifth surface to the sixth surface in contact with the lines; And Reflow body on the terminal of the fifth substrate surface that is connected to the stud on the second surface of the protruding first interposer Semiconductor system comprising a. The method of claim 5, a) further comprising a reflow body attached to the terminal on the sixth substrate surface; b) further comprising a reflow body attached to pads of the third surface of the second interposer; And c) an encapsulation material covering the first and second semiconductor chips, the first semiconductor interposer, the third surface of the second interposer, and a portion of the fifth substrate surface. A semiconductor system characterized by one or more of the following. In the method of manufacturing a semiconductor system, Providing a semiconductor wafer having a thickness and a first surface and a second surface, Manufacturing a conductive line, individual components, and a circuit on the first surface, Forming a via hole having sidewalls extending deeply downwardly from the first surface, Forming an insulating layer over the first and second surfaces including the via hole sidewalls, Removing the semiconductor material from the second wafer surface until the via hole is exposed, Depositing copper to fill the holes and form terminals on the first and second surfaces, Laminating a non-reflow metal stud on the terminal, and Singulating the wafer into dimensionally interposers and selecting a first individual interposer Forming a semiconductor interposer by; Providing a first semiconductor chip having a narrower dimension than the interposer dimension, an activation surface, and a terminal having a non-reflow metal stud on the activation surface; Flip attaching the first chip to the first surface of the selected first interposer such that the interposer dimension protrudes above the chip dimension; Providing an insulated substrate having third and fourth surfaces having terminals, conductive lines between the surfaces, and conductive vias in contact with the lines that extend from the third surface to the fourth surface; Stacking a reflow body on the terminal of the third substrate surface; Contacting the stud on the second surface of the protruding interposer with the reflow body on the third substrate surface; And Reflowing the body around the stud to attach the interposer to the substrate Semiconductor system manufacturing method comprising a. The method of claim 7, wherein a) attaching a reflow body to the terminal on the fourth substrate surface; And b) encapsulating a portion of the chip, the interposer, and the third substrate surface in a packaged material. Method for manufacturing a semiconductor system, characterized in that at least one of. The method according to claim 7 or 8, Providing a second semiconductor chip having a dimension narrower than the interposer dimension and an activation surface comprising a terminal having a non-reflow stud; And Flip attaching the second chip to the second interposer surface such that the interposer dimensions protrude beyond the chip dimensions A semiconductor system manufacturing method further comprising. The method according to claim 7 or 8, Providing a second semiconductor chip having a dimension narrower than the interposer dimension and an activation surface comprising a terminal having a non-reflow stud; And Flip attaching the second chip to the third substrate surface such that the interposer dimensions protrude beyond the chip dimensions A semiconductor system manufacturing method further comprising. The method according to claim 7 or 8, Selecting a second individual interposer having dimensions; Providing a second semiconductor chip having an activation surface comprising a dimension narrower than the dimension of the second interposer and a terminal having a non-reflow stud; Flip attaching the second chip to the second interposer such that the interposer dimension protrudes above the chip dimension; Stacking a reflow body on the terminal of the first surface of the protruding first interposer; Contacting the non-reflow metal stud on the protruding second interposer with the reflow body on the terminal of the protruding first interposer surface; And Reflowing the body around the stud to attach the second interposer to the first interposer A semiconductor system manufacturing method further comprising.

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