KR20090025944A - Image sensor and a method of the same - Google Patents

Abstract

An image sensor and a manufacturing method thereof are provided to improve the reliability of the image sensor by preventing the silicidation of the semiconductor substrate. An image sensor comprises a semiconductor substrate(101); a charge transport unit(130) formed on the semiconductor substrate; a photoelectron transform portion(110) which is formed within one semiconductor substrate of the charge transport unit, and accumulates the electric charge; an electric charge detection part(120) converting the electric charge accumulated in the photoelectron transform portion into the electric signal; the first spacer(210) formed on sidewall and photoelectron transform portion of the charge transport unit; a blocking film(220) which is formed on the semiconductor substrate conformably; the second spacer(230) formed in the sidewall of the charge transport unit in which the blocking film is formed.

Description

Image sensor and method of manufacturing the same

The present invention relates to an image sensor and a manufacturing method thereof, and more particularly, to a manufacturing method of an image sensor with improved productivity and reliability.

An image sensor is an element that converts an optical image into an electrical signal. Recently, with the development of the computer industry and the communication industry, the demand for improved image sensors in various fields such as digital cameras, camcorders, personal communication systems (PCS), gaming devices, security cameras, medical micro cameras, robots, etc. is increasing. have.

The unit pixel of the image sensor may include a photoelectric converter configured to photoelectrically convert incident light, a charge detector configured to receive charge, and a charge transmitter configured to transfer charges generated by the photoelectric converter to the charge detector. The charge transfer unit may include a gate insulating layer, a gate electrode, and a spacer, and the spacer may self-align the ion implantation region during an ion implantation process. However, in recent years, as the size of an image sensor is reduced in size, a short channel effect is generated, and a double spacer structure is formed to reduce the short channel effect.

At this time, during formation of the double spacer, an etching mask is formed on the photoelectric conversion unit to protect the photoelectric conversion unit every time each spacer is formed in order to prevent the photoelectric conversion unit from being damaged. Therefore, the process is complicated because two etching mask formation and removal processes are performed. As a result, there was a difficulty in increasing the process cost and decreasing the process yield.

The problem to be solved by the present invention is to provide an image sensor with improved productivity.

Another object of the present invention is to provide a method of manufacturing an image sensor having improved productivity.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

An image sensor according to an embodiment of the present invention for solving the above problems is a semiconductor substrate, a charge transfer unit formed on the semiconductor substrate, a photoelectric conversion unit formed in the semiconductor substrate on one side of the charge transfer unit to accumulate charge; A charge detector formed in the semiconductor substrate on the other side of the charge transfer unit to receive the charge accumulated in the photoelectric conversion unit and convert the charge into an electrical signal, a first spacer formed on the sidewall of the charge transfer unit, and the photoelectric conversion unit; A blocking film conformally formed on the semiconductor substrate including the first spacer and the charge transfer unit, and a second spacer formed on a sidewall of the charge transfer unit in which the blocking layer is formed.

According to another aspect of the present invention, there is provided a method of manufacturing an image sensor, in which a charge transfer part is formed on a semiconductor substrate, and an ion implantation process is performed on one side of the charge transfer part to form a photoelectric conversion part in the semiconductor substrate. A first spacer is formed on sidewalls of the charge transfer part and the photoelectric conversion part, a low concentration impurity region aligned with the first spacer is formed, and a blocking film is formed on the charge transfer part and the first spacer; And forming a second spacer on a sidewall of the charge transfer part in which the blocking film is formed, and forming a high concentration impurity region aligned with the second spacer.

Other specific details of the invention are included in the detailed description and drawings.

According to the image sensor and the manufacturing method thereof according to the embodiments of the present invention, by forming the blocking film before the second spacer, it is possible to prevent damage to the photoelectric conversion portion that may occur during the etching process. In addition, the semiconductor substrate may be prevented from being exposed by under cut that may occur during the wet etching process, thereby preventing silicide of the semiconductor substrate, thereby improving reliability of the image sensor. In addition, since the blocking layer protects the photoelectric conversion unit from being damaged during the etching process for forming the second spacer, the etching mask does not need to be separately formed, and thus the process may be omitted in the series according to the etching mask formation. Therefore, the process cost is reduced and the process yield is increased, there is an advantage that the productivity is improved.

Advantages and features of the present invention, and methods of achieving the same will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the embodiments are to make the disclosure of the present invention complete, and the general knowledge in the technical field to which the present invention belongs. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Thus, well-known device structures and well-known techniques in some embodiments are not described in detail in order to avoid obscuring the present invention. Furthermore, n-type or p-type is exemplary, and each embodiment described and illustrated herein also includes its complementary embodiment. Like reference numerals refer to like elements throughout.

An image sensor according to embodiments of the present invention includes a charge coupled device (CCD) and a CMOS image sensor. Here, the CCD has less noise and better image quality than the CMOS image sensor, but requires a high voltage and a high process cost. CMOS image sensors are simple to drive and can be implemented in a variety of scanning methods. In addition, the signal processing circuit can be integrated into a single chip, which enables the miniaturization of the product, and the CMOS processing technology can be used interchangeably to reduce the manufacturing cost. Its low power consumption makes it easy to apply to products with limited battery capacity. Therefore, hereinafter, a CMOS image sensor will be described as an image sensor of the present invention. However, the technical idea of the present invention can be applied to the CCD as it is.

Hereinafter, an image sensor according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an image sensor according to an exemplary embodiment.

Referring to FIG. 1, an image sensor according to an embodiment of the present invention may include an active pixel sensor array (APS array) 10, a timing generator 20, and a row decoder. 30, a row driver 40, a correlated double sampler (CDS) 50, an analog to digital converter (ADC) 60, a latch (70) ) And a column decoder 80 or the like.

The active pixel sensor array 10 includes a plurality of unit pixels arranged in two dimensions. A plurality of unit pixels serve to convert an optical image into an electrical signal. The active pixel sensor array 10 is driven by receiving a plurality of driving signals such as a pixel selection signal ROW, a reset signal RST, a charge transfer signal TG, and the like from the row driver 40. The converted electrical signal is also provided to the correlated double sampler 50 via a vertical signal line.

The timing generator 20 provides a timing signal and a control signal to the row decoder 30 and the column decoder 80.

The row driver 40 provides a plurality of driving signals to the active pixel sensor array 10 for driving the plurality of unit pixels according to the result decoded by the row decoder 30. In general, when unit pixels are arranged in a matrix form, a driving signal is provided for each row.

The correlated double sampler 50 receives, holds, and samples electrical signals formed in the active pixel sensor array 10 through vertical signal lines. That is, a specific reference voltage level (hereinafter referred to as "noise level") and a voltage level (hereinafter referred to as "signal level") by the formed electrical signal are sampled twice, corresponding to the difference between the noise level and the signal level. Output the difference level.

The analog-to-digital converter 60 converts an analog signal corresponding to the difference level into a digital signal and outputs the digital signal.

The latch unit 70 latches the digital signal, and the latched signal is sequentially output from the column decoder 80 to the image signal processor (not shown) according to the decoding result.

2 is an equivalent circuit diagram of a unit pixel of an image sensor according to an exemplary embodiment.

Referring to FIG. 2, the unit pixel 100 of the image sensor according to the exemplary embodiment may include a photoelectric converter 110, a charge detector 120, a charge transmitter 130, a reset unit 140, and amplification. The unit 150 and the selection unit 160 are included. In the exemplary embodiment of the present invention, the unit pixel 100 has a four transistor structure as shown in FIG. 2, but may have a five transistor structure.

The photoelectric converter 110 absorbs incident light and accumulates charges corresponding to the amount of light. The photoelectric converter 110 may be a photo diode, a photo transistor, a photo gate, a pinned photo diode (PPD), and a combination thereof.

As the charge detector 120, a floating diffusion region (FD) is mainly used, and the charge accumulated in the photoelectric converter 110 is transferred. Since the charge detector 120 has a parasitic capacitance, charges are accumulated cumulatively. The charge detector 120 is electrically connected to the gate of the amplifier 150 to control the amplifier 150.

The charge transfer unit 130 transfers charges from the photoelectric conversion unit 110 to the charge detection unit 120. The charge transfer unit 130 generally includes one transistor and is controlled by a charge transfer signal TG.

The reset unit 140 periodically resets the charge detector 120. The source of the reset unit 140 is connected to the charge detector 120 and the drain is connected to Vdd. It is also driven in response to the reset signal RST.

The amplifier 150 serves as a source follower buffer amplifier in combination with a constant current source (not shown) located outside the unit pixel 100, and changes in response to the voltage of the charge detector 120. The voltage is output to the vertical signal line 162. The source is connected to the drain of the selector 160 and the drain is connected to Vdd.

The selector 160 selects the unit pixel 100 to be read in units of rows. Driven in response to the select signal ROW, the source is coupled to a vertical signal line 162.

In addition, the driving signal lines 131, 141, and 161 of the charge transfer unit 130, the reset unit 140, and the selector 160 may be driven in the row direction (horizontal direction) so that the unit pixels included in the same row are simultaneously driven. Is extended.

3 is a schematic plan view of a unit pixel of an image sensor according to an exemplary embodiment. 4 is a cross-sectional view taken along the line IV-IV 'of FIG. 3.

3 and 4, an image sensor according to an exemplary embodiment may include a semiconductor substrate 101, a photoelectric converter 110, a charge detector 120, a charge transmitter 130, and a first spacer ( 210, a blocking layer 220, and a second spacer 230. In the exemplary embodiment of the present invention, the photoelectric converter 110 is a pinned photo diode (PPD). However, the photoelectric converter 110 may be applied to a photo diode, a photo transistor, or the like.

The semiconductor substrate 101 is of a first conductivity type (eg, N-type) and is formed in the deep well 107 of the second conductivity type (eg, P-type) formed at a predetermined depth in the semiconductor substrate 101. By the lower substrate region 101a and the upper substrate region 101b. Here, the semiconductor substrate 101 has been described using an N type as an example, but is not limited thereto.

The deep well 107 forms a potential barrier to prevent charges generated deep in the lower substrate region 101a from flowing into the photoelectric converter 110 and increases recombination of charges and holes. It plays a role. Therefore, cross talk between pixels due to random drift of charges can be reduced.

The deep well 107 may be formed to have a highest concentration, for example, at a depth of about 3-12 μm from the surface of the semiconductor substrate 101 and have a layer thickness of about 1-5 μm. Here, 3 to 12 μm is substantially the same as the absorption length of red or near infrared region light in silicon. The deeper the depth of the well 107 is from the surface of the semiconductor substrate 101, the greater the diffusion prevention effect, so that the occurrence of crosstalk is reduced, but the depth of the photoelectric conversion section 110 is also shallower to deepen the photoelectricity. Sensitivity to incident light having a long wavelength (eg, red wavelength) with a relatively high conversion ratio may be lowered. Therefore, the formation position of the deep well 107 can be adjusted according to the wavelength region of the incident light.

An isolation region 109 may be formed in the upper substrate region 101a of the semiconductor substrate 101 to define an active region. In general, the device isolation region 109 may be a field oxide (FOX) or a shallow trench isolation (STI) using a LOCOS (LOCal Oxidation of Silicon) method.

In addition, a separation well 108 of a second conductivity type (eg, P-type) may be formed under the device isolation region 109. The separation well 108 defines each pixel unit of the image sensor. Separation well 108 may include, for example, a higher concentration of P-type impurities than peripheral upper substrate region 101a. The separation well 108 may reduce cross talk in a horizontal direction between each pixel unit of the image sensor by preventing charge from moving from one pixel to another pixel. In addition, the isolation well 108 may be formed deeper than the formation depth of the photodiode 112 to reduce cross talk, or may be formed in connection with the deep well 107 as illustrated in FIG. 4.

The charge transfer unit 130 is formed on the semiconductor substrate 101 and includes a gate insulating layer 131 and a gate electrode 132.

The gate insulating layer 131 is formed of SiO ₂ , SiON, SiN, Al ₂ O 3, Si ₃ N ₄ , Ge _x O _y N _z , Ge _x Si _y O _z Or high dielectric constant materials may be used. Here, the high dielectric constant material may form HfO ₂ , ZrO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ , hafnium silicate, zirconium silicate, or a combination thereof, by atomic layer deposition. In addition, the gate insulating layer 134 may be formed by stacking two or more selected materials from a plurality of layers. The gate insulating layer 131 may be formed to have a thickness of about 5 to about 100 GPa.

The gate electrode 132 is stacked on the gate insulating layer 131. The gate electrode 132 is a conductive polysilicon film, a metal film such as W, Pt, or Al, a metal nitride film such as TiN, or a metal obtained from a refractory metal such as Co, Ni, Ti, Hf, or Pt. It may consist of a silicide film or a combination film thereof. In addition, the gate electrode 132 may be formed by stacking a conductive polysilicon film and a metal silicide film in order, or may be formed by stacking a conductive polysilicon film and a metal film in order, but is not limited thereto.

The photoelectric conversion unit 110 is formed on one side of the charge transfer unit 130 and includes an N-type photodiode 112 and a P ⁺ type pinning layer 114 formed in the semiconductor substrate 101. do.

Charges generated in response to incident light are accumulated in the photodiode 112, and the pinning layer 114 serves to reduce dark current by reducing an electro-hole pair (EHP) generated thermally in the upper substrate region 101b. . In addition, since the photodiode 112 is formed to be spaced apart from the deep well 107 by a predetermined distance, the photodiode 112 may be used as a region for photoelectric conversion of the upper substrate region 101b under the photodiode 112. Thus, color sensitivity for long wavelengths (eg, red wavelengths) having a large penetration depth in silicon can be improved.

The maximum impurity concentration of the photodiode 112 may be 1 × 10 ¹⁵ to 1 × 10 ¹⁸ atoms / cm ³ , and the impurity concentration of the pinning layer 114 may be 1 × 10 ¹⁷ to 1 × 10 ²⁰ atoms / cm ^3. Can be. However, the concentration and the location to be doped may vary depending on the manufacturing process and design is not limited thereto.

The charge detector 120 is formed on the other side of the charge transfer unit 130. The charge detector 120 is a region doped with N-type impurities, for example, and receives charges accumulated in the pinning layer 114 through the charge transfer unit 130. The charge detector 120 includes a low concentration impurity region 121 and a high concentration impurity region 122. That is, the charge detector 120 may have a lightly doped drain (LDD) structure or a doubled doped drain (DDD) structure. In this case, the low concentration impurity region 121 is formed in alignment with the first spacer 210 to be described later, and the high concentration impurity region 122 is formed in alignment with the second spacer.

As described above, the photoelectric conversion unit 110 is positioned on one side of the charge transfer unit 130, and the charge detector 120 is located on the other side of the charge transfer unit 130, centering on the charge transfer unit 130. Here, "one side" and "other side" mean relative directions that may be reversed, and are not limited to the positions shown in the drawings.

The first spacer 210 is formed on the sidewall of the charge transfer unit 130 and the photoelectric conversion unit 110 and may be, for example, an oxide film. The first spacer 210 is formed on the sidewall of the charge transfer unit 130 by performing an etching process, for example, an anisotropic etching process, to form the first spacer 210. In addition, when the first spacer 210 is formed, the first spacer 210 may be formed by covering the photoelectric converter 110 with an etching mask and then performing an etching process so as to minimize damage to the photoelectric converter 110 due to the etching process. It is also formed on the photoelectric conversion unit 110. In this case, the etching mask may be formed on a portion of the charge transfer unit 130 including the photoelectric conversion unit 110. Therefore, the first spacer 210 may be formed to extend on the sidewalls of the charge transfer unit 130 adjacent to the photoelectric converter 110 and the photoelectric converter 110.

The blocking layer 220 is conformally formed on the semiconductor substrate 101 including the first spacer 210 and the charge transfer unit 130. In this case, the blocking film 220 may be formed in a double film structure of the first blocking film 221 and the second blocking film 222. In this case, the first blocking layer 221 may be an etch stop layer as an oxide layer, and the second blocking layer 222 may be a nitride layer. Of course, the blocking film 220 may be a single film made of a nitride film or an oxide film.

In the blocking film 220, the silicide film is formed by contacting the semiconductor substrate 101 with a metal film (eg, Co, Ti, Ni, W, etc.) in an unwanted region in a subsequent silicide film forming process. It can serve as a silicide protective film to prevent. In addition, since the blocking layer 220 is formed on the first spacer 210, damage of the photoelectric conversion unit 110, which may occur in the process of forming the second spacer 230 to be described later, may be prevented, thereby improving reliability of the image sensor. There is an advantage to be improved.

The second spacer 230 is formed on the sidewall of the charge transfer unit 130 on which the blocking layer 220 is formed. The second spacer 230 may be, for example, a nitride film. Unlike the first spacer 210, the second spacer 230 is protected by the blocking film 220 during the etching process for forming the second spacer 230. That is, the second spacer 230 is formed by performing an etching process, for example, anisotropic etching, on the entire surface of the semiconductor substrate 101 without a separate etching mask. Therefore, since the etching mask pattern forming and removing process may be omitted, the manufacturing process of the image sensor may be simplified to further reduce the process cost and increase the process efficiency. In other words, productivity can be much improved. Although not illustrated in the drawings, an etch stop layer of the second spacer 230, for example, an oxide layer, may be further formed between the second spacer 230 and the blocking layer 220.

According to the image sensor according to the exemplary embodiment of the present invention, the blocking film 220 is formed under the second spacer 230 to damage the photoelectric conversion unit 110 that may occur during the etching process of the second spacer 230. This can improve the reliability of the image sensor. In addition, the blocking layer 220 formed under the second spacer 230 does not need to form a separate etching mask to protect the photoelectric conversion unit 110 during the etching process for forming the second spacer 230. The productivity of the sensor can be further increased. In addition, the blocking layer 220 is formed between the semiconductor substrate 101 and the second spacer 230 to prevent the semiconductor substrate 101 from being exposed by an under cut that may occur in a subsequent wet process. Therefore, the semiconductor substrate 101 may be prevented from being silicided in an unwanted shell.

Hereinafter, a manufacturing method of an image sensor according to an exemplary embodiment of the present invention will be described with reference to FIGS. 5 to 10. The same reference numerals are used for constituent elements substantially the same as those of the image sensor according to the exemplary embodiment, and detailed descriptions of the same reference numerals will be omitted or simplified.

5 to 10 are cross-sectional views of intermediate structures for explaining a method of manufacturing an image sensor according to an embodiment of the present invention.

Referring to FIG. 5, the charge transfer unit 130 is formed on the semiconductor substrate 101, the photoelectric conversion unit 110 is formed on one side of the charge transfer unit 130, and on the semiconductor substrate 101. The first spacer layer 210a is formed.

First, a first conductive type (eg, N-type) semiconductor substrate 101 is provided, and a second well type (eg, P-type) deep well 107 at a predetermined depth in the semiconductor substrate 101. The lower substrate region 101b and the upper substrate region 101a may be defined. An isolation region 109 may be formed in the upper substrate region 101a of the semiconductor substrate 101 to define an active region, and in general, a FOX or STI may be formed using a LOCOS method. A second conductive isolation well 108 may be formed below the device isolation region 109 to define each pixel unit of the image sensor.

Subsequently, the gate insulating layer 131 and the gate electrode 132 are stacked to form the charge transfer unit 130. In this case, the gate insulating layer 131 may be an oxide film, a nitride film, or a combination thereof. For example, the gate insulating film 131 may be formed by a method such as CVD (chemical vapor deposition) or PVD (physical vapor deposition). Can be. The gate electrode 132 is formed on the gate insulating film 131 and has a conductive polysilicon film, a metal film such as W, Pt, or Al, a metal nitride film such as TiN, or a Co, Ni, Ti, Hf, Pt It may be a metal silicide film obtained from a refractory metal, or a combination film thereof. In addition, the gate electrode 132 may be formed by, for example, CVD or PVD.

Subsequently, the photoelectric conversion unit 110 is formed on one side of the charge transfer unit 130. The photoelectric conversion unit 110 implants impurities into the active region (not shown) to form the photodiode 112 and the pinning layer 114. In this case, the photodiode 112 may be N-type, and the pinning layer 114 may be ion implanted with P ⁺ -type impurities.

Subsequently, the first spacer layer 210a is conformally formed on the semiconductor substrate 101 including the charge transfer unit 130. The first spacer layer 210a may be, for example, an oxide film or a nitride film, and may be formed by a method such as CVD or PVD.

Subsequently, referring to FIG. 6, an etching mask 250 covering the photoelectric converter 110 is formed.

The etching mask 250 may be, for example, a photoresist. The etching mask 250 serves to prevent the photoelectric conversion unit 110 from being damaged in the subsequent etching process. In this case, in order to minimize damage to the photoelectric conversion unit 110, an etching mask 250 may be formed with a predetermined margin. That is, the etching mask 250 may be formed by including a portion of the charge transfer unit 130.

Subsequently, referring to FIG. 7, the first spacer 210 is formed and an ion implantation process is performed to form the low concentration impurity region 121 aligned with the first spacer 210.

The first spacer 210 may be formed by performing an etching process on the above-described etching mask (see 250 of FIG. 6). At this time, the etching process may perform an anisotropic etching process, for example. In addition, the low concentration impurity region 121 is formed to be aligned with the first spacer 210.

8, a blocking film 220 is conformally formed on the semiconductor substrate 101 including the first spacer 210 and the charge transfer unit 130.

The blocking film 220 may be formed by sequentially stacking the first blocking film 221 and the second blocking film 222. In this case, the first blocking film 221 may be an oxide film, the second blocking film 222 may be a nitride film, and the first blocking film 221 and the second blocking film 222 may be formed by CVD or PVD. can do. Of course, the blocking film 220 may be formed as a single film of a nitride film or an oxide film.

By forming the blocking layer 220 on the first spacer 210, it is possible to prevent the photoelectric conversion unit 110 from being damaged during the subsequent second spacer formation process. That is, the reliability of the image sensor may be improved.

9, a second spacer layer 230a is formed on the blocking film 220. The second spacer layer 230a may be, for example, a nitride film. In addition, the second spacer layer 230a may be formed by a method such as CVD or PVD. In this case, although not shown in the drawing, for example, an oxide film may be further formed on the blocking film 220 as an etch stop film. In particular, when both of the second blocking film 222 and the second spacer layer 230a of the blocking film 220 are nitride films, an oxide film may be further formed as an etch stop film.

Subsequently, referring to FIG. 10, a second spacer 230 is formed on sidewalls of the charge transfer part 130 on which the blocking film 220 is formed, and the high concentration impurity region 122 aligned with the second spacer 230 is formed. Form.

The second spacer 230 may be formed by, for example, performing an anisotropic etching process on the aforementioned second spacer layer (see 230a of FIG. 9). In this case, since the blocking layer 220 is present under the second spacer layer 230a, the photoelectric conversion unit 110 may not be damaged by an etching process, and thus a separate etching mask may not be formed. Therefore, since the etch mask layer and the etch mask pattern are not formed and a series of processes such as the removal of the etch mask pattern are not required, the process may be further simplified. In other words, the productivity is improved.

In addition, the high concentration impurity region 122 may be formed by ion implanting N-type impurities, for example, and use impurities having a higher concentration than the low concentration impurity region 121. The high concentration impurity region 122 may be formed to be aligned with the second spacer 130 to form the charge detection unit 120 having an LDD or DDD structure.

At this time, the ion implantation energy uses higher energy when the low concentration impurity region 121 is formed. When the low concentration impurity region 121 is formed, an ion implantation process is performed directly on the semiconductor substrate 101. However, in the case of the high concentration impurity region 122, the blocking film 220 is formed on the semiconductor substrate 101. Because.

According to the manufacturing method of the image sensor according to the exemplary embodiment of the present invention, the blocking film 220 is formed under the second spacer 230 to form the photoelectric conversion part 110 that may occur during the etching process of the second spacer 230. ) Can improve the reliability of the image sensor. In addition, during the etching process for forming the second spacer 230, it is not necessary to form a separate etching mask 250 to cover the photoelectric conversion unit 110, thereby further increasing the productivity of the image sensor. In addition, the blocking film 220 is prevented from being exposed to the semiconductor substrate 101 by an under cut which may occur in a subsequent wet process, thereby preventing the semiconductor substrate 101 from being silicided in an unwanted region. It may be. That is, the manufacturing method of the image sensor according to an embodiment of the present invention has the advantage of improving both the reliability and productivity of the image sensor.

11 is a schematic diagram illustrating a processor-based system including an image sensor according to embodiments of the present disclosure.

Referring to FIG. 11, the processor-based system 300 is a system that processes an output image of the CMOS image sensor 310. The system 300 may illustrate a computer system, a camera system, a scanner, a mechanized clock system, a navigation system, a videophone, a supervision system, an auto focus system, a tracking system, a motion monitoring system, an image stabilization system, etc., but is not limited thereto. It doesn't happen.

Processor-based system 300, such as a computer system, includes a central information processing unit (CPU) 320, such as a microprocessor, that can communicate with input / output (I / O) device 330 via bus 305. CMOS image sensor 310 may communicate with the system via a bus 305 or other communication link. In addition, processor-based system 300 may include RAM 340, floppy disk drive 350 and / or CD ROM drive 355, and port 360, which may communicate with CPU 320 via bus 305. It may further include. The port 360 may be a port for coupling a video card, a sound card, a memory card, a USB device, or the like, or for communicating data with another system. The CMOS image sensor 310 may be integrated with a CPU, a digital signal processing device (DSP), a microprocessor, or the like. In addition, the memories may be integrated together. In some cases, of course, it may be integrated into a separate chip from the processor.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

1 is a block diagram of an image sensor according to an exemplary embodiment.

2 is an equivalent circuit diagram of a unit pixel of an image sensor according to an exemplary embodiment.

3 is a schematic plan view of a unit pixel of an image sensor according to an exemplary embodiment.

4 is a cross-sectional view taken along the line IV-IV 'of FIG. 3.

5 to 10 are cross-sectional views of intermediate structures for explaining a method of manufacturing an image sensor according to an embodiment of the present invention.

11 is a schematic diagram illustrating a processor-based system including an image sensor according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

10: active pixel sensor array 20: timing generator

30: row decoder 40: row driver

50: correlated double sampler 60: analog-to-digital converter

70: latch portion 80: thermal decoder

100: unit pixel 101: semiconductor substrate

101a: lower substrate region 101b: upper substrate region

107: deep well 108: separation well

109: device isolation region 110: photoelectric conversion section

112: photodiode 114: pinning layer

120: charge detector 121: low concentration impurity region

122: high concentration impurity region 130: charge transfer portion

131: gate insulating film 132: gate electrode

140: reset unit 150: amplification unit

160: selection unit 210: first spacer

220: blocking film 221: first blocking film

222: second blocking film 230: second spacer

250: etching mask 300: processor-based system

305: bus 310: CMOS image sensor

320: central information processing unit 330: I / O element

340: RAM 350: floppy disk drive

355: CD ROM Drive 360: Port

Claims (9)

Semiconductor substrates; A charge transfer part formed on the semiconductor substrate; A photoelectric conversion unit formed in the semiconductor substrate on one side of the charge transfer unit to accumulate charge; A charge detection unit formed in the semiconductor substrate on the other side of the charge transfer unit to receive the charge accumulated in the photoelectric conversion unit and convert the charge into an electric signal; First spacers formed on sidewalls of the charge transfer part and on the photoelectric conversion part; A blocking film conformally formed on the semiconductor substrate including the first spacer and the charge transfer unit; And And a second spacer formed on sidewalls of the charge transfer part in which the blocking layer is formed. According to claim 1, The blocking film has a double film structure including a first blocking film and a second blocking film. The method of claim 2, The first blocking film is an oxide film, and the second blocking film is a nitride film. According to claim 1, Further comprising an etching prevention film which is an oxide film on the blocking film, And the second spacer is a nitride film. A charge transfer part is formed on the semiconductor substrate, An ion implantation process is performed on one side of the charge transfer unit to form a photoelectric conversion unit in the semiconductor substrate, Forming a first spacer on sidewalls of the charge transfer part and on the photoelectric conversion part, Forming a low concentration impurity region aligned with the first spacer, Forming a blocking layer on the charge transfer unit and the first spacer, Forming a second spacer on a sidewall of the charge transfer part in which the blocking film is formed; And forming a high concentration impurity region aligned with said second spacer. The method of claim 5, The blocking film includes a first blocking film and a second blocking film, The first blocking film is an oxide film, and the second blocking film is a nitride film. The method of claim 5, Forming the second spacer, Forming a second spacer layer on the blocking film; And removing the second spacer layer by performing anisotropic etching. The method of claim 7, wherein Before forming the second spacer layer, The method may further include forming an etch stop layer, which is an oxide layer, on the blocking layer. And the second spacer layer is a nitride film. The method of claim 5, Forming the high concentration impurity region, And performing an ion implantation process at higher energy when forming the low concentration impurity region.

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