KR20090016191A - Phase change memory device - Google Patents

Abstract

A phase change memory device is provided to drive stably and efficiently a row data buffer when a data page size of a sense amplifier is smaller than the row data buffer. A plurality of banks(10_0-10_3) includes phase change resistance cells. A plurality of column switches(CSW) are connected to a plurality of bit lines in order to be controlled by a plurality of column selection signals(CS1-CSm). A sense amplifier(S/A) senses and amplifies data applied from the banks. A bank selection unit(20) outputs selectively the data applied from the sense amplifier according to the bank addresses. A column selection unit(30_0-30_3) outputs selectively the data applied from the bank selection unit. A row data buffer(RDB0-RDB3) buffers the data applied from the column selection unit.

Description

Phase change memory device

1A and 1B are diagrams for explaining a conventional phase change resistance element.

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

4 is a block diagram of a conventional LPDDR nonvolatile memory.

5 is an operation flowchart of a conventional LPDDR nonvolatile memory.

6 is a block diagram of a cell array of a phase change memory device according to the present invention;

7 is an operation flowchart of a phase change memory device according to the present invention;

8 is a configuration diagram of a low data buffer of a phase change memory device according to the present invention;

FIG. 9 is a diagram for describing a first active cycle in bank 0 of the phase change memory device of FIG. 8. FIG.

FIG. 10 is a diagram for describing a second active cycle in bank 0 of the phase change memory device of FIG. 8. FIG.

FIG. 11 is a diagram for describing an m th active cycle in bank 0 of the phase change memory device of FIG. 8; FIG.

FIG. 12 is a diagram for describing a first active cycle in bank 3 of the phase change memory device of FIG. 8. FIG.

FIG. 13 is a diagram for describing a second active cycle in bank 3 of the phase change memory device of FIG. 8. FIG.

FIG. 14 is a diagram for describing an m th active cycle in bank 3 of the phase change memory device of FIG. 8; FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase change memory device, and is a technique for driving a row data buffer stably and efficiently.

In general, nonvolatile memories such as magnetic memory and phase change memory (PCM) have data processing speeds of about volatile random access memory (RAM) and preserve data even when the power is turned off. Has the property of being.

1A and 1B are diagrams for explaining a conventional phase change resistor (PCR) element 4.

When the phase change resistance element 4 applies a voltage and a current by inserting a phase change material (PCM) 2 between the top electrode 1 and the bottom electrode 3, a phase is applied. The high temperature is induced in the change layer 2 to change the state of electrical conduction according to the change in resistance. Here, AglnSbTe is mainly used as the material of the phase change layer 2. In addition, the phase change layer 2 uses a chalcogenide (chalcogenide) mainly composed of chalcogen elements (S, Se, Te), specifically, a germanium antimony tellurium alloy material consisting of Ge-Sb-Te (Ge2Sb2Te5 ) Can also be used.

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

As shown in FIG. 2A, when a low current of less than or equal to a threshold flows through the phase change resistance element 4, the phase change layer 2 is at a temperature suitable for crystallization. As a result, the phase change layer 2 is in a crystalline phase to become a material having a low resistance state.

On the other hand, as shown in FIG. 2B, when a high current of more than a threshold flows through the phase change resistance element 4, the temperature of the phase change layer 2 becomes higher than the melting point. As a result, the phase change layer 2 is in an amorphous state and becomes a material of a high resistance state.

As described above, the phase change resistive element 4 can non-volatilely store data corresponding to the states of the two resistors. That is, if the phase change resistance element 4 is in the low resistance state, the data is "1", and in the high resistance state is the data "0", the logic state of the two data can be stored.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

When a current flows between the top electrode 1 and the bottom electrode 3 of the phase change resistance element 4 for a predetermined time, high heat is generated. Thereby, the state of the phase change layer 2 changes into a crystalline phase and an amorphous phase by the temperature state applied to the top electrode 1 and the bottom electrode 3.

At this time, when a low current flows for a predetermined time, a crystal phase is formed by a low temperature heating state, and the phase change resistance element 4, which is a low resistance element, is set. On the contrary, when a high current flows for a predetermined time, an amorphous phase is formed by a high temperature heating state, and the phase change resistance element 4, which is a high resistance element, is reset. Thus, these two phase differences are represented by electrical resistance change.

Accordingly, a low voltage is applied to the phase change resistance element 4 for a long time to write the set state in the write operation mode. On the other hand, in the write operation mode, a high voltage is applied to the phase change resistance element 4 for a short time to write the reset state.

4 is an address block diagram defined in the Low Power Double-Data-Rate (LPDDR) nonvolatile memory standard of the Joint Electron Device Engineering Council (JEDEC). Conventional LPDDR nonvolatile memory supplies an array address in three phases.

First, some of the row addresses RA <N: 0> are input through the address pin during the preactive command period. The row address RA is input through one row address buffer RAB selected from the bank addresses BA0 and BA1 among the four row address buffers RAB0 to RAB3.

During the active instruction period, one row address buffer RAB is selected by bank addresses BA0 and BA1 from four row address buffers RAB0 to RAB3. Accordingly, the row address stored in the selected row address buffer RAB is stored in the row address register RADD_R1. The remaining row address RA is stored in the row address register RADD_R2 through the address pin.

In this way, all the row addresses are determined by the two row address registers RADD_R1 and RADD_R2. The row addresses stored in the row address registers RADD_R1 and RADD_R2 are output to the memory array 1 through the row decoder RD.

In addition, the sense amplifier SA is activated during the active command period. One row data buffer RDB is selected from the four row data buffers RDB0 to RDB3 by the bank addresses BA0 and BA1. Accordingly, the data amplified by the sense amplifier SA through the memory array 1 is transferred to the selected row data buffer RDB.

Meanwhile, one row data buffer RDB is selected from the four row data buffers RDB0 to RDB3 by the bank addresses BA0 and BA1 during a read or write command period. The column address CA <N: 0> is input to the output state machine 2 through the address pin to select the start word of the read burst or the write burst. do. In addition, the data selected by the column address CA is output to the outside via the output pin DQ.

Here, when the corresponding row address RA is input to the corresponding row address buffer RAB in the preactive instruction section, the pre-active command does not need to be used. In addition, in the active command period, when the corresponding row data is input to the corresponding row data buffer RDB, the active command does not need to be used.

5 is a flowchart illustrating operations of a conventional LPDDR nonvolatile memory.

First, when a preactive command is applied (step S1), the row address buffer RAB is operated to buffer the input row address RA. (Step S2) After that, if an active command is applied (step S3), the sense amplifier SA Is activated to amplify the data in the memory array 1 (step S4).

Accordingly, when the page size is N, N-bit data is applied to the row data buffer RDB. (Step S5) Next, the read operation is performed according to the row address RA and column address CA applied to the row data buffer RDB. (Step S6).

Here, when the data page size of the sense amplifier SA and the data page size stored in one row data buffer RDB are the same, all data of one row data buffer RDB can be input by one active operation.

However, when the data page size of the sense amplifier SA is small in the data page size stored in one row data buffer RDB, the data of one row data buffer RDB cannot be input by one active operation.

Such a conventional phase change memory device must change the size of the row address buffer RAB in order to increase the page size, and therefore the size of the row data buffer RDB must be changed. Therefore, there is a problem in that the structure of the bank core must be changed when changing the page size.

In addition, the size of the conventional row data buffer RDB is determined by the number of sense amplifiers SA which is a page size of one bank. That is, in the conventional phase change memory device, the page size is determined only by the number of sense amplifiers SA.

Accordingly, when the operation of one row data buffer RDB is completed, the first step is entered to operate the new row data buffer RDB, and the pre-active operation (step S1), the row address buffer operation (step S2) and the active operation (step S3) Will be performed again. Therefore, there is a problem that the operating time of the row data buffer RDB takes a lot.

The present invention has the following object.

First, when the data page size of the sense amplifier is smaller than the ROH data buffer, the purpose of the ROH data buffer can be driven stably and efficiently.

Second, the purpose is to reduce the operating time of the ROH data buffer by separating the ROH data buffer for each bank.

The phase change memory device of the present invention detects a crystallization state that changes according to the magnitude of a current, stores data corresponding to a change in resistance, and includes a phase change resistance cell formed in an area where a bit line and a word line cross each other. Banks; A plurality of column switches connected to the bit lines and controlled by the plurality of column selection signals; A sense amplifier for sensing and amplifying data applied from the bank through a plurality of column switches; Bank selecting means for selectively outputting data applied from the sense amplifier in accordance with the bank address; Column selecting means for selectively outputting data applied from the bank selecting means depending on whether the plurality of column selection signals are activated; And a row data buffer for buffering the data applied from the column selecting means.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

6 is a configuration diagram illustrating a cell array of a phase change memory device according to the present invention.

According to the present invention, a plurality of bit lines BL0 to BL3 are provided in the row direction. A plurality of word lines WL0 to WL3 are provided in the column direction. A phase change resistor cell is included in an area where the plurality of bit lines BL0 to BL3 and the plurality of word lines WL0 to WL3 cross each other. Each unit cell C of the phase change resistance cell includes a phase change resistance element PCR and a diode D. Here, it is preferable that the diode D consists of a PN diode element.

One electrode of the phase change resistance element PCR is connected to the bit line BL, and the other electrode is connected to the P-type region of the diode D. The N-type region of diode D is connected to wordline WL.

In the present invention, a low voltage is applied to the selected word line WL in the read mode. Then, the read voltage Vread is applied to the bit line BL so that the read current Iset in the set state or the read current Ireset in the reset state is set through the bit line BL, the phase change resistance element PCR, and the diode D. Flow towards WL.

The column switches CSW1 to CSW4 are connected to the bit lines BL0 to BL3 in one-to-one correspondence. The plurality of column switches CSW1 to CSW4 selectively control the connection between the bit line BL and the sense amplifier S / A according to the plurality of column selection signals CS1 to CS4.

The sense amplifier S / A distinguishes the data "1" and "0" by comparing the cell data applied from the bit line BL and the reference current applied through the reference line through the column switch CSW. Here, the sense amplifiers S / A of the shared structure are shared by the plurality of bit lines BL0 to BL3 through the plurality of column switches CSW1 to CSW4.

Accordingly, when the sense amplifier S / A is activated, only one switch of the plurality of column switches CSW1 to CSW4 is activated. That is, when the plurality of column switches CSW1 to CSW4 are activated in m order, all cell data of the selected row can be sensed.

7 is a flowchart illustrating operations of a phase change memory device according to the present invention.

First, when a preactive command is applied (step S10), the row address buffer RAB is operated to buffer the input row address RA. (Step S11) After that, if an active command is applied (step S12), the sense amplifier SA Is activated to amplify the data in the memory array (step S13).

Accordingly, when the page size is N, N-bit data is applied to the row data buffer RDB. At this time, if the page size of the row data buffer RDB is m times larger than the page size of the sense amplifier S / A, the page size of the row data buffer RDB is m × N. Therefore, it is not possible to fill all the data of the row data buffer RDB in one active operation. Accordingly, m repeated active operations are required according to the sequential activation of the plurality of column selection signals CS1 to CS4.

At this time, the row address is fixed, and the order of activation of the column switch CSW in the sense amplifier S / A of the shared structure is sequentially adjusted to obtain m × N data.

That is, when the sense amplifier S / A of the shared structure is activated, only one switch of the plurality of column switches CSW1 to CSWm is activated. That is, when the plurality of column switches CSW1 to CSWm are activated in m order, all cell data of the selected row can be sensed. Accordingly, when the sense amplifier S / A is activated, the plurality of column switches CSW1 to CSWm are repeatedly activated m times in sequence (step S14).

Then, the row data buffer RDB is operated to buffer the row data (step S15). That is, the page size is increased in one row data buffer RDB by changing the column switch CSW. Thereafter, the read operation is performed in accordance with the row address RA and the column address CA applied to the row data buffer RDB (step S16).

8 is a configuration diagram illustrating a low data buffer of the phase change memory device according to the present invention.

The present invention provides a plurality of banks (10_0 to 10_3), row decoder RD, column switch CSW, sense amplifier S / A, bank selecting means, a plurality of column selecting means, and a plurality of row data buffers RDB0 to RDB3. Include. Here, it is preferable that the bank selecting means consists of a multiplexer 20, and the column selecting means consists of multiplexers 30_0 to 30_3.

Data output from each sense amplifier S / A is output to the bank select multiplexer 20. The bank select multiplexer 20 multiplexes the output data of the sense amplifier S / A by the bank addresses BA0 and BA1 and outputs them to the respective column select multiplexers 30_0 to 30_3.

Each column select multiplexer 30 multiplexes the outputs of the bank select multiplexer 20 according to the plurality of column select signals CS1 to CSm and outputs them to the row data buffers RDB0 to RDB3. The column select multiplexer 30 transfers data to each row data buffer RDB corresponding to the plurality of column select signals CS1 to CSm. Here, the column select multiplexers 30_0 to 30_3 are preferably provided in the same number as the banks 10_0 to 10_3.

Each row data buffer RDB0 to RDB3 includes m sub row data buffers S_RDB1 to S_RDBm. Here, the page size of one sense amplifier S / A is preferably the same as the page size of one sub-row data buffer S_RDB. In addition, the number of the plurality of sub-row data buffers S_RDB1 to S_RDBm and the number of the column selection signals CS1 to CSm are the same, it is preferable to be activated in a one-to-one correspondence.

FIG. 9 is a diagram for describing a first active cycle in bank 0 of the phase change memory device of FIG. 8.

FIG. 9 illustrates a data transfer path when bank 0 is selected from four banks and column selection signal CS1 is enabled among the column selection signals CS1 to CSm.

Like the diagonal arrows, the data in bank 0 is transferred to the column switch CSW according to the first active command. When the column select signal CS1 is enabled, the corresponding column switch CSW1 is turned on and the data of the memory array 10_0 is output to the sense amplifier S / A.

Thereafter, the bank select multiplexer 20 outputs data of the sense amplifier S / A to the selected column select multiplexer 30_0 according to the bank addresses BA0 and BA1. When the column select signal CS1 is enabled, the column select multiplexer 30_0 outputs the data applied from the bank select multiplexer 20 to the selected sub-roo data buffer S_RDB1. At this time, N bits of data are input to one sub-loW data buffer S_RDB1.

FIG. 10 is a diagram for describing a second active cycle in bank 0 of the phase change memory device of FIG. 8.

FIG. 10 illustrates a data transfer path when bank 0 of four banks is selected and column select signal CS2 of the plurality of column select signals CS1 to CSm is enabled.

Like the diagonal arrow, the data in bank 0 is transferred to the column switch CSW according to the second active command. When the column select signal CS2 is enabled, the corresponding column switch CSW2 is turned on to output data of the memory array 10_0 to the sense amplifier S / A.

Thereafter, the bank select multiplexer 20 outputs data of the sense amplifier S / A to the selected column select multiplexer 30_0 according to the bank addresses BA0 and BA1. Then, when the column select signal CS2 is enabled, the column select multiplexer 30_0 outputs data applied from the bank select multiplexer 20 to the selected sub-row data buffer S_RDB2. At this time, N bits of data are inputted into one sub-row data buffer S_RDB2.

FIG. 11 is a diagram for describing an m th active cycle in bank 0 of the phase change memory device of FIG. 8.

11 illustrates a data transfer path when bank 0 is selected from four banks and column selection signal CSm is enabled among the column selection signals CS1 to CSm.

Like the diagonal arrows, the data in bank 0 is transferred to the column switch CSW according to the m th active command. When the column select signal CSm is enabled, the corresponding column switch CSWm is turned on and the data of the memory array 10_0 is output to the sense amplifier S / A.

Thereafter, the bank select multiplexer 20 outputs data of the sense amplifier S / A to the selected column select multiplexer 30_0 according to the bank addresses BA0 and BA1. Then, when the column select signal CSm is enabled, the column select multiplexer 30_0 outputs data applied from the bank select multiplexer 20 to the selected sub-row data buffer S_RDBm. At this time, N bits of data are input to one sub-loW data buffer S_RDBm.

FIG. 12 is a diagram for describing a first active cycle in bank 3 of the phase change memory device of FIG. 8.

12 illustrates a data transfer path when bank 3 is selected from four banks and column selection signal CS1 is enabled among the column selection signals CS1 to CSm.

Like the diagonal arrows, the data in bank 3 is transferred to the column switch CSW according to the first active command. When the column select signal CS1 is enabled, the corresponding column switch CSW1 is turned on and the data of the memory array 10_3 is output to the sense amplifier S / A.

Thereafter, the bank select multiplexer 20 outputs data of the sense amplifier S / A to the selected column select multiplexer 30_3 according to the bank addresses BA0 and BA1. When the column select signal CS1 is enabled, the column select multiplexer 30_3 outputs the data applied from the bank select multiplexer 20 to the selected sub-roo data buffer S_RDB1. At this time, N bits of data are input to one sub-loW data buffer S_RDB1.

FIG. 13 is a diagram for describing a second active cycle in bank 3 of the phase change memory device of FIG. 8.

FIG. 13 illustrates a data transfer path when bank 3 is selected from four banks and column selection signal CS2 is enabled among the column selection signals CS1 to CSm.

Like the diagonal arrows, the data in bank 3 is transferred to the column switch CSW according to the second active command. When the column select signal CS2 is enabled, the corresponding column switch CSW2 is turned on and the data of the memory array 10_3 is output to the sense amplifier S / A.

Thereafter, the bank select multiplexer 20 outputs data of the sense amplifier S / A to the selected column select multiplexer 30_3 according to the bank addresses BA0 and BA1. Then, when the column select signal CS2 is enabled, the column select multiplexer 30_0 outputs data applied from the bank select multiplexer 20 to the selected sub-row data buffer S_RDB2. At this time, N bits of data are inputted into one sub-row data buffer S_RDB2.

FIG. 14 is a diagram for describing an m th active cycle in bank 3 of the phase change memory device of FIG. 8.

11 illustrates a data transfer path when bank 3 is selected from four banks and column selection signal CSm is enabled among the column selection signals CS1 to CSm.

Like the diagonal arrows, the data in bank 3 is transferred to the column switch CSW according to the m th active command. When the column select signal CSm is enabled, the corresponding column switch CSWm is turned on and the data of the memory array 10_3 is output to the sense amplifier S / A.

Thereafter, the bank select multiplexer 20 outputs data of the sense amplifier S / A to the selected column select multiplexer 30_3 according to the bank addresses BA0 and BA1. Then, when the column select signal CSm is enabled, the column select multiplexer 30_3 outputs data applied from the bank select multiplexer 20 to the selected sub-row data buffer S_RDBm. At this time, N bits of data are input to one sub-loW data buffer S_RDBm.

As described above, the present invention provides the following effects.

According to the present invention, when the data page size of the sense amplifier is smaller than the ROH data buffer, the ROH data buffer can be driven stably and efficiently. In other words, it is possible to meet the appropriate specifications of the row data buffer without changing the structure of the bank core.

In addition, it is possible to reduce the operating time of the row data buffer by separating the row data buffer for each bank.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (14)

A bank including a phase change resistance cell formed in an area where bit lines and word lines intersect, storing data corresponding to a change in resistance by sensing a crystallization state that changes according to a magnitude of a current; A plurality of column switches connected to the bit lines and controlled by a plurality of column selection signals; A sense amplifier for sensing and amplifying data applied from the bank through the plurality of column switches; Bank selection means for selectively outputting data applied from said sense amplifier in accordance with a bank address; Column selecting means for selectively outputting data applied from the bank selecting means depending on whether the plurality of column selecting signals are activated; And And a row data buffer for buffering the data applied from the column selecting means. The phase change memory device as claimed in claim 1, wherein the sense amplifiers are shared by the plurality of column switches. The phase change memory device as claimed in claim 2, wherein when the sense amplifier is activated, only one of the plurality of column switches is activated. The phase change memory device of claim 1, wherein the row data buffer comprises a plurality of sub row data buffers. The phase change memory device as claimed in claim 4, wherein N bits of data are applied to each of the plurality of sub-row data buffers. The method of claim 5, wherein the column selecting means And when one column selection signal of the plurality of column selection signals is activated, a corresponding one of the plurality of sub row data buffers is selected. 6. The phase change memory device as claimed in claim 5, wherein the plurality of sub-row data buffers are provided in the same number as the plurality of column selection signals. 6. The phase change memory device as claimed in claim 5, wherein the page size of the row data buffer is set to m x N when the number of the sub row data buffers is m. 6. The phase change memory device as claimed in claim 5, wherein when the number of the sub row data buffers is m, m active operations are performed in accordance with sequential activation of the plurality of column selection signals. The phase change memory device as claimed in claim 4, wherein the plurality of sub-row data buffers are sequentially activated according to the plurality of column selection signals. 5. The phase change memory device as claimed in claim 4, wherein the page size of the sense amplifier is equal to the page size of one sub-loof data buffer. The phase change memory device as claimed in claim 1, wherein the column selecting means is provided in the same number as the bank. The phase change memory device as claimed in claim 1, wherein the bank selecting means comprises a multiplexer. The phase change memory device as claimed in claim 1, wherein the column selecting means comprises a multiplexer.

Images