KR20090014238A - Digital broadcasting system and data processing method - Google Patents

Abstract

A digital broadcasting system and a data processing method are provided to perform carrier sync recovery, frame sync recovery, and channel equalization by using base data information, thereby improving receiving ability. A signal receiving unit receives a broadcast signal in which at least one of M data groups includes K dummy bytes. A demodulator(302) demodulates the broadcast signal. A block decoder(305) decodes first data by block among the demodulated broadcast signals. A de-multiplexer outputs the block-decoded first data to a corresponding route among a plurality of routes. One or more RS(Reed Solomon) frame decoder corrects an error generated in the first data.

Description

Digital broadcasting system and data processing method

The present invention relates to a digital broadcasting system, and more particularly, to a data processing method for transmitting and receiving digital broadcasting.

The 8T-VSB (Vestigial Sideband) transmission system, which is adopted as a digital broadcasting standard in North America and Korea, is a system developed for transmission of MPEG video / audio data. However, with the rapid development of digital signal processing technology and the widespread use of the Internet, digital home appliances, computers, and the Internet are being integrated into one big framework. Therefore, in order to meet various needs of users, it is necessary to develop a system capable of transmitting various additional data in addition to video / audio data through a digital broadcasting channel.

Some users of supplementary data broadcasting are expected to use supplementary data broadcasting by using PC card or portable device with simple indoor antenna. In the room, signal strength is greatly reduced due to wall blocking and influence of nearby moving objects. Due to the effects of ghosts and noise caused by reflected waves, broadcast reception performance may decrease. However, unlike general video / audio data, the additional data transmission should have a lower error rate. In the case of video / audio data, errors that the human eye and ears cannot detect are not a problem, while in the case of additional data (eg program executables, stock information, etc.), a bit error may cause serious problems. It can cause problems. therefore There is a need to develop a system that is more resistant to ghosting and noise in the channel.

The transmission of additional data will usually be done in a time division manner over the same channel as the MPEG video / sound. Since the beginning of digital broadcasting, however, ATSC VSB digital broadcasting receivers that receive only MPEG video / audio have been widely used in the market. Therefore, additional data transmitted on the same channel as MPEG video / audio should not affect the existing ATSC VSB-only receivers that have been used in the market. Such a situation is defined as ATSC VSB compatible, and the additional data broadcasting system should be compatible with the ATSC VSB system. The additional data may also be referred to as enhanced data or E-VSB data.

In addition, in a poor channel environment, the reception performance of the conventional ATSC VSB receiving system may be degraded. Especially in the case of portable and mobile receivers, robustness against channel changes and noise is required.

Accordingly, an object of the present invention is to provide a new digital broadcasting system and data processing method suitable for additional data transmission and resistant to noise.

Another object of the present invention is to provide a digital broadcasting transmission / reception system and a data processing method for improving reception performance of a receiver by performing additional encoding on enhanced data.

In order to achieve the above object, a data processing method of a transmission system according to an embodiment of the present invention, the step of receiving enhanced data each having information through a plurality of paths; Collecting an enhanced data byte input for each path to form an RS frame, performing error correction encoding on the basis of the formed RS frame, and performing interleaving on the basis of a super frame composed of a plurality of RS frames; Receiving an interleaved RS frame through each path and multiplexing the RS frame in units of RS frames; And encoding the multiplexed and output enhanced data at a G / H (ie, G <H) code rate.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

The digital broadcasting system and the data processing method according to the present invention have an advantage of being resistant to errors and compatible with existing VSB receivers when transmitting additional data through a channel. In addition, there is an advantage that the additional data can be received without error even in a ghost and noisy channel than the conventional VSB system.

In addition, the present invention performs error correction encoding on the enhanced data, and interleaves and transmits the data in a super frame unit, thereby robustly coping with the fast channel change while giving robustness to the enhanced data.

In particular, the present invention can further increase the error correction capability of the received enhanced data by generating a credit map at the time of error correction decoding of the received data and performing error correction decoding with reference to the credit information of the credit map. .

The present invention is more effective when applied to portable and mobile receivers in which channel variation is severe and robustness to noise is required.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described. At this time, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, by which the technical spirit of the present invention and its core configuration and operation is not limited.

In addition, the terminology used in the present invention is a general term that is currently widely used as much as possible, but in certain cases, the term is arbitrarily selected by the applicant. In this case, since the meaning is described in detail in the description of the present invention, It is intended that the present invention be understood as the meaning of the term rather than the name.

In the present invention, the enhanced data may be data having information such as a program execution file, stock information, or the like, or may be video / audio data. Known data is data known in advance by an appointment of the transmitting / receiving side. In addition, the main data is data that can be received by the existing receiving system, and includes video / audio data.

According to the present invention, additional encoding is performed on the enhanced data to be transmitted, thereby providing robustness to the enhanced data and strongly responding to a rapidly changing channel environment.

In particular, the transmission system of the present invention receives a plurality of enhanced data having different service information and performs additional encoding independently, and the receiving system can receive and decode the received data.

1A and 1B illustrate embodiments of a transmission system for receiving various types of enhanced data and independently performing additional encoding according to the present invention.

First, referring to FIG. 1A, the transmission system includes an E-VSB preprocessor 100 and a packet multiplexer 121.

The E-VSB preprocessor 100 includes a randomizer and an RS frame coder as many types (or numbers) of enhanced data as desired to be encoded.

In this case, the arrangement order of the randomizer and the RS frame encoder may be changed by the system designer. For example, an RS frame encoder may be disposed at the rear end of the renderer, or a renderer may be disposed at the rear end of the RS frame encoder.

In an embodiment of the present invention, an RS frame encoder is disposed at the rear end of the renderer.

At this time, each of the enhanced data to be encoded independently is input to the corresponding optimizer through a different path. In this case, the enhanced data inputted to the corresponding renderer through different paths may be enhanced data having different kinds of services or enhanced data having the same type of service, but may be independently rendered by the corresponding renderer. After it is sized, it is encoded in units of RS frames. For example, the enhanced data including the stock information and the enhanced data including the weather information may be received through respective paths to independently perform randomizing and RS encoding.

In addition, an internal parameter of an RS frame encoder that performs RS encoding on the enhanced data that is rendered and input in each renderer may vary depending on the importance of the enhanced data.

In the present invention, the first to third enhanced data (Enhanced Data 1 to Enhanced Data 3) is input to the first to third randomizers 101a to 101c through respective paths, and the first to third randomizers ( An embodiment in which the first to third RS encoders 102a to 102c are disposed at the output terminals of 101a to 101c, respectively, will be described.

RS frame multiplexing at the output terminals of the first to third RS frame encoders 102a to 102c to multiplex and output the enhanced data encoded by the first to third RS frame encoders 102a to 102c in units of RS frames. Firearms 103 are provided.

At the output end of the RS frame multiplexer 103, a block processor 104, a group formatter 105, a data deinterleaver 106, and a packet formatter 107 are sequentially configured.

In the present invention configured as shown in FIG. 1A, the first to third enhanced data are input to the first to third randomizers 101a to 101c through respective paths, and are respectively randomized. That is, by performing the randomizing on the enhanced data in each of the randomizers 101a to 101c of the E-VSB preprocessor 100, the enhanced data is arranged in the rearmizer of the packet multiplexer 121. You can skip the rendering process for. The enhanced data, each of which is rendered by the first to third randomizers 101a to 101c, is input to the first to third RS frame encoders 102a to 102c, respectively.

The first to third RS frame encoders 102a to 102c form an RS frame by collecting a plurality of enhanced data bytes which are randomized and input, and then perform an error correction encoding process in units of RS frames. do. In this case, the error detection encoding process may or may not be performed. This gives robustness to the enhanced data so that it can cope with extremely poor and rapidly changing propagation environments.

Also, the first to third RS frame encoders 102a to 102c may collect a plurality of RS frames to form a super frame, and then perform interleaving or permutation on a super frame basis. In this way, clustering errors that may occur in the enhanced data due to changes in the propagation environment may be disturbed, thereby enabling a more adaptive response to an extremely poor and rapidly changing propagation environment.

3 and 4, an RS frame forming process of each RS frame encoder and an error correction encoding process performed in units of RS frames will be described in detail. 3 illustrates an example in which a checksum is added by performing error detection encoding after error correction encoding, and FIG. 4 illustrates an example in which an error detection encoding process is omitted.

According to an embodiment of the present invention, the error correction encoding applies RS encoding, and the error detection encoding applies CRC (Cyclic Redundancy Check) encoding. Parity data to be used for error correction is generated when the RS encoding is performed, and CRC data to be used for error detection is generated when CRC encoding is performed. The error detection encoding may use other error detection encoding methods instead of CRC encoding, or may improve the overall error correction capability at the receiving end by using an error correction encoding method.

3 and 4 describe in detail the operation of one RS frame encoder (eg, 102a) among a plurality of RS frame encoders. For other RS frame encoders (eg, 102b, 102c), only internal parameters may be different. Since the basic operation is the same as that of the RS frame encoder 102a, detailed description thereof will be omitted.

First, FIGS. 3A to 3E illustrate a process of encoding an RS frame encoder according to an embodiment of the present invention.

That is, the RS frame encoder 102a divides the enhanced data byte input in units of a predetermined length (A). The predetermined length A is a value determined by the system designer. In the present invention, 187 bytes is described as an embodiment, and for convenience of description, the 187 byte unit will be referred to as a packet.

For example, if the enhanced data input as shown in (a) of FIG. 3 is an MPEG transport stream (TS) packet configured in units of 188 bytes, the first MPEG sync byte is removed and 187 bytes as shown in (b) of FIG. Consists of one packet. The reason for removing the MPEG sync byte is that all enhanced packets have the same value. In this case, the MPEG sync byte removal may be performed at the time of rendering in the front-end imager 101a. In this case, the process of removing the MPEG sync byte from the RS frame encoder 102a is omitted, and when the MPEG sync byte is added in the receiving system, it is added by the derandizer instead of the RS frame decoder.

Therefore, if there is no fixed byte that can be removed from the input enhanced data or if the length of the input packet is not 187 bytes, the input enhanced data is divided by 187 bytes, and one divided by 187 bytes is used. Configure the packet.

Subsequently, as shown in (c) of FIG. 3, N packets of 187 bytes are collected to form one RS frame. In this case, the configuration of one RS frame is achieved by sequentially putting packets of 187 bytes into RS frames having a size of N (row) * 187 (column) bytes.

At this time, all N columns of the RS frame include 187 bytes as shown in FIG.

Therefore, in the present invention, ((187 + P), 187) -RS encoding is performed on each column to generate P bytes of parity, and after the last byte of the column, one column of (187 + P) bytes is added. You can make

When ((187 + P), 187) -RS coding is performed on all N columns of FIG. 3 (c) as shown in FIG. 3 (d), N (row) * (187 + P) (column ) You can create an RS frame with a size of bytes.

As shown in (c) or (d) of FIG. 3, each row of the RS frame includes N bytes. However, an error may be included in the RS frame according to the channel condition between the transmission and reception. When an error occurs like this, a checksum may be added to check for an error in each row unit. For example, the checksum may use CRC data (or also referred to as CRC code or CRC checksum).

The RS frame encoder 102a performs CRC encoding on the RS coded enhanced data to generate the checksum, for example, a CRC checksum. The CRC checksum generated by the CRC encoding may be used to indicate whether enhanced data is damaged by an error while being transmitted through a channel.

As described above, the present invention may use other error detection encoding methods other than CRC encoding, or may increase the overall error correction capability at the receiving end by using an error correction encoding method.

3 (e) shows an example of using a 2-byte (i.e. 16-bit) CRC checksum as CRC data, and after generating a 2-byte CRC checksum for N bytes of each row, an N-byte rear end is generated. It is adding. By doing this, each row is expanded to N + 2 bytes.

Equation 1 below shows an example of a polynomial that generates a 2-byte CRC checksum for each row of N bytes.

g (x) = x ¹⁶ + x ¹² + x ⁵ + 1

Since adding a 2-byte CRC checksum to each row is an embodiment, the present invention will not be limited to the example described above.

When both the RS coding and CRC coding processes described above are performed, the RS frame of 187 * N bytes is extended to an RS frame of (N + 2) * (187 + P) bytes.

4 illustrates another embodiment of an RS frame encoding process of the RS frame encoder 102a, in which an error detection encoding process is omitted.

In FIG. 4, the process of forming one packet by collecting A (eg, 187) enhanced data bytes is the same as that of FIG. 3.

In other words, if the enhanced data input as shown in FIG. Constitute a packet.

However, since the error detection encoding process is not performed in FIG. 4, as shown in FIG. 4C, N + 2 packets composed of 187 bytes are collected to form one RS frame. At this time, the configuration of one RS frame is achieved by sequentially inserting a packet of 187 bytes into an RS frame having a size of N + 2 (row) * 187 (column) bytes.

At this time, all N + 2 columns of the RS frame include 187 bytes as shown in FIG.

Therefore, in the present invention, ((187 + P), 187) -RS encoding is performed on each column to generate P bytes of parity, and after the last byte of the column, one column of (187 + P) bytes is added. You can make

When ((187 + P), 187) -RS coding is performed on all N columns of FIG. 4 (c) as shown in FIG. 4 (d), N + 2 (row) * (187 + P) You can create an RS frame with a size of (column) bytes.

That is, the size of the RS frame in which the error correction encoding and the error detection encoding are performed as shown in FIG. 3 and the size of the RS frame in which the error correction encoding is performed as shown in FIG. 4 are the same.

The P value may have the same value for each RS frame encoder 102a to 102c or may have a different value according to the type of enhanced data to be encoded. For example, it may be set to 48 in the first RS frame encoder 102a and to 36 in the second RS frame encoder 102b. If the P value is set to 48 in the first RS frame encoder 102a, (235, 187) -RS encoding is performed on each column to generate 48 parity bytes.

In the error correction scenario of one RS frame, bytes in the RS frame are transmitted on the channel in the row direction. At this time, if a large amount of error occurs in the limited transmission time, the error occurs in the row direction in the RS frame of the decoding process of the receiving system. However, in view of the RS code performed in the column direction, an error is distributed, and thus an effective error correction can be performed. In this case, although a parity byte (P) is increased as a method for more robust error correction, an appropriate compromise is required because it decreases the transmission efficiency. In addition, erasure decoding can be used to improve the error correction capability.

In addition, the RS frame encoder of the present invention performs interleaving in units of super frames in order to further improve error correction capability of the RS frame.

5 illustrates an embodiment of an interleaving process in units of super frames.

That is, G frames encoded as shown in FIG. 3 or 4 are collected as shown in FIG. 5 (a) to form a super frame. At this time, since each RS frame is composed of (N + 2) * (187 + P) bytes, one super frame is (N + 2) * (187 + P) * G bytes size.

When interleaving is performed by mixing each column of the super frame configured as described above with a predetermined rule, the positions of rows before and after interleaving in the super frame are changed. That is, as shown in (b) of FIG. 5, the i-th row of the super frame before interleaving is located in the j-th row of the same super frame as shown in (c) of FIG. 5 after interleaving is performed. This relationship between i and j can be known through an interleaving rule as shown in Equation 2 below.

Even after interleaving of the super frame unit is performed, each row of the super frame is composed of N + 2 bytes.

After all the interleaving of the super frame unit is performed, it is divided into G interleaved RS frames as shown in (d) of FIG. 5 again.

Note that the RS parity and the number of columns of each RS frame constituting one super frame must be the same.

Similar to the error correction scenario of the RS frame described above, in the case of a super frame, since a large amount of error occurs, the error frame is distributed throughout the super frame even though an error that cannot be corrected is included in one RS frame to be decoded. The decoding capability is improved compared to the RS frame.

In this way, the enhanced data in which the RS frame encoders 102a to 102c are encoded in the RS frame unit and interleaved in the super frame unit is output to the RS frame multiplexer 103. The RS frame multiplexer 103 multiplexes the enhanced data output from the first to third RS frame encoders 102a to 102c in units of RS frames and outputs the multiplexed data to the E-VSB block processor 104.

The E-VSB block processor 104 encodes the enhanced data on which encoding and interleaving are performed at a G / H code rate and outputs the encoded data to the group formatter 105.

That is, the E-VSB block processing unit 104 divides the enhanced data input in byte units into bits, encodes the divided G bits into H bits, and converts them into byte units and outputs them. For example, if one bit of input data is encoded into two bits and outputted, G = 1 and H = 2. If one bit of input data is encoded into four bits and outputted, G = 1 and H = 4. In the present invention, for convenience of description, the former is referred to as encoding at 1/2 code rate (or sometimes referred to as 1/2 encoding), and the latter is referred to as encoding at 1/4 code rate (or referred to as 1/4 encoding). do.

This is because when the 1/4 encoding is used, it has a higher error correction capability due to the higher code rate than the 1/2 encoding. For this reason, the data encoded at the 1/4 code rate in the later group formatter 105 may be allocated to an area where reception performance may be deteriorated, and the data encoded at the 1/2 code rate may have better performance. Assuming allocation to a region, the effect of reducing the difference in performance can be obtained.

In this case, the E-VSB block processing unit 104 may also receive additional information data such as signaling including information of the system. The additional information data may also be received in the same manner as the enhanced data processing process. Perform two coding or quarter coding. Thereafter, additional information data such as signaling is also regarded as enhanced data and processed.

The additional information data such as the signaling may be input to the E-VSB block processor 104 via a randomizer and an RS frame encoder, or may be directly input to the E-VSB block processor 104 without passing through the randomizer and an RS frame encoder. It can also be entered. The signaling information is information necessary for receiving and processing data included in the data group in a receiving system, and may include data group information, multiplexing information, burst information, and the like. The signaling information will be described later.

Meanwhile, the group formatter 105 may include enhanced data (which may include additional data such as signaling data including transmission information) output from the E-VSB block processor 104 according to a predefined rule. It inserts into the corresponding area in the data group to be formed, and also inserts various position holders or known data into the corresponding area in the data group in relation to data deinterleaving.

In this case, the data group may be divided into at least one layered area, and a data type allocated to each area may vary according to characteristics of each layered area. In addition, one data group is configured to include field synchronization.

FIG. 6A illustrates a form in which data before data deinterleaving is listed separately, and FIG. 6B illustrates a form in which data after data deinterleaving is separately classified. That is, FIG. 6A is a form of data after data interleaving, and FIG. 6B is a form of data before data interleaving.

FIG. 6A illustrates an embodiment in which one data group is divided into three regions in a data configuration before data deinterleaving. For convenience of description, each region is referred to as a first, second, and third region. Let's do it. The first to third regions are classified based on regions having similar reception performance in the data group. In this case, the type of enhanced data inserted may vary according to characteristics of each region.

In the present invention, dividing the first to third areas based on the degree of interference of the main data will be described as an embodiment.

Here, the reason why the data group is divided into a plurality of areas is used for different purposes. That is, an area where there is no or little interference of main data may exhibit stronger reception performance than an area that is not. In addition, when applying a system for inserting and transmitting known data into a data group, an area where there is no interference of main data when the long known data is to be inserted periodically in the enhanced data (for example, the first area) It is possible to periodically insert known data of a certain length into the. However, it is difficult to periodically insert known data into the region where the main data interferes (for example, the second and third regions) due to the interference of the main data, and also to insert long known data continuously.

In the present invention, the size of the data group, the number of layered areas in the data group, the size of each area, the number of enhanced bytes that can be inserted into each layered area, and the like are one embodiment for describing the present invention.

In this case, the group formatter 105 forms a data group including a position at which field synchronization is to be inserted, thereby forming a data group as described below.

That is, the first area 211 includes an area in which a long known data sequence in the data group can be periodically inserted, and an area in which main data is not mixed. The first area 211 also includes an area between the field sync area to be inserted into the data group and the area to which the first known data string is inserted. The field sync area has one segment length (ie, 832 symbols) present in ATSC.

In the case of the first region 211 having known data streams back and forth as described above, the receiving system can perform equalization using channel data obtained from known data or field synchronization, and thus robust equalization performance can be obtained.

The second area 212 is an area located within the first eight segments of the field synchronization area in the data group (temporally located in front of the first area 211) and the last known data row inserted into the data group. An area located in the next eight segments (temporally located behind the first area 211). In the case of the second area 212, the receiving system may perform equalization using channel information obtained in the field synchronization period, and may also perform equalization using channel information obtained from the last known data stream. Therefore, the channel can be changed.

The third region 213 is an area (in front of the first region 211 temporally) located within 30 segments in front of it, including the 9th segment in front of the field sync region, and the last known in the data group. An area located in the 44th segment including the 9th segment after the data column (it is located behind the first area 211 in time).

In this case, since the third region 213 located in time ahead of the first region 211 is far from the field synchronization, which is the closest known data, the receiving system may use channel information obtained from the field synchronization when channel equalization is performed. Alternatively, the most recent channel information of the previous data group may be used. The third region 213 located later in time than the first region 211 is equalized when the channel changes rapidly even if the receiving system performs equalization using the channel information obtained from the last known data stream at the time of channel equalization. It may not be perfect. Therefore, the third region 213 may have lower equalization performance than the second region 212.

Assuming that a data group is allocated to a plurality of layered regions as described above, the above-described E-VSB block processor 104 may encode enhanced data to be inserted into each region at different code rates according to the characteristics of the layered region. It may be.

Since the amount of enhanced data actually transmitted varies according to the code rate of the enhanced data to be inserted into each region, the present invention will be described as one example of dividing it into a code mode.

Table 1 below is an embodiment in which the number of enhanced data bytes that can be actually transmitted in each of the areas 211 to 213 is summarized. The enhanced data byte that can be actually transmitted means enhanced data before the E-VSB block processor 104 is encoded at a G / H code rate. In addition, in Table 1 below, the number of bytes separately allocated for transmitting signaling information in a corresponding region is indicated. In addition, trellis initialization, known data, MPEG header, RS parity, etc. are excluded from the enhanced data.

A detailed description of the number of bytes presented in Table 1 will be described later.

Table 2 below is an embodiment of code modes for encoding and transmitting enhanced data according to the code rate combination. By dividing each area in this way, it is possible to transmit a plurality of service data as independent enhanced data.

Table 3 below is an embodiment showing combination modes combining respective regions and the number of services that can be independently transmitted in the combination mode.

Combination mode   Combination  Number of available channels      One First area, second area, third area         3      2 1st area + 2nd area, 3rd area         2      3 1st area + 3rd area, 2nd area         2      4 2nd area + 3rd area, 1st area         2      5 1st area + 2nd area + 3rd area         One

Table 3 shows an example of the number of combination modes that can be combined when one data group is divided into first to third areas. The enhanced data that can be allocated to each area according to the code mode to which the combination mode is applied is shown in Table 3. The amount will vary. Here, the number of modes that can be combined may vary depending on the number of areas that divide the data groups.

That is, when the combination mode is 1 in Table 3, the code set for each enhanced data after receiving the first to third enhanced data having different types of services and performing the above-described randomization and RS encoding is performed. It indicates that the rate can be encoded and allocated to each area for transmission. In this case, since the enhanced data types allocated to the respective regions are different from each other, the E-VSB block processor 104 may perform encoding on the enhanced data to be inserted in each region at an independent code rate.

In Table 3, when the combined mode is 2, the enhanced data to be inserted into the first and second regions after the above-described randomization and RS encoding are received by receiving the first and second enhanced data having different services. Enhanced data to be inserted into the third region at the first code rate indicates that the data can be allocated to each region and then transmitted after encoding at the second code rate. The first and second code rates may be the same as or different from each other. In the present invention, one of the 1/2 code rate and the 1/4 code rate will be described as an embodiment.

Table 4 below shows a combination mode 2, that is, a data group is divided into a first + second area and a third area, and the number of bytes that can be inserted into each area according to each code rate is as shown in Table 1 above. Shows the number of enhanced data bytes that can be inserted into the area.

For example, if the combination mode 2 and the code mode 1 are set, the number of enhanced data bytes that can be inserted into the first region and the second region is 7620 bytes, respectively, encoded at a 1/2 code rate, and the third region is 2074. Byte and similarly encoded at a 1/2 code rate.

In addition, if the combination mode 4 and the code mode 3 are set, the number of enhanced data bytes that can be inserted into the first area + the second area is 7050 bytes, the first area is 1/2 code rate, and the second area is 1/4 code. Encoded by the rate. The number of enhanced data bytes that can be inserted into the third area is 2074 bytes, and encoded at 1/2 code rate.

Meanwhile, in the group formatter 105, in addition to the encoded enhanced data output from the E-VSB block processing unit 104, as shown in FIG. 6A, an MPEG header position holder and an unstructured RS parity position are related to data deinterleaving at a later stage. Insert the holder and the main data position holder. The reason for inserting the main data position holder is that there is an area where the enhanced data and the main data are mixed based on the input of the data deinterleaver as shown in FIG. 6A. As an example, the position holder for the MPEG header is assigned to the front of each packet based on the output data after the data deinterleaving.

The group formatter 105 also inserts known data generated by a predetermined method or inserts known data position holders for inserting known data later. In addition, a position holder for initializing the Trellis encoding module (see FIG. 2) is inserted into the corresponding region. In one embodiment, the initialization data location holder may be inserted before the known data stream.

The output of the group formatter 105 is input to the data interleaver 106, and the data deinterleaver 106 decodes the data and position holders in the data group output from the group formatter 105 in a reverse process of data interleaving. Interleaving is output to the packet formatter 107. That is, when the data and position holder in the data group configured as shown in FIG. 6A are deinterleaved by the data deinterleaver 106, the data group output to the packet formatter 107 has a structure as shown in FIG. 6B.

The packet formatter 107 removes the main data position holder and the RS parity position holder which have been allocated for deinterleaving among the deinterleaved input data, collects the remaining portions, and then stores the MPEG header in the 4-byte MPEG header position holder. Insert it.

Also, the packet formatter 107 may insert actual known data into the known data position holder when the group formatter 105 inserts the known data position holder, or later inserts the known data position holder for replacement insertion. You can output as is without adjustment.

Thereafter, the packet formatter 107 divides the data in the packet-formatted data group into 188-byte enhanced data packets (ie, MPEG TS packets) and provides them to the packet multiplexer 121.

Up to now, the preprocessing process of the enhanced data has been described with reference to the E-VSB preprocessor 100 configured as shown in FIG. 1A.

FIG. 1B illustrates another embodiment of the E-VSB preprocessor according to the present invention, in which the RS frame encoder is included as many as (or the number) of enhanced data desired to be encoded independently. The difference is that a randomizer that renders the enhanced data is placed at the output of the RS frame multiplexer for rendering regardless of the type of enhanced data being input.

That is, the E-VSB preprocessor 111 of FIG. 1B includes the first to third RS frame encoders 111a to 111c, the RS frame multiplexer 112, the randomizer 113, the block processor 114, and the group formatter. 115, the data deinterleaver 116, and the packet formatter 117 are sequentially arranged.

In the present invention configured as shown in FIG. 1B, the first to third enhanced data are input to the first to third RS frame encoders 111a to 111c through respective paths.

The first to third RS frame encoders 111a to 111c form an RS frame by collecting a plurality of received enhanced data bytes and perform an error correction encoding process in units of RS frames. In this case, the error detection encoding process may or may not be performed. This provides robustness to the enhanced data so that it can cope with extremely poor and rapidly changing propagation environments.

In addition, the first to third RS frame encoders 111a to 111c collect a plurality of RS frames to form a super frame and perform interleaving or permutation on a super frame basis. In this way, clustering errors that may occur in the enhanced data due to changes in the propagation environment may be disturbed, thereby enabling a more adaptive response to an extremely poor and rapidly changing propagation environment.

Detailed descriptions of the first to third RS frame encoders 111a to 111c may be referred to with reference to FIGS. 1A, 3, and 4 as described above, and thus the description thereof will be omitted.

In the first to third RS frame encoders 111a to 111c, the enhanced data, in which RS-frame encoding and super-frame interleaving is performed, is output to the RS frame multiplexer 112. The RS frame multiplexer 112 multiplexes the enhanced data output from the first to third RS frame encoders 111a to 111c in RS frame units and outputs the multiplexed data to the randomizer 113.

The randomizer 113 performs randomization on the enhanced data output from the RS frame multiplexer 112 and outputs the same to the E-VSB block processor 114.

Detailed operations of the blocks arranged after the renderer 113, that is, the E-VSB block processor 114, the group formatter 115, the data deinterleaver 116, and the packet formatter 117 are described with reference to FIG. 1A. Since the detailed operation of the E-VSB preprocessor 100 may be referred to, the description thereof will be omitted.

FIG. 2 shows an embodiment of an overall block diagram of a transmission system including an E-VSB preprocessor as shown in FIG. 1A or 1B.

The transmission system of FIG. 2 includes an E-VSB preprocessor 100 or 110, a packet multiplexer 121, a data randomizer 122, an RS encoder / Non-systematic RS encoder (123). ), A data interleaver 124, a parity substituent 125, an unstructured RS encoder 126, a trellis encoder 127, a frame multiplexer 128, and a transmitter 130.

The enhanced data packet preprocessed by the E-VSB preprocessor 100 or 110 is input to the packet multiplexer 121.

The packet multiplexer 121 multiplexes the enhanced data packet and the main data packet in units of 188 bytes output from the E-VSB preprocessor 100 or 110 according to a predefined multiplexing method. The multiplexing method can be adjusted by various variables of the system design.

As one of the multiplexing methods of the packet multiplexer 121, the enhanced data burst section and the main data section may be divided on the time axis, and the two sections may be alternately repeated. In this case, at least one data group may be transmitted in the enhanced data burst section and only main data may be transmitted in the main data section. The main data may be transmitted in the enhanced data burst period.

As described above, when the enhanced data is transmitted in a burst structure, the receiving system receiving only the enhanced data turns on the power only in the burst period to receive the data, and turns off the power in the main data section in which only the main data is transmitted. By not receiving, the power consumption of the receiving system can be reduced.

If the input data is a main data packet, the data randomizer 122 performs rendering in the same manner as the existing one. That is, the MPEG sync byte in the main data packet is discarded, and the remaining 187 bytes are randomly generated using pseudo random bytes generated therein, and then output to the RS encoder / unstructured RS encoder 123.

However, if the input data is an enhanced data packet, the MPEG sync byte is discarded among the 4 byte MPEG headers included in the enhanced data packet, and only the remaining 3 bytes are rendered, and the rest of the enhanced data except the MPEG header is performed. The RS is output to the RS encoder / unstructured RS encoder 123 without performing any rendering. This is because the randomizer of the E-VSB preprocessor 100 or 110 has previously performed rendering on the enhanced data. Rendering may or may not be performed on the known data (or known data location holder) and the initialization data location holder included in the enhanced data packet.

The RS encoder / unstructured RS encoder 123 performs RS encoding on data to be rendered or bypassed by the data randomizer 122 to add 20 bytes of RS parity, and then the data interleaver 124. Will output In this case, the RS encoder / unstructured RS encoder 123 performs systematic RS encoding like the existing ATSC VSB system when the input data is a main data packet, and adds 20 bytes of RS parity to 187 bytes of data. In the case of an enhanced data packet, a 20-byte RS parity obtained by performing unsystematic RS encoding is inserted at a parity byte position determined in the packet.

The data interleaver 124 is a convolutional interleaver in bytes.

The output of the data interleaver 124 is input to the parity substituent 125 and the unstructured RS encoder 126.

On the other hand, in order to make the output data of the trellis encoder 127 located at the rear end of the parity substituent 125 into known data defined by appointment on the transmitting / receiving side, the memory in the trellis encoder 127 is first initialized. Is needed. That is, before the input known data string is trellis encoded, the memory of the trellis encoder 127 must be initialized.

At this time, the starting part of the known data stream is not the actual known data but the initialization data position holder inserted by the group formatter of the E-VSB preprocessor 100 or 110. Therefore, a process of generating initialization data immediately before the input known data string is trellis encoded and replacing the corresponding trellis memory initialization data position holder is required.

The trellis memory initialization data is generated by determining a value thereof according to the memory state of the trellis encoder 127. In addition, a process of recalculating RS parity under the influence of the replaced initialization data and replacing the RS parity with the RS parity output from the data interleaver 124 is required.

Accordingly, the unstructured RS encoder 126 receives an enhanced data packet including an initialization data position holder to be replaced with initialization data from the data interleaver 124 and inputs initialization data from the trellis encoder 127. Receive. Subsequently, the initialization data position holder of the input enhanced data packet is replaced with the initialization data, the RS parity data added to the enhanced data packet is removed, and a new unsystematic RS parity is calculated and output to the parity substituent 125. The parity substituent 125 then selects the output of the data interleaver 124 for the data in the enhanced data packet, and the trellis encoder 127 for the RS parity by selecting the output of the unstructured RS encoder 126. Will output

Meanwhile, when the main data packet is input or an enhanced data packet including an initialization data position holder to be replaced is input, the parity substituent 125 selects data and RS parity output from the data interleaver 124 and transmits the same. Output to release release unit 127.

The trellis encoder 127 converts the data of the byte unit into the symbol unit, performs 12-way interleaving, trellis-encodes, and outputs the trellis to the frame multiplexer 128.

The frame multiplexer 128 inserts field synchronization and segment synchronization into the output of the trellis encoder 127 and outputs them to the transmitter 130.

The transmitter 130 includes a pilot inserter 131, a VSB modulator 132, and an RF up-converter 133, and thus the detailed description thereof will be omitted.

detailed Example

Next, specific embodiments of the E-VSB preprocessor 100 or 110 and the packet multiplexer 121 will be described.

In an embodiment of the present invention, an N value, which is the length of one row of the RS frame configured in the RS frame encoder, is set to 538.

Then, the RS frame encoder receives 538 transport stream (TS) packets when applying FIG. 3 to form an RS frame having a size of 538 * 187 bytes, and applies 540 transport streams (TS) when applying FIG. 4. It receives the packet and constructs an RS frame of 540 * 187 bytes.

That is, in the case of FIG. 3, an RS frame having a size of 538 * 235 bytes is formed through an (235,187) -RS encoding on an RS frame having a size of 538 * 187 bytes, and then a 540 * 235 process through generating a 16-bit CRC checksum. It will expand to RS frames of byte size. In addition, in FIG. 4, an RS frame having a size of 540 * 187 bytes is extended to an RS frame having a size of 540 * 235 bytes through (235,187) -RS encoding.

Meanwhile, suppose that in Tables 2 and 3, enhanced data is encoded, grouped, and transmitted in code mode 3 and combination mode 2. Referring to Table 2, in the code mode 3, the first and third regions are encoded at 1/2 code rate, and the second region is encoded at 1/4 code rate. In addition, in Table 3, in the combined mode 2, the enhanced data inserted into the first + second areas by dividing the data group into the first + second areas and the third area is the same kind of service, and the third area. The enhanced data inserted into the service is a different kind of service from the enhanced data inserted into the first + second areas. This is an embodiment, and the setting of the sign mode and the combination mode may be different by the designer, and thus the present invention will not be limited to the examples described above.

In the above-described embodiment, referring to Tables 1 to 4, the number of transmitted bytes in the first + second regions is 7050, and the third region is 2074 bytes.

In this case, suppose that one super frame is composed of two RS frames, and 18 data groups are configured to form one RS frame. Assuming that the enhanced data of the two RS frames constituting the super frame is inserted into the first + second regions in each data group, the super frame is composed of 253800 bytes and the RS frame is composed of 126900 bytes. In this case, if RS parity (P) is set to 48 and the CRC checksum is set to 2 bytes per row, 1076 enhanced data packets of 188 bytes can be transmitted in one super frame. This means that 538 enhanced data packets can be transmitted per RS frame.

Similarly, the number of transmitted bytes in the third area is 2074. In this case, assuming that 18 data groups are collected to form one RS frame, and the enhanced data of the RS frame is inserted into a third region, the RS frame is composed of 37332 bytes. In this case, if the RS parity (P) is set to 36 and the CRC checksum is allocated to 2 bytes for each row, 165 enhanced data packets can be transmitted in one RS frame. In this case, when a super frame is composed of two RS frames, it means that 330 enhanced data packets of 188 bytes can be transmitted per super frame.

In this case, 91 bytes remain in each RS frame in the third region of the data group. If the byte remains as described above may occur while dividing the RS frame into a plurality of data groups of the same size. That is, the size of the RS frame, the size and number of data groups to be divided, the number of enhanced data bytes that can be inserted into each data group, the code rate of the corresponding area, the number of bytes of RS parity, whether CRC checksums are allocated, and Depending on the number of bytes of the CRC checksum, the remaining bytes may occur in a specific area per RS frame.

When a single RS frame is divided into a plurality of data groups having the same size as described above, when bytes remaining in the RS frame are generated, a plurality of dummy bytes are added after the number of bytes (K) remaining in the RS frame. Separate into three data groups.

This process is illustrated in FIG. 7.

FIG. 7 illustrates an embodiment of a process in which K bytes remain when an RS frame having a size of (N + 2) * (187 + P) is divided into M data groups having the same size.

In this case, K dummy bytes are added to an RS frame of size (N + 2) * (187 + P) as shown in FIG. 7A, and are read in rows and M as shown in FIG. Separate into three data groups. Each data group has a NoBytesPerGrp byte size.

This is represented by the following equation (3).

M * NoBytesPerGrp = (N + 2) * (187 + P) * K

Here, NoBytesPerGrp is the number of bytes allocated to one data group (NoBytesPerGrp means the Number of Bytes per a Group).

That is, the size of bytes + K bytes of one RS frame is the same as that of M data groups.

1A and 1B may receive 1076 packets through the first enhanced data path and 330 packets through the second enhanced data path.

Referring to FIG. 1A, 1076 packets inputted as a path through the first enhanced data and 330 packets inputted through the second enhanced data path are respectively rendered by the first and second renderers 101a and 101b. Mizing is performed in the first and second RS frame encoders 102a and 102b to perform RS frame-based encoding and superframe-based interleaving, respectively. It is input to the VSB block processing unit 104.

According to an embodiment of the present invention, the first RS frame encoder 102a adds 48 parity bytes in the column direction and a CRC checksum of 2 bytes in the row direction for the corresponding RS frame. In the second RS frame encoder 102b, 36 parity bytes are added for the corresponding RS frame, and a CRC checksum of 2 bytes is added in the row direction.

The E-VSB block processor 104 receives the encoded and interleaved enhanced data divided into byte units allocated to one data group.

In this case, as described above, 91 bytes remain in each RS frame in the data group. Therefore, when all data of the RS frame to be allocated to the third area is input, 91 bytes of dummy bytes are added. The addition of the dummy byte may be performed by the E-VSB block processor 104 or may be input from an external block (not shown).

The E-VSB block processing unit 104 encodes each byte at a code rate of 1/2 or 1/4 according to an area to be disposed on the data group and outputs the byte to the group formatter 105. For example, the first enhanced data to be inserted into the first region is encoded at 1/2 code rate, and the first enhanced data to be inserted into the second region is encoded at 1/4 code rate and inserted into the third region. The second enhanced data to be encoded is encoded at a 1/2 code rate.

In the group formatter 105, encoded and input enhanced data and other data (e.g., MPEG header position holder, unstructured RS parity position holder, main data position holder, known data or known data position holder, initialization data) Position holders, etc.) are inserted (or placed) in the corresponding areas in the data group of FIG. 6A. That is, the first enhanced data encoded at the 1/2 code rate and the first enhanced data encoded at the 1/4 code rate are inserted into the first + second region, and the second encoded code at the 1/2 code rate. The enhanced data is inserted into the third area.

The data in the data group configured as in FIG. 6A are deinterleaved in the data deinterleaver 106 and converted as shown in FIG. 6B and converted into 187 bytes of enhanced data packets (compatible with existing VSB packets) in the packet formatter 107. After that is output to the packet multiplexer 121.

The packet multiplexer 121 multiplexes the packet including the enhanced data and the packet including the main data in burst units and outputs the packet to the randomizer 122.

8 illustrates an example of an operation of the packet multiplexer 121 according to a specific embodiment of the present invention, and illustrates an embodiment in which burst transmission is performed.

That is, one burst period (or BP interval) in the packet multiplexer 121 is composed of BP fields. In other words, the BP interval includes the number of fields from the start of the current burst to the start of the next burst.

The BP interval is composed of BS fields and BP-BS fields. The section consisting of the BS fields (or BS section) includes fields in which an enhanced data group and main data are mixed, and the section consisting of the BP-BS fields (or BP-BS section). Contains fields that contain only main data.

Each field of the BS section is composed of one field sync segment and 312 data segments, and one data group and main data are multiplexed into 312 data segments. In the case of FIG. 8, data in the data group is allocated to 118 segments and main data is allocated to 195 segments in the BS section to form an field.

In FIG. 8, each field in the BS section has a data group index, and GI indicates the order (or order) of the data group currently transmitted in one burst section. The TNB section includes the number of fields from the current data group GI to the next burst start position in one burst section. The TNB value is updated according to the index GI of the currently transmitted data group.

Here, the number of fields included in the TNB interval may be obtained by knowing the number of fields included in the BP interval and the index GI of the current data group.

The on time of the next burst may be predicted by BP-GI or predicted by a TNB value.

In the example described above, since one RS frame is transmitted divided into 18 data groups, in FIG. 8, the BS interval is composed of 18 fields, and one super frame is divided into 36 data groups, that is, two bursts. Is being sent.

By doing so, the receiving system can turn on the power only in the corresponding burst section including the desired data service to receive the corresponding data, and turn off the power in the remaining sections, thereby reducing power consumption of the receiving system. In addition, even if the receiving system receives power for 18 fields including a data group and turns off the receiver during the (BP-18) field, saving power consumption is no problem for broadcast reception.

In the receiving system, since one RS frame can be configured from 18 data groups received in one burst period, decoding is easy.

Signaling  Information

As described above, in order for the receiver to correctly process the enhanced data, the receiver needs to know exactly the transmission parameters used in the transmission system.

In the E-VSB preprocessor described above, examples of such mandatory parameters include the number of RS frames constituting a super frame (Super frame size (SFS)), the number of RS parities (P) per column in the RS frame, and the RS frame. Use of checksum added to determine whether there is an error in the row direction, if used, its type and size (currently 2 bytes added as CRC), and the number of data groups constituting one RS frame. The number of data groups in one burst is equal to the number of burst groups (BS) since they are transmitted in bursts of two bursts-and the modes shown in Tables 2 and 3 are the parameters required for burst reception (Burst Period: BP)- One burst period is a count of the number of fields from the start of one burst to the start of the next burst-and the RS frame currently being transmitted differs within one superframe. There is a permuted frame index (PFI) or a group index (GI) currently being transmitted in one RS frame (burst). According to the burst operation method, the number of fields remaining until the start of the next burst (TNB) may be transmitted as a parameter to inform the receiver of the relative distance (number of fields) to the start of the next burst for each data group transmitted. .

In the embodiment of the present invention, a method of transmitting a parameter is to collect a parameter and make a block code of a small size using a Kerdock code, a BCH or RS code, etc., and transmit the result in a byte (see Table 1) allocated for signaling in a group. . However, in this case, since the parameter value is obtained through the E-VSB block decoder in terms of reception, the mode parameters of Table 2 and Table 3, which are required for block decoding, must be obtained first. For this reason, the mode parameter uses a symbol correlation for fast decoding in inserting the parameter into some unused section of the known data. In other words, one of eight orthogonal sequences (e.g., the eight modes shown in Table 2) is inserted in this section for each data group according to the current mode. The receiving system determines the sign mode and the combination mode by looking at the correlation between the sequences and the currently received sequence.

For example, the transmission parameter may allocate and insert a predetermined area of an enhanced data packet or group. In this case, the transmission parameter is treated the same as the enhanced data. Alternatively, the transmission parameter may be inserted by multiplexing with other data. For example, when multiplexing the known data with the enhanced data, the transmission parameter may be inserted instead of the known data at a position where the known data may be inserted, or may be mixed with the known data. Alternatively, the transmission parameter may be allocated by inserting a part of the unused area in the field sync segment of the VSB frame. On the other hand, when the transmission parameter is inserted into the field sync segment area or the known data area and is transmitted, since the reliability is lowered when the transmission parameter passes through the transmission channel, one of the predefined patterns is inserted according to the transmission parameter. It is also possible. In this case, the reception system may recognize a transmission parameter by performing a correlation operation between the received signal and predefined patterns.

Receiving system

9 is a block diagram showing an embodiment of a digital broadcast receiving system according to the present invention. In the digital broadcasting reception system of FIG. 9, reception performance may be improved by performing carrier synchronization recovery, frame synchronization recovery, and channel equalization using known data information inserted and transmitted in an enhanced data interval in a transmission system.

Digital broadcast reception system according to the present invention for this purpose is tuner 301, demodulator 302, equalizer 303, known data detector 304, E-VSB block decoder 305, E-VSB data processor ( 306, and a main data processing unit 307.

The main data processor 307 includes a data deinterleaver 308, an RS decoder 309, and a data derandomizer 310.

The E-VSB data processor 306 may have various structures according to the configuration of the E-VSB preprocessor of the transmission system.

10A and 10B illustrate embodiments of a detailed block diagram of the E-VSB data processor 306.

10A is effective when the E-VSB preprocessor of the transmission system is configured as shown in FIG. 1A, and FIG. 10B is effective when the E-VSB preprocessor of the transmission system is configured as in FIG. 1B.

That is, the tuner 301 tunes the frequency of a specific channel, down-converts the intermediate frequency (IF) signal, and outputs the demodulator 302 and the known data detector 304.

The demodulator 302 performs automatic gain control, carrier recovery, and timing recovery on the input IF signal to form a baseband signal and outputs the same to the equalizer 303 and the known data detector 304.

The equalizer 303 compensates for the distortion on the channel included in the demodulated signal and outputs it to the E-VSB block decoder 305.

At this time, the known data detector 304 detects the position of the known data inserted by the transmitter from the input / output data of the demodulator 302, that is, the data before the demodulation is performed or the data after the demodulation is performed. The symbol sequence of the known data generated at the position is output to the demodulator 302 and the equalizer 303. In addition, the E-VSB determines whether the known data detection unit 304 can distinguish the enhanced data that has been further encoded and the main data that has not been further encoded by the E-VSB block decoder 305 at the transmitting side. Output to the block decoder 305. Although the connection state is not illustrated in the drawing of FIG. 9, the information detected by the known data detector 304 may be generally used in the reception system, and may be used by the E-VSB data processor 306.

The demodulator 302 can improve demodulation performance by using the known data symbol string during timing recovery or carrier recovery. The equalizer 303 can also use the known data to improve equalization performance. have. In addition, the equalization performance may be improved by feeding back the decoding result of the E-VSB block decoder 305 to the equalizer 303.

The equalizer 303 may perform channel equalization in various ways. In the present invention, channel equalization is performed by estimating a channel impulse response (CIR).

In particular, the present invention describes that the estimation and application of the channel impulse response (CIR) are different according to each region in the data group layered and transmitted in the transmission system. In addition, the present invention provides a more stable channel equalization by estimating the CIR using known data and field synchronization, which are known in terms of location and content, by appointment of the transmitting and receiving party.

At this time, one data group input for equalization is hierarchized into first to third regions as shown in FIG. 6A.

According to the present invention, channel equalization is performed on data in a data group using the field synchronization and the CIR estimated from the known data stream. In this case, one of the estimated CIRs may be used as it is according to the characteristics of each region of the data group. In addition, CIR generated by interpolating or extrapolating at least a plurality of CIRs may be used.

Where interpolation is a function value at some point between A and B when a function value F (A) at point A and a function value F (B) at point B are known for a function F (x) It is meant to estimate, and the simplest example of the interpolation is linear interpolation. The linear interpolation technique is the simplest of many interpolation techniques, and various other interpolation techniques may be used in addition to the above-described methods, and thus the present invention will not be limited to the examples described above.

Also, extrapolation can be used to determine the function value F (A) at time A and the function value F (B) at time B for a function F (x). It means to estimate the function value at the time point. The simplest example of such extrapolation is linear extrapolation. The linear extrapolation technique is the simplest of many extrapolation techniques, and various other extrapolation techniques may be used in addition to the above-described methods, and thus the present invention will not be limited to the examples described above.

On the other hand, if the data inputted to the E-VSB block decoder 305 after channel equalization in the equalizer 303 is enhanced data in which both additional encoding and trellis encoding are performed at the transmitting side, the reverse side of the transmitting side is trellis. If the data decoding and additional decoding are performed, and additional encoding is not performed and only trellis encoding is performed, only trellis decoding is performed. The data group decoded by the E-VSB block decoder 305 is input to the E-VSB data processor 306, and the main data packet is input to the data deinterleaver 308 of the main data processor 307.

If the input data is main data, the E-VSB block decoder 305 may perform Viterbi decoding on the input data to output a hard decision value, or hard decision the soft decision value and output the result.

If the input data is enhanced data, the E-VSB block decoder 305 outputs a hard decision value or a soft decision value with respect to the input enhanced data.

That is, if the input data is enhanced data, the E-VSB block decoder 305 decodes the data encoded by the E-VSB block processor and the trellis encoder of the transmission system. At this time, the RS frame encoder of the E-VSB preprocessor of the transmitting side becomes an external code, and the E-VSB block processor and the trellis encoder can be regarded as one internal code.

In order to maximize the performance of the outer code at the time of decoding the concatenated code, the soft decision value should be output from the decoder of the inner code.

Accordingly, the E-VSB block decoder 305 may output a hard decision value for the enhanced data, but it may be better to output a soft decision value if necessary.

Meanwhile, the data deinterleaver 308, the RS decoder 309, and the derandomizer 310 in the main data processing unit 307 are blocks necessary for receiving main data, and are a receiving system for receiving only enhanced data. It may not be necessary in the structure.

The data deinterleaver 308 deinterleaves the main data output from the E-VSB block decoder 305 in the reverse process of the data interleaver on the transmitting side and outputs the main data to the RS decoder 309.

The RS decoder 309 performs systematic RS decoding on the deinterleaved data and outputs it to the derandomizer 310.

The derandomizer 310 receives the output of the RS decoder 309 to generate the same pseudo random byte as the transmitter's renderer, bitwise XORs the MPEG sync byte, Insert it before and output in 188 byte main data packet unit.

Next, the E-VSB data processor 306 will be described in detail with reference to FIGS. 10A and 10B.

The E-VSB data processor of FIG. 10A includes an E-VSB data deformatter 411, an RS frame demultiplexer 412, a plurality of RS frame decoders 413a to 413c, and a plurality of E-VSB de-randomizers 414a. 414c). The number of RS frame decoders and the number of E-VSB de-randomizers of FIG. 10A is one embodiment, and may vary according to the configuration of a transmission system, the type of serviceable enhanced data, importance, and the like. It will not be limited to.

Referring to FIG. 10A configured as described above, the data output from the E-VSB block decoder 305 to the E-VSB data deformatter 411 of the E-VSB data processor 306 is a data group type. In this case, the E-VSB data deformatter 411 knows the configuration of the input data group and thus distinguishes signaling information having system information from enhanced data in the data group. The separated signaling information is transferred to the system information, and the enhanced data is output to the RS frame demultiplexer 412. The RS frame demultiplexer 412 classifies the enhanced data according to the type of service transmitted from the transmitter and outputs the enhanced data to each RS frame decoder 413a to 413c.

At this time, the E-VSB data deformatter 411 is added to the main data and the known data, trellis initialization data, MPEG header and the RS encoder / unstructured RS encoder or unstructured RS encoder of the transmission system. The RS parity is removed and output to the RS frame demultiplexer 412. Accordingly, the first to third RS frame decoders 413a to 413c receive only enhanced data that is RS-coded, CRC-coded, and interleaved in superframe units.

The first to third RS frame decoders 413a to 413c perform an inverse process on a corresponding RS frame encoder of a transmission system to correct errors in an RS frame, and then process an RS frame into an error corrected enhanced data packet. The MPEG sync bytes of 1 byte, which have been removed from the memory module, are added to the first to third E-VSB de-randomizers 414a to 414c, respectively. Detailed operation of each RS frame decoder will be described later.

The first to third E-VSB de-randomizers 414a to 414c respectively perform de-randomizing corresponding to the reverse process of the randomizer of the transmission system and output the received enhanced data, thereby transmitting them in the transmission system. You get one enhanced data. In an embodiment, assuming that all of the first to third E-VSB de-randomizers 414a to 414c are configured and all operate, three different types of enhanced data services are possible.

10B is another embodiment of the E-VSB data processing unit of the present invention. The difference between FIG. 10A and FIG. 10B is the location of the derandomizer. That is, since the derandomizer of the receiving system is a reverse process of the renderer of the transmitting system, the derandomizer position is located behind the RS frame demultiplexer in the receiving system according to the position of the renderer of the transmitting system as shown in FIGS. Or in front of the RS frame demultiplexer as shown in FIG.

That is, the E-VSB data processor of FIG. 10B includes an E-VSB data deformatter 511, a derandomizer 512, an RS frame demultiplexer 513, and a plurality of RS frame decoders 514a to 514c. It is composed. The number of RS frame decoders of FIG. 10B is one embodiment and may vary depending on the configuration of the transmission system, the type of enhanced data that can be serviced, the importance, and the like, and thus the present invention will not be limited to the embodiment described above.

Detailed description of the E-VSB data deformatter 511 may be referred to the E-VSB data deformatter of FIG. 10A, and thus this embodiment will be omitted.

10B, the derandomizer 512 is positioned in front of the RS frame decoders 514a to 514c. Therefore, in the de-rendering process, when the soft decision value is required in the RS frames decoders 514a to 514c in the subsequent stage and the soft decision value is input from the E-VSB block decoder 305, the soft decision value is decoded. Difficult to XOR with pseudo random bits for rendering.

Therefore, when the pseudo random bit to be XORed with respect to the soft decision value of the enhanced data bit is 1, the derandomizer 512 reverses the sign of the soft decision value. By outputting the code as it is, the soft decision state can be maintained and transmitted to the RS frame decoder.

The reason for changing the sign of the soft decision value when the pseudo random bit is 1 in the above explanation is that the output data bit is reversed when the pseudo random bit XORed to the input data bit in the randomizer of the transmission system is 1. That is, 0 XOR 1 = 1 and 1 XOR 1 = 0. In other words, when the pseudorandom bit generated by the de-randomizer 512 is 1, the value is reversed when the hard decision value of the enhanced data bit is XORed. Therefore, the soft decision value is output when the soft decision value is output. The sign of the value is reversed.

The following is a detailed operation of one RS frame decoder among the plurality of RS frame decoders of FIGS. 10A and 10B.

FIG. 11A illustrates a process of forming a single RS frame and an RS frame reliability map by collecting a plurality of data groups, for example, 18 data groups, and performing deinterleaving on a super frame basis in a reverse process of a transmission system. Afterwards, a process of reclassifying the deinterleaved RS frame and the RS frame credit map is shown.

That is, the RS frame decoder collects the received enhanced data to form an RS frame. The enhanced data is RS encoded in RS frames in the transmission system and interleaved in super frames. In this case, for example, CRC encoding may be performed (see FIG. 3) or omitted (see FIG. 4).

If it is assumed that RS frames having a size of (N + 2) * (187 + P) bytes in the transmitting system are divided into M (for example, 18) data groups and then transmitted, the receiving system also has the (a) of FIG. The enhanced data of each data group is gathered as follows to form an RS frame having a size of (N + 2) * (187 + P) bytes.

At this time, if a dummy byte is added and transmitted to at least one data group constituting the RS frame, the dummy byte is removed and an RS frame and an RS frame credit map are configured. For example, if K dummy bytes are added as shown in FIG. 7, after the K dummy bytes are removed, an RS frame and an RS frame credit map are configured.

In addition, assuming that the RS frames are divided into 18 data groups and transmitted in one burst period, the receiving system configures the RS frame by collecting enhanced data of 18 data groups in the burst period.

In this case, assuming that the decoding result is output by the E-VSB block decoder 305 as a soft decision value, the RS frame decoder may determine 0 and 1 of the corresponding bit as a sign of the soft decision value. The eight are gathered together to form one byte. Performing this process on all of the soft decision values of the 18 data groups in one burst, it is possible to construct an RS frame of size (N + 2) * (187 + P) bytes.

In addition, the present invention not only uses the soft decision value to construct an RS frame, but also to construct a reliability map.

The credit map indicates whether the corresponding byte formed by collecting eight bits determined by the sign of the soft decision value is reliable.

In an embodiment, when the absolute value of the soft determination value exceeds a preset threshold, the corresponding bit value determined by the sign of the soft determination value is determined to be reliable, and when it is not exceeded, it is determined to be unreliable. Then, in the case where it is determined that even one bit in one byte composed of eight bits determined by the sign of the soft decision value is unreliable, the credit map indicates that the byte is unreliable. Here, one bit is an embodiment, and when a plurality of, for example, four or more bits are determined to be unreliable, it may indicate that the corresponding byte is not reliable in the credit map.

On the contrary, when all bits in one byte are determined to be reliable, that is, when the absolute value of the soft decision value of all bits of one byte exceeds a preset threshold, the corresponding map is marked as reliable. Similarly, if a plurality of bits in one byte, for example, four or more bits are determined to be reliable, the credit map indicates that the bytes are reliable.

The above-described numerical values are merely examples, and the scope of the present invention is not limited to the numerical values.

The configuration of the RS frame and the configuration of the credit map using the soft decision value can be performed simultaneously. At this time, the credit information in the credit map corresponds 1: 1 to each byte in the RS frame. For example, if one RS frame has a (N + 2) * (187 + P) byte size, the credit map has a (N + 2) * (187 + P) bit size. 11A and 11B illustrate a process of forming a credit map according to the present invention.

In this case, the RS frame of FIG. 11A and the RS frame credit map of (b ') are interleaved in units of super frames (see FIG. 5). Therefore, after collecting the RS frame and the RS frame credit map to configure the super frame and the super frame credit map, as shown in (c) and (c ') of FIG. Deinterleaving is performed in units of frames.

When the deinterleaving is performed in the unit of the super frame as described above, the RS frame having the size of (N + 2) * (187 + P) bytes and (N + 2) deinterleaved as shown in (d) and (d ') of FIG. 11A. ) * Divided into RS frame credit maps of (187 + P) bits.

Then, error correction is performed on the deinterleaved RS frame using RS frame credit map information.

11B and 11C illustrate embodiments of an error correction process according to the present invention.

FIG. 11B illustrates an error correction process in the case where both RS encoding and CRC encoding are performed on an RS frame in a transmission system (see FIG. 3). FIG. 11C illustrates that only RS encoding is performed on an RS frame and CRC encoding is performed. FIG. 4 illustrates an error correction process when not performed (see FIG. 4).

The following describes the error correction process shown in FIG. 11B in detail.

That is, an RS frame of (N + 2) * (187 + P) byte size and an RS frame credit map of (N + 2) * (187 + P) bit size as shown in (a) and (a ') of FIG. 11B. If configured, CRC syndrome check is performed on this RS frame to check whether an error occurs in each row. Subsequently, as shown in (b) of FIG. 11B, an RS frame having a size of N * (187 + P) bytes is formed by removing a 2-byte CRC checksum, and an error flag corresponding to each row indicates whether an error occurs. Similarly, since the portion of the credit map corresponding to the CRC checksum is not utilized, this portion is removed to leave only N * (187 + P) credit information as shown in (b ') of FIG. 11B.

After the CRC syndrome check is performed as described above, RS decoding is performed in the column direction. In this case, RS erasure correction may be performed according to the number of CRC error flags. That is, as shown in (c) of FIG. 11B, the CRC error flag corresponding to each row in the RS frame is checked, and the maximum number of RS erasure corrections can be performed when the number of rows having an error is performed in the column direction RS decoding. Determine if it is less than or equal to the number of errors. The maximum number of errors is the number of parities (P) inserted during RS encoding.

In an embodiment of the present invention, it is assumed that the parity number P added to each column is 48.

In this case, if the number of rows having a CRC error is less than or equal to the maximum number of errors that can be corrected by RS erasure decoding (48 according to an embodiment), as shown in (d) of FIG. (235,187) -RS erasure decoding is performed in the column direction on an RS frame having 235 N byte rows, and as shown in (e) of FIG. 11B, 48 bytes of parity data added to the end of each column are removed.

However, if the number of rows having a CRC error is larger than the maximum number of errors that can be corrected by RS erasure decoding (that is, 48), RS erasure decoding cannot be performed.

In this case, error correction may be performed through general RS decoding. In addition, the present invention can further improve error correction capability by using a credit map generated when constructing an RS frame from the soft decision value.

That is, the RS frame decoder compares the absolute value of the soft decision value of the E-VSB block decoder 305 with a preset threshold value to determine the credit of the bit value determined by the sign of the soft decision value. Credit information for the corresponding byte formed by collecting eight bits determined by the sign of the soft decision value was displayed on the credit map.

Therefore, the present invention does not assume that all bytes of a row have an error even if the CRC syndrome check of a particular row determines that there is a CRC error as shown in FIG. 11B (c). Set the error to only those bytes that are considered unreliable. That is, only the bytes determined to be unreliable in the credit information of the credit map regardless of the CRC error of the corresponding row are set as erasure points.

Alternatively, the CRC syndrome check determines that there is a CRC error in the row, and sets an error only for bytes determined that the credit information of the credit map is unreliable. That is, only a byte having a CRC error in a corresponding row and determined to be unreliable in credit information of a credit map is set as an erasure point.

Then, if the number of error points for each column is less than or equal to the maximum error number that can be corrected by RS erasure decoding (that is, 48), RS erasure decoding is performed on the column. On the contrary, if the number of error points is larger than the maximum number that can be modified by RS erasure decoding (that is, 48), general RS decoding is performed on the column.

That is, if the number of rows with CRC errors is greater than the maximum number of errors that can be corrected by RS erasure decoding (for example, 48), then the corresponding columns are determined according to the number of erasure points in the corresponding column determined by the credit information of the credit map. RS erasure decoding is performed or general RS decoding is performed.

For example, the number of rows having a CRC error in the RS frame is greater than 48, and the number of erasure points determined by the credit information of the credit map is 40 in the first column and 50 in the second column. Suppose Then, (235,187) -RS erasure decoding is performed on the first column, and (235,187) -RS decoding is performed on the second column.

When the error correction decoding is performed in all column directions in the RS frame by performing the above process, as shown in (e) of FIG. 11B, 48 bytes of parity data added to the end of each column are removed.

As described above, in the present invention, even if the total number of CRC errors corresponding to each row in the RS frame is larger than the maximum number of errors that can be corrected by RS erasure decoding, the credit information of the corresponding column in the credit map of the corresponding column is corrected. As a result, if the number of bytes with low credit is equal to or smaller than the maximum error number correctable by RS erasure decoding, RS erasure decoding may be performed on the column.

Here, the difference between general RS decoding and RS erasure decoding is the number of correctable errors. That is, by performing normal RS decoding, errors can be corrected by the number corresponding to (number of parity) / 2 (eg, 24) inserted in the RS encoding process, and when RS erasure decoding is performed, RS encoding process is performed. An error may be corrected by the number of parities inserted (e.g., 48).

After the error correction decoding is performed as described above, as shown in (e) of FIG. 11B, an RS frame having 187 N-byte rows (ie, packets) can be obtained. RS frames of size 187 * N bytes are output in the order of N 187 bytes in size. In this case, as shown in (f) of FIG. 11B, each 187 byte packet includes one byte of MPEG sync bytes deleted from the transmission system. In addition, an enhanced data packet of 188 bytes is output.

Next, the error correction process illustrated in FIG. 11C will be described in detail.

That is, an RS frame of (N + 2) * (187 + P) byte size and an RS frame credit map of (N + 2) * (187 + P) bit size as shown in (a) and (a ') of FIG. 11C. If configured, RS decoding is performed in the column direction with reference to the credit map for this RS frame.

In FIG. 11C, since the CRC encoding is not performed on the enhanced data in the transmission system, the CRC syndrome check process is omitted and there is no CRC error flag to refer to when RS decoding. That is, it is not possible to determine whether each row is an error. Therefore, in performing RS decoding of each column, FIG. 11C performs RS decoding with reference to a credit map generated when constructing an RS frame from a soft decision value.

(B) and (b ') of FIG. 11C further illustrate an RS frame credit map of (N + 2) * (187 + P) byte size and an RS frame credit map of (N + 2) * (187 + P) bit size. It is concrete, and has the same meaning as (a), (a ') of FIG. 11C.

That is, the RS frame decoder compares the absolute value of the soft decision value of the E-VSB block decoder 305 with a preset threshold value to determine the credit of the bit value determined by the sign of the soft decision value. Credit information for the corresponding byte formed by collecting eight bits determined by the sign of the soft decision value was displayed on the credit map.

Therefore, the present invention sets an error only for bytes determined to be unreliable by referring to credit information of a credit map as shown in (c) of FIG. 11C. That is, only bytes determined to be unreliable in credit information of a credit map are set as erasure points.

Then, if the number of error points for each column is less than or equal to P (for example, 48) which is the maximum error number that can be corrected by RS erasure decoding, RS erasure decoding is performed on the column. On the contrary, if the number of error points is larger than P (for example, 48) which is the maximum number that can be modified by RS erasure decoding, general RS decoding is performed on the column.

For example, suppose that the number of erasure points determined by the credit information of the credit map in the RS frame is displayed in the first column and 50 in the second column. Then, (235,187) -RS erasure decoding is performed on the first column, and (235,187) -RS decoding is performed on the second column.

On the other hand, if the number of bytes determined to be untrusted by another method of referencing credit information in decoding each column is less than or equal to P / 2, general RS decoding is performed. If it is smaller or equal, RS erasure decoding may be performed, and if it is larger than P, RS decoding may be performed by performing general RS decoding again. In this case, the above-described method may perform better according to a threshold value or a specific situation for determining credit information, and in another case, the above-described method may perform better.

In addition, the selection of which RS decoding method to use is not limited to FIG. 11C, but is applicable to the methods described with reference to FIG. 11B. That is, in the case of FIG. 11B, when the number of CRC errors is less than or equal to P, only an embodiment using a method of decoding all columns with the same erasure point is illustrated, but the CRC error is yet another method. Even if the number of times is less than or equal to P, it is further subdivided. When the number of CRC errors is less than or equal to P / 2, RS decoding is performed. When the number of CRC errors is greater than P / 2 and less than or equal to P, RS erasure decoding can be performed. Similarly, when the number of CRC errors is greater than P, the CRC error information and the credit information of each byte of the credit map are referred together. In this case, the credit map information belongs to a row indicating a CRC error in decoding each column. If the number of undetermined bytes is less than or equal to P / 2, RS decoding can be used; if RS is greater than P / 2 and less than or equal to P, RS erasure decoding is used; . Also, as another embodiment, RS erasure decoding or RS decoding may be selected based on a value less than or equal to P.

On the other hand, if the error correction decoding is performed in all column directions in the RS frame by performing the above process, as shown in (d) of FIG. 11C, 48 bytes of parity data added to the end of each column are removed.

As described above, when the error correction decoding of a specific column in an RS frame is performed, if the number of bytes having a low credit is equal to or smaller than the maximum error number that can be corrected by RS erasure decoding, RS erasure decoding may be performed.

After the error correction decoding is performed as described above, an RS frame having 187 N + 2 byte rows (that is, a packet) can be obtained as shown in (d) of FIG. 11C. In addition, RS frames having a size of (N + 2) * (187 + P) bytes are output in the order of N + 2 187 bytes, in this case, as shown in (e) of FIG. An MPEG data byte of 1 byte deleted in S is added to output an enhanced data packet in units of 188 bytes.

The present invention described so far is not limited to the above-described embodiments, and can be modified by those skilled in the art as can be seen from the appended claims, and such modifications are the scope of the present invention. Belongs to.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Figure 1a is a block diagram showing an embodiment of the E-VSB preprocessor in the transmission system according to the present invention

Figure 1b is a block diagram showing another embodiment of the E-VSB preprocessor in the transmission system according to the present invention

2 is an overall block diagram of a transmission system according to an embodiment of the present invention;

3A to 3E illustrate error correction encoding and error detection encoding processes according to an embodiment of the present invention.

4 (a) to (d) illustrate an error correction encoding process according to another embodiment of the present invention.

5A to 5D are diagrams illustrating an interleaving process in units of a super frame according to an embodiment of the present invention.

6A and 6B illustrate examples of data configurations before and after the data deinterleaver in the transmission system according to the present invention.

7A and 7B illustrate an embodiment of a process of dividing an RS frame to form a data group according to the present invention.

8 illustrates an example of an operation of a packet multiplexer for transmitting a data group according to the present invention.

9 is a block diagram illustrating a digital broadcast receiving system according to an embodiment of the present invention.

10A and 10B are block diagrams illustrating embodiments of the E-VSB data processor of FIG. 9.

11A to 11C illustrate a decoding process of an RS frame decoder according to embodiments of the present invention.

* Description of the symbols for the main parts of the drawings *

100,110: E-VSB preprocessor 101a, 101b, 101c, 113: randomizer

102a, 102b, 102c, 111a, 111b, 111c: frame encoder

103,112: RS frame multiplexer

104, 114: block processing unit 105, 115: group formatter

106,116 deinterleaver 107,117 packet formatter

121: packet multiplexer

Claims (20)

A signal receiving unit configured to receive a broadcast signal including K dummy bytes, wherein M data groups are configured from an RS frame including first error corrected coded first data, wherein at least one of the M data groups includes: A demodulator for demodulating the broadcast signal; A block decoder for decoding first data of the demodulated broadcast signal in block units; A demultiplexer for outputting the block decoded first data to a corresponding one of a plurality of paths; And And at least one RS frame decoder configured to correct error generated in the first data by performing error correction decoding in units of RS frames on the first data received through the corresponding path. The method of claim 1, The broadcast signal further comprises a second error correction coded second data. The method of claim 1, A plurality of data packets including first data in the RS frame, an RS parity generated in each column based on the plurality of data packets, and a CRC generated in each row based on the plurality of data packets and the RS parity Receiving system comprising a checksum is received. The method of claim 3, wherein The K dummy bytes are determined by applying the following equation. K = M * NoBytesPerGrp-(N + 2) * (187 + P) NoBytesPerGrp = number of bytes of first data contained in the data group (N + 2) = number of bytes in each row that make up an RS frame (187 + P) = number of bytes in each column that make up an RS frame N = number of bytes of first data included in each row P = number of bytes of RS parity data contained in each column The method of claim 1, wherein the RS frame decoder And an error generated in the first data in units of the RS frame based on the number of errors estimated from the RS frame and a credit map indicating the credit information of the first data. The method of claim 5, wherein the RS frame decoder And receiving the CRC decoding on the RS frame to estimate the number of errors. 7. The RS frame decoder of claim 6, wherein the RS frame decoder RS in the column direction for all columns of the RS frame if the number of errors indicated in the error flag corresponding to each row in the RS frame by the CRC decoding is less than or equal to the number of parities added to the column direction of the RS frame. A receiving system, characterized by performing erasure decoding. 7. The RS frame decoder of claim 6, wherein the RS frame decoder If the number of errors indicated in the error flag corresponding to each row in the RS frame by the CRC decoding is greater than the number of parity added in the column direction of the RS frame, general RS decoding and RS for each column based on the credit map And determining one of the erasure decoding, and performing error correction with the determined error correction decoding method for the column. The method of claim 1, And a known data detector for detecting a known data stream from the data group. The method of claim 9, And an equalizer for compensating for channel distortion generated in the first data by using the detected known data sequence. Receiving a broadcast signal including M data groups from an RS frame including first error corrected encoded first data, wherein at least one of the M data groups includes K dummy bytes; Demodulating the broadcast signal; Decoding first data among the demodulated broadcast signals in block units; Outputting the block decoded first data to a corresponding one of a plurality of paths; And And correcting an error generated in the first data by performing error correction decoding in units of RS frames on the first data received through the corresponding path. The method of claim 11, The broadcast signal further comprises a second error correcting coded second data. The method of claim 11, A plurality of data packets including first data in the RS frame, an RS parity generated in each column based on the plurality of data packets, and a CRC generated in each row based on the plurality of data packets and the RS parity and a checksum is included and received. The method of claim 13, The K dummy bytes are determined by applying the following equation. K = M * NoBytesPerGrp-(N + 2) * (187 + P) NoBytesPerGrp = number of bytes of first data contained in the data group (N + 2) = number of bytes in each row that make up an RS frame (187 + P) = number of bytes in each column that make up an RS frame N = number of bytes of first data included in each row P = number of bytes of RS parity data contained in each column 12. The method of claim 11 wherein the error correction step is And correcting an error generated in the first data in units of the RS frame based on the number of errors estimated from the RS frame and a credit map indicating credit information of the first data. . The method of claim 15, wherein the error correction step And estimating the number of errors by performing CRC decoding on the RS frame. 17. The method of claim 16 wherein the error correction step is RS in the column direction for all columns of the RS frame if the number of errors indicated in the error flag corresponding to each row in the RS frame by the CRC decoding is less than or equal to the number of parities added to the column direction of the RS frame. Erasure decoding data processing method characterized in that the receiving system. 17. The method of claim 16 wherein the error correction step is If the number of errors indicated in the error flag corresponding to each row in the RS frame by the CRC decoding is greater than the number of parity added in the column direction of the RS frame, general RS decoding and RS for each column based on the credit map A method for processing data in a receiving system, characterized in that one of the erasure decoding is determined, and error correction is performed using the determined error correction decoding method for the column. The method of claim 11, Detecting a known data stream from the data group. The method of claim 19, And compensating for channel distortion generated in the first data by using the detected known data sequence.

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