KR20090013954A - Method for fabricating of nonvolatile memory device - Google Patents

Abstract

A method for fabricating of nonvolatile memory device is provided to realize minute wire of the semiconductor device by forming thickness of a photoresist layer thinner on the substrate including a floating gate. In a method for fabricating of nonvolatile memory device, an element isolation film(109) is formed on the semiconductor substrate(100) and is divided into a cell region and a logic area. A laminated oxide film(112a), a floating gate(114a), a dielectric film(116) and a control gate(119) are formed on the cell region of the semiconductor substrate. The photoresist layer(200) is formed so that the element isolation film on the cell region is exposed to the outside. After the element isolation film is removed through an etching process, an implant processing is performed and the common source area is formed on the element isolation film. The oxide film and the laminated logic gate of the structure are formed on the logic area.

Description

Method for Fabricating a Nonvolatile Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, and more particularly, to a method of manufacturing a nonvolatile memory device capable of preventing an impurity from being injected into a logic region during impurity injection into a cell region.

Flash memory is a type of programmable ROM (PROM) that allows electrical data rewriting. Flash memory has an EPROM (Erasable PROM) in which a memory cell is composed of one transistor and has a small cell area but must be erased by UV light. In combination with (Electrically Erasable PROM), the device is made to perform the program input method of the EPROM and the erase method of the EEPROM as one transistor, and its exact name is Flash EEPROM. Such a flash memory is called a nonvolatile memory because the memory information does not disappear even when the power is turned off. In this regard, the flash memory is different from a DRAM (Dynamic RAM) and a Static RAM (SRAM).

Flash memory can be divided into NOR-type structures in which cells are arranged in parallel between bit lines and ground, and NAND-type structures arranged in series, according to a cell array scheme. NOR flash memory, which is a parallel structure, is widely used for booting a mobile phone because high-speed random access is possible when performing a read operation.NAND flash memory, which is a serial structure, is generally used for data storage because of a slow reading speed but a fast writing speed. It has a merit that it is suitable for the and suitable for miniaturization.

1A to 1D are cross-sectional views illustrating a manufacturing process of a nonvolatile memory device according to the prior art.

Referring to FIG. 1A, a device isolation layer 19 is first formed on a P-type semiconductor substrate 10 defined as a cell region and a logic region, and then a tunnel oxide layer is formed on the semiconductor substrate 10. 12a and a gate oxide film 12b are formed. Subsequently, after depositing a first polysilicon material, which is a floating gate material, on the cell region on the tunnel oxide layer 12a, the first polysilicon layer 14 is formed through a photolithography and an etching process using a photoresist. do. Subsequently, an ONO (Oxide / Nitride / Oxide) film 16 is deposited on the first polysilicon film 14 as a dielectric film to insulate the control gate deposited in a subsequent process, and then the ONO film ( A second polysilicon film 18, which is a control gate material, is deposited on the entire surface of the semiconductor substrate 10 including the semiconductor substrate 10.

Referring to FIG. 1B, a plurality of floating gates 14a and a plurality of floating gates 14a are formed on a cell area in a photolithography and etching process using a photoresist on a second polysilicon material 18, and an ONO film is formed on the plurality of floating gates 14a. 16 and the control gate 19 are formed by stacking.

Subsequently, as shown in FIG. 1C, the second polysilicon layer 18 on the logic region is patterned through photolithography and etching processes to form the stacked gate insulating layer and the logic gate 21.

Referring to FIG. 1D, a thin photoresist material is applied to the entire surface of the substrate 10 including the plurality of logic gates 21 and then formed to expose the device isolation region 5 through a photolithography and an etching process. Subsequently, the common source region 24 is formed under the semiconductor substrate 10 on which the device isolation region 5 is exposed using impurities.

At this time, an unwanted N-type impurity region is formed due to impurities in the logic region to which the thinly formed photoresist material is applied, thereby causing a problem of insufficient process margin and productivity. In addition, if the photoresist material is thickly formed to prevent this, a problem arises in that the photoresist residue remains in the device isolation layer area when the photoresist material is subsequently removed.

In order to solve the above problems, the present invention provides a method of manufacturing a nonvolatile memory device capable of preventing impurities from being injected into a logic region when impurity is injected into a cell region.

In order to achieve the above technical problem, a method of manufacturing a nonvolatile memory device according to the present invention comprises the steps of forming an isolation layer on a semiconductor substrate defined by a cell region and a logic region, and after forming an oxide film on the entire surface of the semiconductor substrate And sequentially forming a floating gate polysilicon film and a dielectric film on the cell region, and forming a control gate polysilicon film on the semiconductor substrate including the floating gate polysilicon film and a dielectric film. Patterning the oxide film, the floating gate polysilicon film, the dielectric film, and the control gate polysilicon film on the cell region to form a stacked oxide film, the floating gate, the dielectric film, and the control gate in the same pattern; Forming a photoresist layer to expose the device isolation film on the substrate And removing the device isolation layer through an etching process, forming a common source region in the device isolation layer by performing an implant process, and patterning the oxide layer and the polysilicon layer for the control gate on the logic region to form a stacked oxide layer. And forming a logic gate.

The manufacturing method of the nonvolatile memory device according to the present invention has the following effects.

First, by forming a thin thickness of the photoresist layer on the semiconductor substrate including the floating gate, the exposure amount may be small, so that the productivity of the photo process is improved and the fine line width of the semiconductor element can be formed.

Second, since the photoresist layer is thinly formed, resolution can be increased.

Third, by forming a common source / drain in the device isolation region, the area occupied by the cell region can be reduced.

Fourth, since the polysilicon film is formed on the entire logic region, it is possible to prevent impurities from being injected into the substrate of the logic region since the polysilicon film is not affected by the impurities during the subsequent implant process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2A to 2D.

2A through 2D are cross-sectional views illustrating a manufacturing process of a nonvolatile memory device according to the present invention.

Referring to FIG. 2A, first, a conventional LOCOS or shallow trench isolation (STI) is formed on a P-type semiconductor substrate 100 defined as a cell area and a logic area. After the device isolation film 109 is formed through the device isolation process through the transistor), the tunnel oxide film 112a and the gate gate are disposed on the logic region using a dry or wet oxidation method in a temperature range of 750 ° C to 900 ° C. An oxide film 112b is formed. The tunnel oxide film 112a and the gate oxide film 112b may be formed at the same time or may have different thicknesses on each region.

Subsequently, a polysilicon material, which is a floating gate material, is deposited on the entire surface of the semiconductor substrate 100 including the tunnel oxide film 112a and the gate oxide film 112b, and then a cell region is formed through a photo and etching process using a photoresist. The first polysilicon film 114 is formed in the film.

The first polysilicon film 114 may be formed to a thickness of about 500 to 2000 kPa, and may be formed of 80 to 80 by low pressure-chemical vapor deposition (LP-CVD) using SiH ₄ or Si ₂ H ₆ and PH ₃ gas. It may be formed at a temperature of about 620 ℃ and pressure conditions of about 0.1 to 3 Torr.

Subsequently, an ONO (Oxide / Nitride / Oxide) film 116 is deposited on the first polysilicon film 114 as a dielectric film to insulate the control gate deposited in a subsequent process, and then the ONO film ( 116 is selectively removed so as to remain only in the cell region through a photo and etching process using photoresist. Subsequently, a second polysilicon film 118 is formed of a polysilicon material on the entire surface of the semiconductor substrate 100 including the ONO film 116.

Referring to FIG. 2B, the gate oxide film 112b and the second polysilicon are sequentially stacked on the entire logic region by a photolithography and an etching process using a photoresist on the entire surface of the semiconductor substrate 100 including the second polysilicon layer 118. The film 118 remains, and at the same time, the tunnel oxide film 112a, the floating gate 114a, the ONO film 116, and the control gate 119, which are sequentially stacked on the cell region, are formed in the same pattern.

Referring to FIG. 2C, after the photoresist layer 200 is formed on the entire surface of the semiconductor substrate 100 on which the plurality of floating gates 114a and the logic gates 118a are formed, the device isolation layer is exposed through photolithography and etching processes. Optionally remove Here, the photoresist layer 200 is formed to a thin thickness of 0.6 to 0.8㎛, and thus the resolution can be increased to 0.26 to 0.29㎛ compared with the conventional.

Subsequently, a device isolation layer is formed by performing a reactive ion etching (RIE) process on the photoresist layer 200 where the device isolation layer 109 is exposed to form a self aligned source (SAS) region. After removing 109, an implant process for forming a common source and drain region (not shown) is performed on the semiconductor substrate 100 to form a common source region 124 under and on the device isolation layer 109. . Here, it is preferable to proceed with the implant process using N-type impurities in order to increase hot carrier generation. In other words, the implant process is characterized in that the impurity of As at a concentration of 1 × 10 ¹⁴ to 1 × 10 ¹⁵ is carried out with an energy of 20 ~ 40 KeV.

In this case, since the second polysilicon layer 118, which is a logic gate material, is formed on the entire surface of the logic region, impurities may be prevented from being implanted into the logic region because the second polysilicon layer 118 is not affected by impurities during the implant process. In addition, by forming a thin photoresist layer 200 on the semiconductor substrate 100 including the second polysilicon film 118, it is possible to form a fine line width of the semiconductor device.

In this case, when the semiconductor substrate 100 is N-type, an implant process may be performed using P-type impurities, in contrast to the above method.

Next, as shown in FIG. 2D, the photoresist layer 200 thinly formed on the semiconductor substrate 100 including the second polysilicon film 118 is removed. Subsequently, the gate oxide layer 112b and the logic gate 122 stacked on the logic region are formed in the same pattern through a photolithography and an etching process using a photoresist.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

1A to 1D are cross-sectional views illustrating a manufacturing process of a nonvolatile memory device according to the prior art.

2A to 2D are cross-sectional views illustrating a manufacturing process of a nonvolatile memory device according to the present invention.

* Description of the symbols for the main parts of the drawings *

100 semiconductor substrate 112 tunnel oxide film

114a: Floating gate 116: ONO film

120: control gate 124: common source region

Claims (6)

Forming an isolation layer on a semiconductor substrate defined by a cell region and a logic region; Forming an oxide film on the entire surface of the semiconductor substrate, and then sequentially forming a floating gate polysilicon film and a dielectric film on the cell region; Forming a polysilicon film for a control gate on the semiconductor substrate including the floating gate polysilicon film and a dielectric film; Patterning the oxide film, the floating gate polysilicon film, the dielectric film, and the control gate polysilicon film on the cell region to form the stacked oxide film, the floating gate, the dielectric film, and the control gate in the same pattern; Forming a photoresist layer to expose the device isolation layer on the cell region; Removing the device isolation layer through an etching process and then performing an implant process to form a common source region in the device isolation layer; And patterning the oxide film and the polysilicon film for a control gate on the logic region to form a stacked oxide film and a logic gate. The method of claim 1, The photoresist layer is a method of manufacturing a nonvolatile memory device, characterized in that formed in a thickness of 0.6 to 0.8 ㎛. The method of claim 1, The etching process is a method of manufacturing a nonvolatile memory device, characterized in that using a reactive ion etching (RIE) process. The method of claim 3, wherein The reactive ion etching process is a method of manufacturing a non-volatile memory device, characterized in that using a mixed gas of argon (Ar) and oxygen (O ₂ ). The method of claim 1, The implant process is a method of manufacturing a nonvolatile memory device, characterized in that the impurity of 1 × 10 ¹⁴ to 1 × 10 ¹⁵ concentration of 20 ~ 40 KeV energy. The method of claim 1, And the common source region is formed on the lower and side surfaces of the device isolation layer.

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