KR20090009561A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided to form a capacitor by using metal patterns, thereby simplifying a manufacturing process and increasing capacitance. A gate electrode(114) is formed on a semiconductor substrate(100). An impurity region(105) is formed within the semiconductor substrate of both sides of the gate electrode. A contact plug(124) connected to the impurity region is formed. Subsequently, a capacitor(200) is formed on the outcome. The capacitor comprises first metal patterns(132a,152a) connected with the contact plug, second metal patterns(132b,152b) around the first metal patterns, and interlayer insulating films(140,160) filled between the first and second metal patterns. The first metal patterns configure a first electrode of the capacitor. The second metal patterns configure a second electrode of the capacitor.

Description

Semiconductor device and method for manufacturing the same {Semiconductor device and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a capacitor formed using a metal wiring and a method for manufacturing the same.

In recent years, the area of a unit cell is rapidly decreasing as a semiconductor device such as DRAM becomes more integrated and larger in capacity. Accordingly, the area occupied by the capacitor formed in each unit cell of the semiconductor device is also reduced. However, even if the area where the capacitor is to be formed is reduced, the minimum capacitance that determines the storage capacity of the memory device must be maintained. Therefore, the capacitance of the capacitor must be increased within the limited area.

As a method of increasing the capacitance of the capacitor, there is a method of using a material having a high dielectric constant as the dielectric film, a method of reducing the thickness of the dielectric, or a method of increasing the surface area of the electrode.

Among them, a capacitor having a three-dimensional structure may be used to increase the surface area of the electrode. However, in the case of a three-dimensional capacitor, the manufacturing method is complicated, and if the height of the capacitor is continuously increased, the capacitor may fall down.

An object of the present invention is to provide a semiconductor device including a capacitor using a metal wiring.

In addition, another technical problem to be solved by the present invention is to provide a method for manufacturing such a semiconductor device.

The technical problem to be achieved by the present invention is not limited to the above-mentioned problem, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, a semiconductor device includes a gate electrode on a semiconductor substrate, an impurity region formed in a semiconductor substrate on both sides of the gate electrode, a contact plug connected to the impurity region, and a first metal pattern connected to the contact plug. And a capacitor comprising second metal patterns formed around the first metal pattern and an insulating film filled between the first metal pattern and the second metal patterns.

In order to achieve the above technical problem, a semiconductor device manufacturing method according to an embodiment of the present invention includes forming a gate electrode on a semiconductor substrate, forming an impurity region in the semiconductor substrate on both sides of the gate electrode, and contacting the impurity region. Forming a plug and forming a capacitor comprising a first metal pattern connected with the contact plug, second metal patterns around the first metal pattern, and an insulating film filled between the first metal pattern and the second metal patterns .

Specific details of other embodiments are included in the detailed description and the drawings.

According to the semiconductor device of the present invention and a method of manufacturing the capacitor, by forming the capacitor using the metal patterns, unlike the method of forming the lower electrode having a large surface area to increase the capacitance of the capacitor, it is possible to simplify the manufacturing process of the capacitor. Accordingly, the cost of the semiconductor device manufacturing process can be reduced. In addition, since the parasitic capacitance between adjacent metal patterns can be increased by repeatedly forming the metal patterns, the capacitance can be easily increased and the degree of integration of the semiconductor device can be increased.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, including and / or comprising the components, steps, operations and / or elements mentioned exclude the presence or addition of one or more other components, steps, operations and / or elements. I never do that.

In addition, the embodiments described herein will be described with reference to cross-sectional and / or plan views, which are ideal exemplary views of the present invention. Accordingly, the shape of the exemplary diagram may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in forms generated by the manufacturing process. For example, the etched regions shown at right angles may be rounded or have a predetermined curvature. Accordingly, the regions illustrated in the figures have schematic attributes, and the shape of the regions illustrated in the figures is intended to illustrate a particular form of region of the device and not to limit the scope of the invention.

Hereinafter, a semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to FIGS. 1A, 1B, and 2 to 6.

First, a structure of a semiconductor device according to exemplary embodiments of the present invention will be described with reference to FIGS. 1A, 1B, and 2. 1A and 1B are layout views of a semiconductor device according to some embodiments of the present invention, and FIG. 2 is a cross-sectional view of the semiconductor device according to some embodiments of the present invention, taken along line II-II ′ of FIGS. 1A and 1B. It is a cross-sectional view.

1A, 1B, and 2, an active region 104 is defined in the semiconductor substrate 100 by an isolation layer 102. Here, the active region 104 may have a '-' shape as shown in FIG. 1A, or may have a 'TT' shape in which a predetermined region protrudes as shown in FIG. 1B. The shape of the active region 104 is not limited thereto, and may be changed into various shapes according to the structure of the semiconductor device.

As such, a plurality of gate lines 110 intersecting the active region 104 are positioned on the semiconductor substrate 100 in which the active region 104 is defined. The gate line 110 may have a structure in which the gate insulating layer 112, the gate electrode 114, and the silicide layer 116 are stacked on the semiconductor substrate 100, and spacers are formed at both sides of the stacked structure. have.

An impurity doped region 105 is formed in the semiconductor substrate 100 at both sides of the gate line 110.

The first interlayer insulating layer 120 is positioned on the semiconductor substrate 100 on which the gate lines 110 are formed, and the first and second contact plugs are in contact with the impurity region 105 in the first interlayer insulating layer 120. 122 and 124 are formed. The first and second contact plugs 122 and 124 are formed of polysilicon or a metal material doped with impurities, and a silicide layer (between the first and second contact plugs 122 and 124 and the impurity region 105) is formed. Not shown). The first and second contact plugs 122 and 124 may be self aligned with respect to the gate line 114.

More specifically, the first contact plug 122 is connected to the source region of the impurity regions 105 in the semiconductor substrate 100 and the second contact plug 124 is the impurity regions 105 in the semiconductor substrate 100. It is connected to the middle drain region.

As such, the upper portion of the first interlayer insulating layer 120 including the first and second contact plugs 122 and 124 is planarized, and the capacitor 200 and the bit of the semiconductor device are disposed on the upper portion of the first interlayer insulating layer 120. Line 192 is formed.

In more detail, the capacitor 200 formed on the first interlayer insulating layer 120 may include metal patterns 132a, 132b, 152a, 152b, and 172, and metal patterns 132a, 132b, 152a, 152b, and 172. It is formed by using parasitic capacitance generated by the insulating film filling the gap.

That is, the first metal pattern 132a is formed on the first interlayer insulating layer 120 to contact the first contact plug 122, and the second metal patterns 132b are formed around the first metal pattern 132a. It is. In this case, the second metal patterns 132b are formed adjacent to the first metal pattern 132a to be mutually coupled with the first metal pattern 132a. The third metal pattern 132c is formed on the second contact plug 124. In this case, the third metal pattern 132c is disposed between the second metal patterns 132b and may serve to expand the contact area of the lower second contact plug 124.

As such, the second interlayer insulating layer 140 is positioned on the first interlayer insulating layer 120 on which the metal patterns 132a, 132b, and 132c are formed. The first to third metal patterns 152a, 152b, and 152c are formed on the second interlayer insulating layer 140 in the same manner as the metal patterns 132a, 132b, and 132c on the first interlayer insulating layer 120. That is, the first to third metal patterns 132a, 132b, 132c, 152a, 152b, and 152c are disposed up and down, respectively.

In the second interlayer insulating layer 140, vias 142 and 144 connecting lower metal patterns 132a, 132b and 132c and upper metal patterns 152a, 152b and 152c are formed. have.

The third interlayer insulating layer 160 covering the metal patterns 152a, 152b, and 152c is positioned on the second interlayer insulating layer 140, and the lower second metal patterns 152b are disposed in the third interlayer insulating layer 140. Connected vias 162 are formed. Another second metal pattern 172 is formed on the third interlayer insulating layer 160. Here, the second metal pattern 172 may be formed to correspond to the second metal pattern 152b disposed below, but may be connected to one upper portion of the first metal pattern 152a as shown in the figure. That is, the second metal pattern 172 on the third interlayer insulating layer 160 is connected to the second metal patterns 152b positioned at both sides of the first metal pattern 152a disposed below.

As such, the capacitor 200 of the unit cell is formed by the first and second metal patterns 132a, 132b, 152a, 152b, and 172 positioned on the first contact plug 122.

In the capacitor 200, the first metal patterns 132a and 152a connected to the first contact plug 122 serve as a first electrode of the capacitor 200, and the second metal is positioned around the first electrodes. The patterns 132b, 152b, and 172 serve as the second electrode, and the interlayer insulating layers 140 and 160 between the first and second electrodes serve as the dielectric film of the capacitor. Accordingly, parasitic capacitance is formed between the metal patterns 132a, 132b, 152a, 152b, and 172 to ensure capacitance per unit cell.

Meanwhile, in the embodiment of the present invention, the metal patterns 132a, 132b, 152a, 152b, and 172 and the interlayer insulating layers 140, 160, and 180 are formed over three layers, but the capacitance of the capacitor is described. It may be formed repeatedly over multiple layers to increase.

In addition, the third metal pattern 132a and the vias 144, 164, and 184 are repeatedly positioned in each interlayer insulating layer 140, 160, and 180 on the second contact plug 124, and the fourth interlayer insulating layer ( The bit line 192 is formed on the 180. In this case, the bit line 192 may be disposed vertically or horizontally with lower gate lines 110. In addition, in one embodiment of the present invention, the bit line 192 is positioned above the capacitor 200. Alternatively, the bit line 192 may be located below the capacitor 200.

As such, the metal patterns 132a, 132b, 152a, 152b, and 172 and the bit line 192 disposed on the first and second contact plugs 122 and 124 may include titanium (Ti), tantalum (Ta), It is formed of a metal material such as nickel (Ni), cobalt (Co) or tungsten (W).

As described above, the capacitor formed using the metal wiring per unit cell may overcome the limitation of the manufacturing process when forming the capacitor as the integration degree of the semiconductor device is reduced. In addition, by repeatedly forming the metal patterns, the capacitance of the capacitor can be increased.

Hereinafter, a method of manufacturing a semiconductor device according to embodiments of the present invention will be described in detail with reference to FIGS. 1A, 1B, and 2 to 6. 3 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with embodiments of the present invention.

First, referring to FIG. 3, a device isolation layer 102 defining an active region 104 is formed by performing a local oxide of silicon (LOCOS) process or a shallow trench isolation (STI) process on a semiconductor substrate 100. In this case, the active region 104 may be defined in various shapes such as a '-' shape or a 'TT' shape shown in FIGS. 1A and 1B.

After defining the active region 104, a plurality of gate lines 110 are formed on the semiconductor substrate 100 to extend in one direction across the active region 104. The gate lines 110 may be formed by sequentially stacking and patterning a gate insulating layer 112 and a conductive layer for a gate electrode on the semiconductor substrate 100. As a result, the gate electrode 114 is formed on the gate insulating layer 112. In this case, the gate insulating layer 112 may be formed of an oxide layer, and the gate electrode 114 may be formed of a polysilicon layer doped with impurities. Then, spacers are formed on both sides of the gate insulating film 112 and the gate electrode 114.

Thereafter, impurities are implanted into the semiconductor substrate 100 using the gate line 110 and the device isolation layer 102 as an ion implantation mask. As a result, an impurity region 105 is formed in the semiconductor substrate 100 on both sides of the gate electrode 114, thereby completing a transistor per unit cell of the semiconductor device.

After forming the transistor, the silicide process may proceed. When the silicide process is performed, the silicide layer 116 may be formed on the top surface of the gate electrode 114 and the top surface of the impurity region 105.

In more detail, after the transistors are completed, a silicide metal film is deposited on the entire surface of the semiconductor substrate 100 on which the gate electrode 114 and the impurity region 105 are formed. Thereafter, a heat treatment process is performed on the entire surface of the metal film to be silicided. Then, the silicide film 116 is formed on the gate electrode 114 and the impurity region 105 by removing the metal film remaining unsilicided.

Next, referring to FIG. 4, an insulating material is deposited on the entire surface of the semiconductor substrate 100 on which the gate lines 110 are formed, and a chemical mechanical polishing (CMP) or etch back process is performed. The first interlayer insulating film 120 is formed by planarizing the upper portion. The first interlayer insulating layer 120 may be formed of silicon oxide, or may be formed of an insulating material having a low dielectric constant (low-k), such as HSQ (Hydrogen Silsesquioxane), MSQ (Methyl Silsesquioxane), MHSQ (Methyl Hydrogen Silsesquioxane), or the like. .

Thereafter, a normal photolithography process is performed on the first interlayer insulating layer 120 to form a contact hole exposing the impurity region 105 in the semiconductor substrate 100. Then, polysilicon or metal material is embedded in the contact holes to form the first and second contact plugs 122 and 124. That is, a first contact plug 122 electrically connected to the source region and a second contact plug electrically connected to the drain region are formed in the first interlayer insulating layer 120.

Subsequently, capacitors are formed per unit cell of the semiconductor device on the first interlayer insulating layer 120 including the first and second contact plugs 122 and 124. In more detail, first, a plurality of metal patterns 132a, 132b, and 132c are formed on the first interlayer insulating layer 120. Here, the plurality of metal patterns 132a, 132b, and 132c may be formed by forming and then patterning a metal film on the entire surface of the first interlayer insulating film 120. For example, titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co) or tungsten (W) may be used as the metal film.

When forming the plurality of metal patterns 132a, 132b, and 132c, the first metal pattern 132a is formed on the first contact plug 122, and the first metal is surrounded by the first metal pattern 132a. The second metal pattern 132b is spaced apart from the pattern 132a by a predetermined interval. Here, the second metal pattern 132b should be formed to be spaced apart enough to be mutually coupled with the first metal pattern 132a. At the same time, a third metal pattern 132c spaced apart from the second metal pattern 132b is formed on the second contact plug 124. The third metal pattern 132c may serve to extend the second contact plug 124.

Next, referring to FIG. 5, a second interlayer insulating layer 140 is formed on the first interlayer insulating layer 120 on which the first to third metal patterns 132a, 132b, and 132c are formed. Here, the second interlayer insulating layer 140 may be formed of silicon oxide or an insulating material having a low dielectric constant, like the first interlayer insulating layer 120. The second interlayer insulating layer 140 formed as described above fills between the lower metal patterns 132a, 132b, and 132c, and thus serves as a dielectric between the metal patterns 132a, 132b, and 132c.

Then, vias 142 and 144 electrically connected to the metal patterns 132a, 132b, and 132c are formed in the second interlayer insulating layer 140. In this case, the vias 142 and 144 may be coupled to each other as the degree of integration of the semiconductor device decreases, thereby increasing the capacitance of the capacitor.

Subsequently, metal patterns 152a, 152b, and 152c connected to the respective vias 144 are formed on the second interlayer insulating layer 140. The metal patterns 152a, 152b, and 152c formed on the second interlayer insulating layer 140 may be formed in the same manner as the lower metal patterns 132a, 132b, and 132c. That is, first to third metal patterns 152a, 152b, and 152c are formed on the second interlayer insulating layer 140.

Next, referring to FIG. 6, a third interlayer insulating layer 160 is formed on the second interlayer insulating layer 140 on which the first to third metal patterns 152a, 152b, and 152c are formed. In addition, vias 162 and 164 are formed in the third interlayer insulating layer 160 to be connected to the second and third metal patterns 152b and 152c, respectively.

Meanwhile, the vias 162 and 164 in the third interlayer insulating layer 160 may be formed on the metal patterns 152a, 152b and 152c, as formed in the second interlayer insulating layer 140. That is, the metal patterns 152a, 152b, and 152c and the vias 162 and 164 in the third interlayer insulating layer 160 may have the same structure as the structure formed in the second interlayer insulating layer 140. In addition, multilayer interlayer insulating layers may be interposed between the second and third interlayer insulating layers 140 and 160, and metal patterns and vias are formed in each interlayer insulating layer to form a structure in which metal patterns are stacked over the multilayer. It may be formed to have.

Vias 162 and 164 are formed in the third interlayer insulating layer 160, and then second metal patterns 172 are formed on the third interlayer insulating layer 160. The second metal patterns 172 on the third interlayer insulating layer 160 are formed in a line shape on the first and second metal patterns 152a and 152b disposed below. In addition, the second metal patterns 172 are in contact with the bars 162 formed on the second metal patterns 152b formed at the lower portion thereof, and are electrically connected to the second metal patterns 152b.

As described above, the capacitor 200 per unit cell is completed by the first and second metal patterns 132a, 132b, 152a, 152b, and 172 over the second to third interlayer insulating layers 120 and 140.

As described above, the capacitor 200 is formed using the metal patterns 132a, 132b, 152a, 152b, and 172, so that the manufacturing process of the capacitor is different from the method of forming the lower electrode having a large surface area in order to increase the capacitance of the capacitor. Can be simplified. Accordingly, the cost of the semiconductor device manufacturing process can be reduced. In addition, since the parasitic capacitance between adjacent metal patterns can be increased by repeatedly forming the metal patterns, the capacitance can be easily increased and the degree of integration of the semiconductor device can be increased.

Next, referring to FIG. 2, a fourth interlayer insulating layer 180 is formed on the third interlayer insulating layer 180 on which the line-shaped second metal patterns 172 are formed, and in the fourth interlayer insulating layer 180, A via 184 is formed to be electrically connected to the second contact plug 124. A bit line 192 is then formed on the fourth interlayer insulating layer 180 to be in contact with the via 184. In the embodiment of the present invention, the bit line 192 has been described as being formed on top of the capacitors, but the bit line 192 may be formed under the capacitor.

As such, the first to third metal patterns 132a, 132b, 132c, 152a, 152b, 152c, and 172 formed over the second to fourth interlayer insulating layers 140, 160, and 180 may be titanium (Ti) or tantalum. It may be formed of a metal material such as (Ta), nickel (Ni), cobalt (Co), or tungsten (W).

In addition, when the metal patterns 132a, 132b, 152a, 152b, and 172 for forming the capacitor 200 are formed on the second to fourth interlayer insulating layers 140, 160, and 180, the cell regions are positioned around the cell region. In the peripheral circuit region, metal wires for forming a logic device may be formed in the same layer where the metal patterns are formed.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

1A is a layout diagram of a semiconductor device according to example embodiments.

1B is a layout diagram of a semiconductor device according to another embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor device according to example embodiments of the present invention, taken along line II-II ′ of FIGS. 1A and 1B.

3 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with embodiments of the present invention.

<Explanation of symbols on main parts of the drawings>

100: semiconductor substrate 102: device isolation film

104: active region 105: source and drain region

110: gate line 112: gate insulating film

114: gate electrode 116: silicide film

120: first interlayer insulating film 122: first contact plug

124: second contact plug 132a and 152a: first metal pattern

132b, 152b, and 172: second metal pattern 132c and 152c: third metal pattern

140: second interlayer insulating film 160: third interlayer insulating film

180: fourth interlayer insulating film 192: bit line

142, 144, 162, 164, 184: Via

Claims (8)

A gate electrode on the semiconductor substrate; An impurity region formed in the semiconductor substrate on both sides of the gate electrode; A contact plug connected to the impurity region; And And a capacitor including a first metal pattern connected to the contact plug, second metal patterns formed around the first metal pattern, and an insulating layer filled between the first metal pattern and the second metal patterns. The method of claim 1, The first metal patterns constitute a first electrode of the capacitor, and the second metal patterns constitute a second electrode of the capacitor. The method of claim 2, The first and second metal patterns are formed over a plurality of interlayer insulating layers, and the first and second metal patterns are respectively disposed on upper and lower portions thereof. The method of claim 3, wherein And a via connecting the first and second metal patterns formed in the multilayer interlayer insulating layers to each other. The method of claim 4, wherein The second metal pattern positioned on the uppermost layer is a semiconductor device formed in a line shape on the first metal pattern. Forming a gate electrode on the semiconductor substrate, An impurity region is formed in the semiconductor substrate on both sides of the gate electrode, Forming a contact plug connected to the impurity region, Forming a capacitor comprising a first metal pattern connected with the contact plug, second metal patterns around the first metal pattern, and an insulating layer filled between the first metal pattern and the second metal patterns Manufacturing method. The method of claim 6, wherein forming the capacitor, Forming the first and second metal patterns on the contact plug, Forming an interlayer insulating film covering the first and second metal patterns; Forming vias in the interlayer insulating layer to be connected to the first and second metal patterns, respectively; And forming first and second metal patterns on the vias to correspond to the first and second metal patterns on the bottom, respectively. The method of claim 7, wherein And forming the first and second metal patterns over the multilayer interlayer insulating layer, wherein the second metal pattern positioned on the uppermost layer is formed in a line shape on the first metal pattern.

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