KR20090007971A - Semiconductor device and fabrication method for the same - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided to broaden a width of a storage node contact, thereby suppressing generation of misalignment of a capacitor positioned on the storage node contact. A transistor is formed in a substrate(100) including an active area and an inactive region. A first insulation layer(270) is formed on the substrate. A second insulation layer(330) including a bit line is formed on the first insulation layer. A contact mask pattern(400) is formed on the second insulation layer. A barrier layer(431) is formed within the second insulation layer. A first etching process using the contact mask pattern is performed to form a contact hole in the second insulation layer. A second etching process is performed. A width of the contact hole is extended to form a second storage node contact hole. A first storage node contact hole is formed in the first insulation layer by using the contact mask pattern. Conductive material is reclaimed in the first and second storage node contact hole. First and second storage node contacts(460,470) are formed.

Description

Semiconductor device and fabrication method {Semiconductor device and fabrication method for the same}

The present invention relates to a semiconductor device having a contact margin for misalignment that may occur when a storage node contact is in contact with a capacitor, and a method of manufacturing the same.

One of the semiconductor devices, DRAM, is composed of cells including a transistor and a capacitor. Such semiconductor devices have a trend toward miniaturization and thinning, and as a result, high integration is required, design rules of semiconductor devices are rapidly reduced, and thus cell cross-sectional area is reduced. Therefore, the cross-sectional area of the storage node contact connecting the capacitor and the portion of the transistor is reduced, and the possibility of misalignment between the storage node contact and the capacitor is increased. Miss alignment can deteriorate the characteristics of the semiconductor device by increasing the contact resistance.

An object of the present invention is to provide a semiconductor device having a contact margin for misalignment that may occur when a storage contact is in contact with a capacitor.

Another object of the present invention is to provide a method of manufacturing a semiconductor device having a contact margin for misalignment that may occur when a storage contact is in contact with a capacitor.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, a semiconductor device includes an active region and an inactive region, and includes a substrate including a transistor in the active region, a substrate located on the substrate, and a source of the transistor. A first insulating layer including a first storage node contact connected to a second / drain region, and a second insulating layer disposed on the first insulating layer, the first insulating layer contact being located on the first storage node contact, and the first storage node contact And a second insulating layer that is wider and includes a second storage node contact formed to overlap the gate of the transistor, and a capacitor located on the second storage node contact.

According to one or more exemplary embodiments, a method of manufacturing a semiconductor device includes forming a transistor on a substrate including an active region and an inactive region, forming a first insulating layer on the substrate, A second insulating layer including a bit line is formed on a first insulating layer, a contact mask pattern is formed on the second insulating layer, a barrier layer is formed in the second insulating layer, and the contact mask pattern is used. By performing a first etching process to form a contact hole in the second insulating layer, by performing a second etching process, the width of the contact hole is formed to form a second storage node contact hole, by using the contact mask pattern A first storage node contact hole is formed in the first insulating layer, and a conductive material is filled in the first and second storage node contact holes, so that the first and second storage node contacts are formed. It includes forming.

Other specific details of the invention are included in the detailed description and drawings.

The semiconductor device as described above can suppress the occurrence of misalignment of the capacitor located on the storage node contact by widening the width of the storage node contact. Therefore, deterioration of the characteristics of the semiconductor element can be prevented.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only the embodiments are to make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Although the first, second, etc. are used to describe various elements, components and / or sections, these elements, components and / or sections are of course not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Therefore, the first device, the first component, or the first section mentioned below may be a second device, a second component, or a second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.

Hereinafter, a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2. 1 is a plan view illustrating a semiconductor device in accordance with an embodiment of the present invention.

First, referring to FIG. 1, word lines 230a and 230b and bit lines 310 crossing at an angle with respect to the active region 120 are formed on a semiconductor substrate including the active region 120 and the inactive region. Formed. The storage node contacts 471 formed in the same direction as the word lines 230a and 230b overlap the word lines 230a and 230b. These storage node contacts 471 are separated by bit lines 310. A barrier layer 431 is formed between the neighboring storage node contacts 471 so as to completely overlap the inactive region of the semiconductor substrate 100. Here, the capacitor (not shown) is in contact with the contact connected to the source / drain region of the semiconductor substrate 100, so that the portion 500 in which the capacitor is in contact with the storage node contact 471 overlapping the active region 120. Can be formed.

2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. In FIG. 2, A is a cross-sectional view taken along the line a-a 'of FIG. 1, and B is a cross-sectional view taken along the line b-b' of FIG. 1.

Referring to FIG. 2, a transistor is formed in the semiconductor substrate 100. In the figure, a recess channel transistor is illustrated as a transistor. Specifically, the semiconductor substrate 100 is separated into an active region and an inactive region by a device isolation layer 110 formed in the semiconductor substrate 100 by using shallow trench isolation (STO) or field oxide (FOX). The recess channel 210 is formed. Since the recess channel 210 is formed obliquely to the active region, the recess channel 210 may be formed not only in the active region but also partially in the inactive region in the semiconductor substrate 100 as shown in B of FIG. 2. have. The gate insulating layer 220 is formed on the recess channel 210. The gate insulating layer 220 may be, for example, a material such as a silicon oxide layer (SiOx), a silicon oxynitride layer (SiON), or the like. The first and second gates 230a and 230b protruding from the recess channel 210 and protruding above the recess channel are formed on the gate insulating layer 220. The first and second gates 230a and 230b may include a stacked layer of polysilicon 232 and a gate metal 234. Spacers 240 may be formed on both sidewalls of the protruding first and second gates 230a and 230b. In addition, source / drain regions 250 and 260 into which impurities are implanted are provided in the active regions on both sides of the first and second gates 230a and 230b. For example, when the semiconductor substrate 100 is a P-type semiconductor substrate, the source / drain regions 250 and 260 may be formed by ion implantation of N-type impurities.

A first insulating layer 270 having a first storage node contact 460 and a bit line contact 281 is formed on the semiconductor substrate 100 to cover the transistor. Specifically, the first and second gates 230a and 230b may be covered with a pair of first storage node contacts 460 formed adjacent to the outside of the first and second gates 230a and 230b, respectively. The first insulating layer 270 is formed. Here, the first insulating layer 270 may be an oxide film.

A second insulating layer 330 including a bit line 310, a second storage node contact 470, and a barrier layer 431 is formed on the first insulating layer 270. Here, the second insulating layer 330 may be an oxide film as the same material as the first insulating layer 270.

The bit line 310 is formed to cross the first and second gates 230a and 230b and is connected to the bit line contact 281 provided in the first insulating layer 270. The bit line 310 includes a conductive layer 312 and a mask layer 314, and bit line spacers are formed on sidewalls of the bit line 310. The structure of the bit line is not limited thereto, and a polysilicon layer may be further formed on the mask layer.

The second storage node contacts 470 are formed between the bit lines 310 and are separated by the bit lines 310 and the bit line spacers. In addition, the pair of second storage node contacts 470 are formed on the pair of first storage node contacts 460 formed adjacent to the outside of the first and second gates 230a and 230b, respectively. Thus, the pair of second storage node contacts 470 is connected to the pair of first storage node contacts 460. Here, the second storage node contact 470 is wider than the first storage node contact 460. In detail, the second storage node contact 470 is wider in the direction of the first and second gates 230a and 230b than the first storage node contact 460. In other words, the second storage node contact 470 may be wider in the opposite direction of the barrier layer 431 than the first storage node contact 460. Cross sections of the pair of second storage node contacts 470 adjacent to the first and second gates 230a and 230b may be symmetrical. The second storage node contact 470 may overlap at least some of the first and second gates 230a and 230b. Here, the first and second storage node contacts 470 may be a conductive material, for example, polysilicon. Although not illustrated, the wide second storage node contact 470 may secure a margin for misalignment with the capacitor when contacting the capacitor formed on the upper portion. As a result, the contact resistance can be lowered and the deterioration of the characteristics of the semiconductor element can be suppressed.

In addition, the barrier layer 431 provided on the second insulating layer 330 is formed to completely overlap the inactive region of the semiconductor substrate 100 between the adjacent second storage node contacts 470. In other words, it is formed between the pair of second storage node contacts 470 and the pair of second storage node contacts 470. The barrier layer 431 may be formed of a material having an etching selectivity higher than that of the second insulating layer 330. For example, it may be silicon nitride, but is not limited thereto.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 3 to 10. 3 through 10 are cross-sectional views for sequentially describing a method of manufacturing a semiconductor device. In each of the drawings, A is a cross-sectional view taken along the line a-a 'of FIG. 1, and B is a cross-sectional view taken along the line b-b' of FIG.

First, as illustrated in FIG. 3, a transistor is formed in the semiconductor substrate 100, and a first insulating layer 270 is formed to cover the transistor and include a bit line contact 281.

Specifically, gates 230a and 230b may be formed on the semiconductor substrate 100 in which the active region and the inactive region are separated by an isolation layer 102 such as shallow trench isolation (STI) or field oxide (FOX). Form. The gates 230a and 230b are formed by forming the recess channel 210 and the gate insulating layer 220 in the semiconductor substrate 100, and subsequently stacking the polysilicon 232 and the gate metal 234. Spacers 240 may be formed on both sidewalls of the gates 230a and 230b. In this case, the gates 230a and 230b may be formed obliquely with respect to the active region.

Therefore, the first and second gates 230a and 230b may be formed in the semiconductor substrate 100 in the inactive region as well as the active region. Impurity ions are implanted into the semiconductor substrate 100 between the gates 230a and 230b to form source / drain regions 250 and 260. As a result, recess channel transistors are formed that include gates 230a and 230b and source / drain regions 250 and 260. Here, although the example of forming the recess channel transistor has been described, the structure of the transistor is not limited thereto.

Then, the first insulating layer 270 is formed on the semiconductor substrate 100 on which the transistors are formed. In this case, as the first insulating layer 270, for example, Borosilicate Glass (BSG), PhosphoSilicate Glass (PSG), BoroPhosphoSilicate Glass (BPSG), Undoped Silicate Glass (USG), TetraEthlyOrthoSilicate Glass (TEOS), or HDP- It may be formed using an oxide such as CVD (High Density Plasma-CVD).

Then, the bit line contact hole 280 is formed using an etch mask that exposes the source region between the first and second gates 230a and 230b, and a conductive material is filled in the bit line contact hole 280. Put it in. Subsequently, chemical mechanical polishing (CMP) or etch-back forms bit line contact 281.

Subsequently, as shown in FIG. 4, the second insulating layer 330 having the bit line 310 is formed on the first insulating layer 270.

In detail, the bit line 310 having the conductive layer 312 and the mask layer 314 stacked on the first insulating layer 270 may be formed by stacking the conductive layer and the mask layer. 281) formed on top. In this case, the bit line 310 may be formed to cross on the gate, that is, the word line. The material of the conductive layer 312 may be W, Ti, or TiN, or a combination thereof, and the mask layer 314 may be nitride. Here, the structure of the bit line 310 is not limited thereto, and a multilayer conductive layer may be formed, and a polysilicon layer may be further formed on the mask layer.

Thereafter, nitride is deposited on the first insulating layer 270 and the bit line 310 and etched to form bit line spacers on both sidewalls of the bit line 310.

Subsequently, after depositing the same material as the first insulating layer 270, that is, oxide, on the resultant, the second insulating layer 330 is formed by chemical mechanical polishing (CMP) or etch-back. do.

Subsequently, a barrier layer 431 is formed in the second insulating layer 330, and a contact mask pattern 400 is formed on the second insulating layer 330.

First, as shown in FIG. 5, the contact mask pattern 400 is formed on the second insulating layer 330. The contact mask pattern 400 may be formed as a line on the second insulating layer 330 along the gates 230a and 230b, and may have a width that completely overlaps the first and second gates 230a and 230b. . The contact mask pattern 400 may be formed to cross the bit line 310. The material of the contact mask pattern 400 may be polysilicon.

Subsequently, as shown in FIG. 6, contact mask spacers 410 are formed on both sidewalls of the contact mask pattern 400.

Specifically, an insulating material is deposited on the resultant of FIG. 5 and planarized to expose the contact mask pattern 400 to form a third insulating layer. The third insulating layer may be formed of a silicon nitride film. Thereafter, a separation for exposing the first insulating layer 270 on a region where the pair of first and second gates 230a and 230b and the other pair of first and second gates 230a and 230b are separated. After the etching mask is formed on the third insulating layer, the third insulating layer is etched. Here, by etching the third insulating layer, contact mask spacers 410 are formed on both sidewalls of the contact mask pattern 400 on the second insulating layer.

Subsequently, as shown in FIG. 7, a barrier layer 431 is formed in the second insulating layer 330.

Specifically, by etching the exposed second insulating layer 330 by using a separation etching mask formed on the third insulating layer, the pair of first and second gates 230a and 230b and the pair of first and second A barrier hole 430 is formed in an upper portion of the region where the second gates 230a and 230b are separated. Then, an insulating material is deposited on the resultant, and the insulating material is filled in the barrier hole 430. Thereafter, the insulating material of the third insulating layer is etched using the contact mask pattern 400 as an etch mask. At this time, the contact mask spacer 410 is also etched together. Therefore, the contact mask pattern 400 may be formed of a material having an etching selectivity higher than that of the third insulating layer and the contact mask spacer 410. As a result, the barrier layer 431 is formed in the second insulating layer 330 so as to completely overlap the inactive region of the semiconductor substrate 100 between the neighboring storage node contacts 471. Therefore, the barrier layer 431 may be formed of a material having a higher etching selectivity than the second insulating layer 330. The barrier layer 431 may be formed of, for example, silicon nitride.

Subsequently, as shown in FIG. 8, the first hole is etched to form a contact hole 440 in the second insulating layer 330.

In detail, the contact hole 440 is formed on the drain of the semiconductor substrate 100 by etching the second insulating layer 330 exposed by the contact mask pattern 400. In this case, the barrier layer 431 formed in the second insulating layer 330 is exposed by the contact mask pattern 400, but is not etched because the etching selectivity is higher than that of the second insulating layer 330. In addition, the mask layer 314 of the bit line 310 exposed to the contact mask pattern 400 is also not etched because the etch selectivity is higher than that of the second insulating layer 330.

Subsequently, as shown in FIG. 9, the second storage layer is etched to form a second storage node contact hole 442 in the second insulating layer 330.

In detail, the second storage node contact hole 442 is formed by extending the contact hole 440 formed in the second insulating layer 330. In this case, the contact hole 440 is expanded by isotropic etching using the contact mask pattern 400 and the barrier layer 431. Isotropic etching can be accomplished by wet etching using LAL etchant, diluted hydrofluoric acid (HF) or mixtures thereof. In this case, the barrier layer 431 is not etched because the etching selectivity is higher than that of the second insulating layer 330. Therefore, the width of the contact hole 440 does not extend in the direction of the barrier layer 431 but may extend in the direction opposite to the barrier layer 431. As a result, the second storage node contact hole 442 is formed to extend in the opposite direction of the barrier layer 431, that is, in the directions of the first and second gates 230a and 230b.

Subsequently, as illustrated in FIG. 10, a first storage node contact hole 450 is formed in the first insulating layer 270.

In detail, the first storage node contact hole 450 is formed in the first insulating layer 270 by etching the first insulating layer 270 exposed by the contact mask pattern 400 and the barrier layer 431. .

Subsequently, the semiconductor device illustrated in FIG. 2 may be formed by filling the first and second storage node contact holes 442 and 450.

Specifically, by depositing a conductive material on the resultant of FIG. 9, the conductive material is filled in the first and second storage node contact holes 442 and 450, and the chemical mechanical polishing is performed to expose the second insulating layer 330. CMP) or etch-back to form first and second storage node contacts 460 and 470. In this case, polysilicon may be used as the conductive material to fill the first and second storage node contact holes 442 and 450, but is not limited thereto.

The first storage node contact 460 is formed on the drain 250 region of the semiconductor substrate 100, and the second storage node contact 470 is formed on the first storage node contact 460. Here, the second storage node contact 470 is wider than the first storage node contact 460. In detail, the second storage node contact 470 is wider in the direction of the first and second gates 230a and 230b than the first storage node contact 460. Accordingly, a portion of the second storage node contact 470 may be formed to overlap the first and second gates 230a and 230b, and the pair of storage node contacts 471 may include the first and second gates. It may be formed symmetrically about (230a, 230b).

Thereafter, a capacitor may be formed on the second storage node contact 470 by a subsequent process. In this case, by forming the second storage node contact 470 wider than the first storage node contact 460, the contact area with the capacitor may be increased. This ensures a margin for misalignment that may occur due to the high integration of semiconductor devices. Therefore, the semiconductor device including the storage node contact can prevent the misalignment from occurring, thereby preventing deterioration of the characteristics of the semiconductor device and driving the semiconductor device stably.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

1 is a plan view illustrating a semiconductor device in accordance with an embodiment of the present invention.

2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

3 to 10 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

100: semiconductor substrate 110: device isolation film

230a, 230b: first and second gates 270: first insulating layer

310: bit line 330: second insulating layer

400: contact mask pattern 431: barrier layer

460: First storage node contact 470: Second storage node contact

Claims (8)

A substrate comprising an active region and an inactive region, the substrate having a transistor in the active region; A first insulating layer on the substrate, the first insulating layer including a first storage node contact connected to a source / drain region of the transistor; A second insulating layer on the first insulating layer, wherein the second storage node contact is formed on the first storage node contact, is wider than the first storage node contact, and is formed to overlap the gate of the transistor; A second insulating layer comprising; And And a capacitor positioned on the second storage node contact. According to claim 1, The second insulating layer includes a barrier layer, The barrier layer is formed between neighboring second storage node contacts. The method of claim 2, The barrier layer is formed of a material having a higher etching selectivity than the second insulating layer. The method of claim 2, The barrier layer is formed of silicon nitride. Forming a transistor on a substrate comprising an active region and an inactive region, Forming a first insulating layer on the substrate, Forming a second insulating layer including a bit line on the first insulating layer, Forming a contact mask pattern on the second insulating layer, Forming a barrier layer in the second insulating layer, Forming a contact hole in a second insulating layer by performing a first etching process using the contact mask pattern, By performing a second etching process, the width of the contact hole is extended to form a second storage node contact hole, A first storage node contact hole is formed in a first insulating layer using the contact mask pattern, Forming a first and second storage node contacts by filling a conductive material in the first and second storage node contact holes. The method of claim 5, The barrier layer may form a contact mask spacer by depositing and etching an insulating material on a resultant formed with the contact mask pattern, And depositing a barrier material on the resultant and etching the second insulating layer to expose the second insulating layer. The method of claim 6, The contact mask pattern is formed of a material having a higher etching selectivity than the contact mask spacer. The method of claim 5, The first etching process is performed anisotropically, and the second etching process is an isotropic semiconductor device manufacturing method.

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