KR20080113459A - Multi channel frequency and function generator - Google Patents

Multi channel frequency and function generator Download PDF

Info

Publication number
KR20080113459A
KR20080113459A KR1020070061947A KR20070061947A KR20080113459A KR 20080113459 A KR20080113459 A KR 20080113459A KR 1020070061947 A KR1020070061947 A KR 1020070061947A KR 20070061947 A KR20070061947 A KR 20070061947A KR 20080113459 A KR20080113459 A KR 20080113459A
Authority
KR
South Korea
Prior art keywords
frequency
function
generator
unit
output
Prior art date
Application number
KR1020070061947A
Other languages
Korean (ko)
Inventor
곽재영
Original Assignee
(주)세오전자
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by (주)세오전자 filed Critical (주)세오전자
Priority to KR1020070061947A priority Critical patent/KR20080113459A/en
Publication of KR20080113459A publication Critical patent/KR20080113459A/en

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02Digital function generators
    • G06F1/03Digital function generators working, at least partly, by table look-up
    • G06F1/0321Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K7/00Modulating pulses with a continuously-variable modulating signal
    • H03K7/08Duration or width modulation ; Duty cycle modulation

Abstract

The present invention relates to a multi-channel frequency and a function waveform generator,

The apparatus of the present invention comprises a power supply for supplying power to the apparatus; An external function signal unit capable of receiving a function signal required for the device from an external device; A display showing the operational status of the device; A function generator for outputting a frequency of each unique waveform; A microprocessor responsible for assigning or controlling data and addresses to each function generator; A button input unit for setting a frequency value required for the device or starting or stopping the operation of the device; An oscillator (OSC) for generating a clock required for the function generator; A pulse unit which is an output unit of a frequency generated by each individual function generator; A MUX for synthesizing a plurality of pulses that are outputs of the plurality of function generators; It includes an output for outputting the mixed frequency from a plurality of function generators to the outside.

According to the present invention, the multi-channel frequency and the function waveform generator is capable of simultaneously outputting multiple frequencies to multiple channels, and it is possible to use multiple frequencies simultaneously, and outputting various types of waveforms to each channel. It is possible.

In addition, it is a device capable of generating a new frequency by synthesizing a plurality of frequencies and outputting, it is also possible to generate and output a variety of waveforms by using the superposition method of the waveform.

Description

Multi-Channel Frequency and Function Waveform Generator

1 is an overall block diagram of a multi-channel frequency and math waveform generator.

Denoted at 10 is a power supply for supplying power to the multi-channel frequency generator.

Reference numeral 15 denotes an external function signal unit that can receive a function signal required for a multi-channel frequency generator from an external device.

Reference numeral 20 is a display showing the operating state of the device.

Reference numeral 30 is a microprocessor which is responsible for assigning or controlling data and addresses to each function generator in order to create unique waveforms for each function generator.

40 is a button input unit for setting a desired frequency value or starting or stopping an operation.

Numeral 50 denotes a function generator that outputs the frequency of each unique waveform.

Reference numeral 60 is an oscillator (OSC) for generating a clock required for the function generator 50.

Reference numeral 70 denotes a pulse unit that is an output unit of a frequency generated by each function generator.

Reference numeral 80 is a MUX for synthesizing a plurality of pulses which are outputs of a plurality of function generators.

90 is the final output of the mixed frequencies in the multiple function generators.

Most of the existing function generators or conventional frequency generators have been a method of sustaining or outputting only a specific frequency for a predetermined time.

In a conventional frequency generator, when the clock inside the device is determined, the maximum frequency that can be generated in the device is determined. However, in the multi-channel frequency generator of the present invention, since a plurality of frequencies can be synthesized using the internal function generator and the MUX, the maximum output frequency is much higher than the frequency that the internal clock of the apparatus can independently output. High frequency output is possible.

In addition, the existing function generator or the existing frequency generator was able to output only some waveforms such as triangular wave, sine wave and square wave.

However, the device of the present invention can synthesize waveforms of a plurality of frequencies or constant frequencies, thereby generating various types of waveforms.

1. It is possible to implement a function generator with a time delay.

2. Various types of waveforms can be generated.

3. Frequency synthesis allows the generation of frequencies higher than the maximum frequency of the device's internal clock.

4. It is possible to synthesize the function signal inside the device by receiving the function signal of the external device.

5. In the absence of a particular type or a specific time delay, the device is capable of random frequency output or white noise output.

1 is an overall block diagram of a multi-channel frequency generator.

Denoted at 10 is a power supply for supplying power to the multi-channel frequency generator.

Reference numeral 15 denotes an external function signal unit that can receive a function signal required for a multi-channel frequency generator from an external device.

Reference numeral 20 is a display showing the operating state of the device.

Reference numeral 30 is a microprocessor which is responsible for assigning or controlling data and addresses to each function generator in order to create unique waveforms for each function generator.

40 is a button input unit for setting a desired frequency value or starting or stopping an operation.

Numeral 50 denotes a function generator that outputs the frequency of each unique waveform.

Reference numeral 60 is an oscillator (OSC) for generating a clock required for the function generator 50.

Reference numeral 70 is a pulse unit that is an output unit of a frequency generated by each function generator.

Reference numeral 80 is a MUX for synthesizing a plurality of pulses which are outputs of a plurality of function generators.

90 is the final output of the mixed frequencies in the multiple function generators.

2 is an internal block diagram of a function generator.

The function generator 50 has a buffer 51 for amplifying and stabilizing a clock supplied from an external oscillator (OSC) 60 and supplying a clock signal therein.

Decoder 53 which decodes the signal of the address bus and decodes the control latch 52, the time delay PWM generator 54, and the time delay unit 55 by making DECODERBUS. Wow

Control Latch 52, which is selected as a chip select signal generated from external data and decoder 53 to create a Control Bus.

A time delay unit 55 for generating an ENABLE signal after delaying the corresponding time, and a time delay PWM generator 54 operating after the ENABLE signal;

It consists of a three-state buffer 58 that determines whether to output the signal generated by this time delay PWM generator 54.

In addition, the function generator 50 has the address ADDRESS and data DATA controlled by the microprocessor, delays the time for a delay time desired by the user, and then generates a PWM frequency. ) Starts the operation by writing a START signal to the control latch selected by the microprocessor 30.

The time delay unit 55 operates first, and the time delay unit 55 delaying the user-specified time generates an ENABLE signal, and the time delay PWM generator 54 acquiring the ENABLE signal is desired by the data input by the user. The PWM pulse PULSE is supplied to the three state buffer 58.

When the data is initially written to the time delay PWM generator 54 and the time delay unit 55, the user inputs the frequency of the function generator 50, and the microprocessor operates the control latch 52. To generate a SELECT signal.

If the corresponding SELECT signal is generated, the frequency is output from the pulse unit 70 by outputting the PWM pulse supplied from the time delay PWM generator to the outside, and if not selected, the corresponding pulse unit ( 70) no output is generated.

3 is a time delay PWM generator.

The time delay PWM generator 54 includes two pieces of data: a pulse width latch unit 110 storing data for determining a pulse width, and a frequency latch unit 120 storing data for determining a frequency of a generated PWM. Data of the binary counter 130 and the pulse width latch 110 and the binary counter 130 operating with the supplied clock (CLOCK) and the ENABLE signal supplied from the time delay unit 55. Comparator 2 (150), which compares the data of the data, to determine the pulse width, and compares the data of the frequency latch 120 and the data of the binary counter 130 to determine the frequency. (Comparator 1) 140 and flip-flop 160 for generating pulses from signals output from the comparators 140 and 150, respectively.

Unlike the conventional PWM module, the time delay PWM generator 54 is started by the ENABLE signal supplied from the time delay unit 55.

When the operation of the binary counter 130 starts, the binary counter value is continuously increased with the input clock CLOCK. The data of the counter and the pulse width latch 110 are compared with the comparator 2 (Comparator 2). 2) 150 are compared, and if the same value is generated, a clock signal is generated in the flip-flop 160 to invert the flip-flop 160 Q value.

After that, the comparator 1 140 compares the data of the frequency latch 120 that stores the frequency value of the PWM pulse PULSE with the counter value that is continuously increasing, and if the value is the same, a binary counter. 130 is cleared and the flip-flop 160 is cleared at the same time to invert the Q value again and outputs a PWM pulse PULSE whose duty ratio and frequency are changed after one cycle.

4 is a time delay unit.

The time delay unit 55 is a portion that delays the PWM generation start time.

The time delay unit 55 outputs an output when the data of the counter 220 that counters the clock externally and the data of the latch 210 in which the PWM delay time is stored are the same (Comparator 3). And a flip-flop 230 which produces a signal which delays the PWM pulse PULSE by a desired time with the signal output from the comparator 240.

First, the delay time data is written into the latch 210 selected from the decoder bus DECODERBUS by the microprocessor. When the START signal is given from the control bus, the counter 220 operates. The initial value is written into the flip-flop 230.

The counter 220 continuously increases the value with the supplied clock CLOCK, and in the comparator 3 240, the latch 210 value and the counter 220 value are obtained. When the comparison results in the same value, since all the delayed time has passed, the flip-flop 230 is reset to supply the ENABLE signal to the time delay PWM generator 54.

In addition, the ENABLE signal operates as a DISABLE to stop the counter 220 inside the time delay unit 55.

5 is a block diagram illustrating a state in which both the time delay PWM generator and the time delay unit are connected.

6, 7, and 9 are output through the MUX 80 which synthesizes various frequency waveforms of the pulse unit 70 of a plurality of function generators and these various frequency waveforms. An example of the waveform of the output unit 90 is shown.

In the pulse section of each of the plurality of function generators (1, 2, 3, ... n), n frequencies are output from 1, 2, 3, respectively. After synthesized through), the new frequency of the new waveform is output through the output unit 90.

8 shows an output unit 90 for outputting waveforms of various pulse widths of the same frequency from the pulse unit 70 of a plurality of function generators, and outputting them through the MUX 80 for synthesizing these waveforms. Another example of a waveform is shown.

In the pulse section of each of the multiple function generators (1, 2, 3, ... n), waveforms with n pulse widths from 1, 2, 3, which are different, are output. After synthesis through 90, the new frequency of the new waveform is output through the output unit 90.

FIG. 10 shows an output unit 90 outputting waveforms of the same pulse width at the same frequency from the pulse unit 70 of the plurality of function generators, and outputting them through the MUX 80 that synthesizes these waveforms. Another example of a waveform is shown.

The same frequency which is time-delayed in the pulse part of each of the plurality of function generators (1, 2, 3, ... n) is output, and these same frequency waveforms are synthesized through the MUX 90 and then output. The new frequency is output through the unit 90.

In the same way as above,

Various types of waveforms are output from the pulse unit 70 of the plurality of function generators. These waveforms may have the same frequency or different frequency values, and the new form through the MUX 80 that synthesizes these waveforms. It is possible to output a waveform of, and these new types of waveforms can generate the same frequency or a new frequency.

The multi-channel frequency output device of the present invention has the following advantages.

1. It is possible to output various frequencies by using frequency overlap.

2. Various waveforms can be generated and output.

3. By using the frequency superposition method, it is possible to output higher frequency than the clock inside the device.

4. Multi-channel frequency and function waveform generator can output several frequencies at the same time to several channels, and it is possible to use several frequencies at the same time, and it is possible to output various waveforms to each channel.

5. It is possible to generate and output a new frequency by synthesizing a plurality of frequencies. It is also possible to generate and output various waveforms by using the superposition method of waveforms.

Claims (5)

The apparatus of the present invention comprises a power supply for supplying power to the apparatus; An external function signal unit capable of receiving a function signal required for the device from an external device; A display showing the operational status of the device; A function generator for outputting a frequency of each unique waveform; A microprocessor responsible for assigning or controlling data and addresses to each function generator; A button input unit for setting a frequency value required for the device or starting or stopping the operation of the device; An oscillator (OSC) for generating a clock required for the function generator; A pulse unit which is an output unit of a frequency generated by each individual function generator; A synthesis unit (MUX) for synthesizing a plurality of pulses which are outputs of a plurality of function generators; Multi-channel frequency and function waveform generator, characterized in that it comprises an output unit for outputting the mixed frequency from the plurality of function generator to the outside. The method of claim 1, wherein the function generator A buffer for amplifying and stabilizing a clock supplied from an external oscillator (OSC) 60 to supply a clock signal therein; A decoder which decodes the signal of the address bus and decodes the control bus and generates a decoder bus to the control latch and the time delay PWM generator 54 and the time delay unit 55. Decoder); A control latch selected as an external data and a chip select signal generated from a decoder 53 to generate a control bus; A time delay unit for generating an ENABLE signal after delaying the corresponding time; A time delay PWM generator operating after the ENABLE signal; And a three state buffer (3 state buffer) for determining whether to output a signal generated by the time delay PWM generator (54). The method of claim 2, wherein the time delay PWM generator A pulse width latch (Latch 110) unit in which data for determining a pulse width is stored; a frequency latch (120) unit for storing data for determining a frequency of a PWM to be generated; these two data A counter 130 which is a target to be compared and is operated by a supplied clock clock and an enable signal supplied from a time delay unit 55; and data of a pulse width latch 110; Comparator 2 150 that compares the data of the counter 130 to determine the pulse width; compares the data of the frequency latch 120 with the data of the counter 130 Comparator 1 (140) for determining the frequency; Multi-channel frequency, characterized in that it comprises a flip-flop (160) for generating a pulse with a signal output from each of the comparator (140, 150) and Math waveform generator. The method of claim 2, wherein the time delay unit A counter 220 that counters the clock from the outside; A latch in which data of a counter 220 and a PWM delay time are stored; A comparator 3 240 which outputs an output when the data of the latch 210 is the same; Multi-channel frequency characterized in that it comprises a flip-flop (230) for generating a signal to delay the PWM pulse (PULSE) as a signal output from the comparator (240) and the desired time and Math waveform generator. A method of connecting an oscillator (OSC) and a microprocessor address bus (ADDRESSBUS) and a data bus in parallel with each function generator configured to enable simultaneous output of different frequencies or different waveforms on a plurality of channels, respectively, A multi-channel frequency and function waveform generator including a method of synthesizing the output of an individual pulse unit having a frequency or waveform of a new frequency or a new waveform.
KR1020070061947A 2007-06-25 2007-06-25 Multi channel frequency and function generator KR20080113459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070061947A KR20080113459A (en) 2007-06-25 2007-06-25 Multi channel frequency and function generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070061947A KR20080113459A (en) 2007-06-25 2007-06-25 Multi channel frequency and function generator

Publications (1)

Publication Number Publication Date
KR20080113459A true KR20080113459A (en) 2008-12-31

Family

ID=40370703

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070061947A KR20080113459A (en) 2007-06-25 2007-06-25 Multi channel frequency and function generator

Country Status (1)

Country Link
KR (1) KR20080113459A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022114446A1 (en) * 2020-11-30 2022-06-02 이승준 Multi-wave generation system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022114446A1 (en) * 2020-11-30 2022-06-02 이승준 Multi-wave generation system

Similar Documents

Publication Publication Date Title
JP4423454B2 (en) Signal generator
JP5714010B2 (en) Sub-beam forming transmitter circuit for ultrasound systems
JP4649480B2 (en) Test apparatus, clock generator, and electronic device
US7015685B2 (en) Semiconductor tester
JP5015793B2 (en) Digital frequency synthesizer and method for generating a frequency sweep
JP5343966B2 (en) Clock signal divider circuit and method
JPH07169265A (en) Synchronous random-access memory device
KR20080113459A (en) Multi channel frequency and function generator
KR20080006140U (en) Multi Frequency Generator
US8963527B2 (en) EMI mitigation of power converters by modulation of switch control signals
DE60128696D1 (en) FREQUENCY SYNTHESIZER
US4154132A (en) Rhythm pattern variation device
WO2010021131A1 (en) Test device and testing method
US20120306539A1 (en) Fractional-n clock generator and method thereof
US5870593A (en) Method and programmable device for generating variable width pulse trains
JP2010193338A (en) Optional waveform generator, and semiconductor tester using the same
US20130311816A1 (en) Circuit and method for controllably delaying an input signal, and microscope, and method for controlling a microscope
KR0166163B1 (en) Pulse width modulating wave generation circuit
JP2004021204A (en) Musical sound formation circuit
KR20050100457A (en) Apparatus and method of sdram clock generation in low frequency
JP2004012175A (en) Evaluation method for circuit with built-in pll, evaluation system for circuit with built-in pll, and circuit with built-in pll
JP2003015761A (en) Clock generating circuit
JPH11102231A (en) Device and method for generating timing
JP2001272443A (en) Semiconductor testing device and semiconductor testing method using the device
KR19990070523A (en) Clock generator

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E601 Decision to refuse application