KR20080104726A - Gate driving circuit and display device having the same - Google Patents

Abstract

A gate driving circuit and a display device are provided to reduce a ripple voltage of a first node connected to a source electrode of a ninth transistor by increasing a first parasitic capacitance between a gate electrode and the source electrode of the ninth transistor. A plurality of stages are composed of subordinately connected shift registers. A pull up unit(210) receives a first clock signal, and outputs a first clock signal to a gate signal by responding to a signal of a first node which is converted to a high level by a first input signal. A pull down unit(220) discharges a gate signal to the off voltage in response to a second input signal. A discharging unit(230) discharges the signal of the first node to the off voltage in response to a second input signal. A first holding unit(242) maintains the signal of the first node as the gate signal discharged to the off voltage in response to the first clock signal. A second holding unit(244) has parasitic capacitance of an asymmetric structure and includes a transistor maintaining the signal of the first node as the off voltage of the first input signal in response to the second clock signal.

Description

GATE DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE SAME

1 is a schematic plan view of a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram of the gate driving circuit shown in FIG. 1.

3 is a detailed circuit diagram of the stage shown in FIG.

4 is a signal waveform diagram of the stage shown in FIG.

5A and 5B are schematic views of the ninth transistor shown in FIG. 3.

FIG. 6 is a simulation waveform diagram of the ripple voltage of the first node shown in FIG. 3.

7 is a graph illustrating frequency characteristics of a gate driving circuit during long term driving.

<Description of the symbols for the main parts of the drawings>

IN1: first input terminal IN2: second input terminal

CK1: first clock terminal CK2: second clock terminal

VSS: Voltage terminal RE: Voltage terminal

CR: carry terminal OUT: output terminal

210: pull-up part 220: pull-down part

230: discharge unit 242: first holding unit

244: second holding part 246: third holding part

248: fourth holding unit 250: switching unit

260: reset unit 270: charging unit

280: buffer portion 290: carry portion

The present invention relates to a gate driving circuit and a display device including the same, and more particularly, to a gate driving circuit for improving the reliability of the product and a display device including the same.

BACKGROUND ART In general, a liquid crystal display device is a display device that obtains a desired image signal by applying an electric field to a liquid crystal having an anisotropic dielectric constant injected between an array substrate and an opposing substrate, and adjusting the light transmittance according to the intensity of the electric field.

The liquid crystal display includes a display panel in which a plurality of pixel portions are formed by gate lines and data lines crossing the gate lines, data for outputting a data signal to a gate driver and data lines for outputting a gate signal to the gate lines. It includes a drive unit. In general, the gate driver and the data driver have a chip shape and are mounted on a display panel.

Recently, in order to increase productivity while reducing the overall size, a method of integrating the gate driver on the display substrate in the form of an integrated circuit has been attracting attention. As such, the gate driving circuit integrated in the form of an integrated circuit in the display panel has a problem in that a noise defect in which an abnormal gate on signal appears in a gate off signal section occurs when driving at a high temperature.

Specifically, the coupling with the clock signal by the parasitic capacitance Cgd of the pull-up element increases the off voltage of the gate electrode, and at the same time, the leakage current increases as the temperature increases to turn on the pull-up element. As a result, the gate-on signal is intermittently generated in the gate-off signal section, thereby causing a problem of poor image quality.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a gate driving circuit for improving driving reliability.

Another object of the present invention is to provide a display device including the gate driving circuit.

The gate driving circuit according to the embodiment for realizing the object of the present invention is composed of a shift register coupled to a plurality of stages, the m-th stage is a pull-up, pull-down, discharge, first holding and It includes two holding parts. The pull-up unit receives a first clock signal and outputs the first clock signal as a gate signal in response to a signal of a first node that is switched to a high level by the first input signal. The pull-down part discharges the gate signal to an off voltage in response to a second input signal. The discharge unit discharges the signal of the first node to the off voltage in response to the second input signal. The first holding part maintains the signal of the first node as the gate signal discharged to an off voltage in response to the first clock signal. The second holding part has a parasitic capacitance having an asymmetric structure, and includes a transistor configured to maintain a signal of the first node at an off voltage of a first input signal in response to a second clock signal.

According to another exemplary embodiment of the present invention, a display device includes a display panel, a data driver, and a gate driver. The display panel includes a display area in which a plurality of pixel parts are formed by gate lines and data lines crossing the gate lines, and a peripheral area surrounding the display area. The data driver outputs a data signal to the data lines. The gate driving circuit is composed of a plurality of stages connected in a cascade and is directly formed in the peripheral area to output gate signals to the gate lines, and the mth stage includes a pull-up part, a pull-down part, a discharge part, a first holding part, And a second holding part. The second holding part has a parasitic capacitance having an asymmetric structure, and includes a transistor configured to maintain a signal of the first node at an off voltage of a first input signal in response to a second clock signal.

According to the gate driving circuit and the display device having the same, the ripple generated in the control electrode of the pull-up part can be reduced to prevent abnormal generation of the gate-on signal in the gate-off signal period, and the driving reliability can be improved when used for a long time.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a schematic plan view of a display device according to an exemplary embodiment of the present invention. FIG. 2 is a block diagram of the gate driving circuit shown in FIG. 1.

1 and 2, the display device includes a display panel 100, a gate driving circuit 200 for driving the display panel 100, and a data driver 130.

The display panel 100 includes an array substrate and an opposing substrate (eg, a color filter substrate) facing each other at a predetermined interval, and a liquid crystal layer interposed between the array substrate and the opposing substrate, and includes a display area DA and a display area DA. ) Is made up of a peripheral area PA. In the display area DA, a plurality of pixel parts are formed by the gate lines GL formed in one direction and the data lines DL formed in a direction crossing the gate lines GL to display an image.

Each pixel unit includes a thin film transistor TFT as a switching element, a liquid crystal capacitor CLC, and a storage capacitor CST electrically connected to the thin film transistor TFT. In detail, the gate electrode and the source electrode of the thin film transistor TFT are electrically connected to the gate line GL and the data line DL, respectively, and the liquid crystal capacitor CLC and the storage capacitor CST are electrically connected to the drain electrode. do.

The peripheral area PA includes a first peripheral area PA1 positioned at one end of the data lines DL and a second peripheral area PA2 positioned at one end of the gate lines GL.

The data driver 130 outputs a data signal to the data lines DL in synchronization with the gate signal applied to the gate line GL and includes at least one data driving chip 132. The data driving chip 132 is mounted on the flexible circuit board 134 having one end connected to the first peripheral area PA1 of the display panel 100 and the other end connected to the printed circuit board 140. The substrate 134 may be electrically connected to the printed circuit board 134 and the display panel 100.

The gate driving circuit 200 includes a shift register in which a plurality of stages are cascaded, and sequentially outputs gate signals to the gate lines GL. The gate driving circuit 200 may be formed in the form of an integrated circuit integrated in the second peripheral area PA2 of the display panel 100. In the case of the gate driving circuit 200 formed on the display panel 100 in the form of an integrated circuit, Mo / Al / Mo (molybdenum / aluminum / molybdenum 3-layer metal), which is a low resistance metal, is used to improve driving margin. It is desirable to.

Referring to FIG. 2, the shift register includes first to n + 1th stages SRC1 to SRCn + 1 connected to each other dependently.

The first to nth + 1 stages SRC1 to SRCn + 1 are the first to nth stages SRC1 to SRCn that output n gate signals and the first to nth + 1 stages SRC1 to SRCn + 1. ), The n + 1th stage SRCn + 1 outputs a reset signal. In order to minimize noise that may be included in the output of the n th stage SCRn during the porch period, the n th +2 th stage SRCn + 2 may be further included.

Each of the first to n + 1th stages SRC1 to SRCn + 1 includes a first clock terminal CK1, a second clock terminal CK2, a first input terminal IN1, a second input terminal IN2, And a voltage terminal VSS, a reset terminal RE, a carry terminal CR, and an output terminal OUT.

The first clock signal CK and the second clock signal CKB having opposite phases are provided to the first clock terminal CK1 and the second clock terminal CK2. Specifically, the first clock signal CK is provided to the first clock terminal CK1 of the odd-numbered stages SRC1, SRC3,..., SRCn + 1, and the second clock terminal CK2 is provided to the first clock signal CK1. The second clock signal CKB is provided. The second clock signal CKB is provided to the first clock terminal CK1 of even-numbered stages SRC2, SRC4, ..., SRCn, and the first clock signal is provided to the second clock terminal CK2. (CK) is provided.

The first input terminal IN1 is provided with a vertical start signal STV or a carry signal of a previous stage. That is, a vertical start signal STV is provided to the first input terminal IN1 of the first stage SRC1, which is the first stage, and the second to n + 1 stages SRC2 to SRCn + 1 are provided. One input terminal IN1 is provided with a carry signal of the previous stages SRC1 to SRCn, respectively.

The second input terminal IN2 is provided with a gate signal or a vertical start signal STV of a next stage. Gate signals of the next stages SRC2 to SRCn + 1 are respectively provided to the second input terminals IN2 of the first to nth stages SRC1 to SRCn, and the n + 1th stage SRCn + 1 is provided. The vertical start signal STV is provided to the second input terminal IN2.

An off voltage VOFF is provided to the voltage terminal VSS, and a carry signal of the n + 1th stage SRCn + 1 is provided as a reset signal to the reset terminal RE.

The output terminal OUT outputs a gate signal to an electrically connected gate line. The odd-numbered gate signal output from the output terminal OUT of the odd-numbered stages SRC1, SRC3,..., SRCn + 1 is output in a high section of the first clock signal CK. The even-numbered gate signal output from the output terminal OUT of the even-numbered stages SRC2, SRC4,..., SRCn is output in the high period of the second clock signal CKB. Therefore, the first to n + 1th stages SRC1 to SRCn + 1 sequentially output gate signals G1,..., Gn.

3 is a detailed circuit diagram of the stage shown in FIG. 4 is a signal waveform diagram of the stage shown in FIG.

3 and 4, the m-th stage SRCm pulls the m-th gate signal Gm into the first clock signal CK in response to a carry signal of the m-th stage SRCm-1. The off voltage VOFF is applied to the pull-up unit 210 that pulls up the gate signal Gm + 1 in response to the gate signal Gm + 1 of the m + 1th stage SRCm + 1. It includes a pull-down unit 220 to pull down.

The pull-up unit 210 includes a fifth transistor T5 having a gate electrode connected to the first node N1, a drain electrode connected to the first clock terminal CK1, and a source electrode connected to the output terminal OUT. It includes. Therefore, the drain electrode of the fifth transistor T5 receives the first clock signal CK through the first clock terminal CK1.

The pull-down unit 220 has a gate electrode connected to a second input terminal IN2, a drain electrode connected to an output terminal OUT, a source electrode connected to a voltage terminal VSS, and the off voltage VOFF. This includes the sixth transistor T6 provided.

The m-th stage SRCm turns on the pull-up unit 210 in response to a carry signal of the m-th stage SRCm-1, and the gate signal of the m + 1th stage SRCm + 1. And a pull-up driving unit which turns off the pull-up unit 210 in response to Gm + 1). The pull-up driving unit includes a buffer unit 280, a charging unit 270, and a discharge unit 230.

The buffer unit 280 includes a thirteenth transistor T13 having a gate electrode and a drain electrode commonly connected to the first input terminal IN1, and a source electrode connected to the first node N1.

The charging unit 270 includes a third capacitor C3 having a first electrode connected to the first node N1 and a second electrode connected to the output terminal OUT. The discharge unit 230 has a gate electrode connected to the second input terminal IN2, a drain electrode connected to the first node N1, and a source electrode connected to the voltage terminal VSS, so that the off voltage VOFF is applied. ) Is provided with a seventh transistor T7.

When the thirteenth transistor T13 is turned on in response to a carry signal of the m-th stage SRCm-1, the pull-up driver is applied to the first node N1 to apply the first signal to the first node N1. The node N1 is switched to the high level and at the same time the third capacitor C3 is charged. Subsequently, when the charge above the threshold voltage of the fifth transistor T5 is charged in the third capacitor C3 and the first clock signal CK becomes a high period, the fifth transistor T5 bootstrap. The first clock signal CK of the high level is output to the output terminal OUT. The fifth transistor T5 is bootstraped to output an mth gate signal Gm, which is an output signal of the mth stage SRCm.

Subsequently, when the seventh transistor T7 is turned on in response to the m + 1th gate signal Gm + 1, the charge charged in the third capacitor C3 is turned off of the voltage terminal VSS. The fifth transistor T5 is turned off by being discharged to VOFF.

The m-th stage SRCm may include a first holding part for maintaining a signal of the first node N1, that is, a signal applied to a control terminal of the pull-up part 210 at a level of the off voltage VOFF. 242 and the second holding part 244 is further included.

The first holding part 242 has a gate electrode connected to the first clock terminal CK1, a drain electrode connected to the first node N1, and a source electrode connected to the output terminal OUT. 8 transistor T8. The second holding part 244 has a gate electrode connected to the second clock terminal CK2, a drain electrode connected to the first input terminal IN1, and a source electrode connected to the first node N1. And a ninth transistor T9 connected thereto.

The ninth transistor has an asymmetrical design of the first parasitic capacitance Cgs between the gate electrode and the source electrode and the second parasitic capacitance Cgd between the gate electrode and the drain electrode. That is, the first parasitic capacitance Cgs is formed larger than the second parasitic capacitance Cgd. Accordingly, when the second clock signal CKB input to the gate electrode of the ninth transistor T9 is falling, the first parasitic capacitance Cgs is larger than the second parasitic capacitance Cgd. The ripple component of the first node N1 connected to the source electrode is suppressed. As the first parasitic capacitance Cgs is increased, the ripple suppression effect is also improved. This will be described in detail with reference to FIGS. 5A and 5B.

The first holding part 242 and the second holding part 244 have the first node after the m-th gate signal Gm is shifted to the level of the off voltage VOFF by the pull-down part 220. The signal of N1) is maintained at the level of the off voltage VOFF.

That is, when the eighth transistor T8 is turned on in response to the first clock signal CK, the m-th gate signal Gm discharged to the level of the off voltage VOFF becomes the first node ( N1) is applied to maintain the first node N1 at the level of the off voltage VOFF. In addition, when the ninth transistor T9 is turned on in response to the second clock signal CKB, the first input signal having an off voltage (VOFF) state is applied to the first node N1 to provide the first input signal. One node N1 is maintained at the level of the off voltage VOFF.

As described above, the first holding part 242 and the second holding part 244 are alternately turned on in response to a first clock signal CK and a second clock signal CKB, respectively, so that the first node is turned on. The signal of N1 is maintained at the level of the off voltage VOFF.

The m-th stage SRCm is the first clock signal CK and the second clock signal CKB after the third node N3 is switched to the off voltage VOFF level by the pull-down unit 220 after the gate signal is output. The third holding part 246 and the fourth holding part 248 to maintain the off voltage VOFF level stably before the gate signal output of the next frame irrespective of external noise such as the And a switching unit 250 that controls the on / off operation of the fourth holding unit 248.

The third holding part 246 has a gate electrode connected to the second clock terminal CK2, a drain electrode connected to the output terminal OUT, a source electrode connected to the voltage terminal VSS, and the off voltage ( And a tenth transistor T10 provided with VOFF). The fourth holding part 248 has a gate electrode connected to the second node N2 of the switching part 250, a drain electrode connected to an output terminal OUT, and a source electrode connected to the voltage terminal VSS. And an eleventh transistor T11 connected to receive an off voltage VOFF.

The switching unit 250 includes first to fourth transistors T1, T2, T3, and T4, and first and second capacitors C1 and C2.

The gate electrode and the drain electrode of the first transistor T1 are commonly connected to the first clock terminal CK1 to receive the first clock signal CK, and the source electrode of the drain of the second transistor T2. Connected with the electrode. The gate electrode of the second transistor T2 is connected to the output terminal OUT, and the source electrode is connected to the voltage terminal V to receive the off voltage VOFF. The drain electrode of the third transistor T3 is connected to the first clock terminal CK1, the gate electrode is connected to the first clock terminal CK1 through the first capacitor C1, and the source electrode is It is connected to the second node N2.

Accordingly, the drain electrode and the gate electrode of the third transistor T3 receive the first clock signal CK, and the second capacitor C2 is disposed between the gate electrode and the source electrode of the third transistor T3. Connected. The fourth transistor T4 has a gate electrode connected to an output terminal OUT, a drain electrode connected to a second node N2, a source electrode connected to a voltage terminal VSS, and the off voltage VOFF. To be provided.

When the m-th stage SRCm outputs the first clock signal CK as the gate signal Gm having a high level, the second and fourth transistors T2 as the output terminal OUT is switched to the high level. , T4 is turned on, and thus the off voltage VOFF is applied to the second node N2. In this case, since the first clock signal CK is in a high state, the first and third transistors T1 and T3 also maintain a turn-on state, and thus the first clock signal CK having a high level at the second node N2. ) Is also applied to the gate electrode of the eleventh transistor T11 strictly in proportion to the resistance ratio of the third transistor T3 and the fourth transistor T4 and the voltage level of the first clock signal CK and the off. The divided voltage between the voltage VOFF voltage levels is applied. In this case, when the division voltage is designed to be less than or equal to the threshold voltage of the eleventh transistor, the eleventh transistor may maintain a turn-off state, and thus, the third node N3 may maintain a high level state.

When 1H elapses and the high level m + 1 gate signal Gm + 1 is input to the second input terminal IN2, the sixth transistor is turned on so that the third node N3 may turn off the voltage. VOFF), and the second and fourth transistors T2 and T4 are turned off. At the same time, since the second clock signal CK2 becomes high, the tenth transistor T10 is turned on so that the third node N3 reaches the off voltage VOFF more quickly.

The second clock signal CKB and the first clock signal CK are alternately responded to a period other than a period of outputting the m-th gate signal and the m-th gate signal during one frame period. The third node N3 maintains the off voltage VOFF stably without noise by the third holding part 246 and the fourth holding part 248.

That is, the second and fourth transistors T2 and T4 are turned off as the mth gate signal GOUTm is discharged to the off voltage VOFF in response to the m + 1th gate signal GOUTm + 1. After the switching, when the first clock signal CK is switched to the high level until the m-th gate signal GOUTm of the next frame is output, the voltages output from the first and third transistors T1 and T3 are changed. As the potential of the second node N2 is switched to the high level and the potential of the second node N2 is switched to the high level, the eleventh transistor T11 is turned on and the turned-on eleventh transistor T11 is turned on. ), The potential of the output terminal OUT is discharged more quickly to the off voltage (VOFF).

Thereafter, when the first clock signal CK is switched to the low level, the potential of the second node N2 is also switched to the low level so that the eleventh transistor T11 is turned off. On the other hand, the tenth transistor T10 is turned on by the second clock signal CKB having a phase opposite to that of the first clock signal CK to discharge the potential of the output terminal OUT to the off voltage VOFF. .

As such, the third holding part 246 and the fourth holding part 248 alternately change the potential of the output terminal OUT in response to the second clock signal CKB and the first clock signal CK, respectively. VOFF).

The m-th stage of the gate driving circuit 200 further includes a reset unit 260 and a carry unit 290. The reset unit 260 has a gate electrode connected to the reset terminal RE, a drain electrode connected to the first node N1, and a source electrode connected to the voltage terminal VSS. The twelfth transistor T12 provides the off voltage VOFF to N1. The reset unit 160 receives the carry signal of the last stage n + 1 stage (SRCn + 1) and, after completion of one frame, sets the first node N1 of all stages to the off voltage VOFF. Reset it. Since the third node N3 of the N + 1th stage SRCn + 1 is not reset until the vertical start signal STV of the next frame is input, the third node N3 turns off the first node N1 during the blank period. It can be kept stable with (VOFF).

The carry unit 290 has a gate electrode connected to the first node N1, a drain electrode connected to the first clock terminal CK1 to receive the first clock signal CK, and a source electrode The fourteenth transistor T14 is connected to the carry terminal CR. The carry unit 290 outputs a high section of the first clock signal CK to the carry terminal CR as the potential of the first node N1 is changed to a high level.

In this example, the carry signal output from the carry unit 290 is provided to the first input terminal IN1 of the next stage to control the start of the operation. However, the carry unit 290 is removed and the output terminal OUT is removed. The gate signal output from the signal may be provided to the first input terminal IN1 of the next stage. However, in the case of XGA or higher resolution panel or large panel, the load on the gate line is relatively larger than that of the low resolution model or the small panel. Therefore, when using the gate signal as a carry signal, the lower part of the panel may not be driven due to signal delay. Since it may occur, it is preferable to have a separate carry part 290 as in the present embodiment.

5A and 5B are schematic views of the ninth transistor shown in FIG. 3.

Referring to FIG. 5A, the channel shape of the ninth transistor 110 according to the exemplary embodiment has an I shape. Specifically, the ninth transistor 110 includes a channel layer 113 formed on the gate electrode 111, a plurality of source electrodes 115 and a plurality of drain electrodes 117 formed on the channel layer 113. It includes.

Each of the source electrode 115 and the drain electrode 117 is formed in an I shape and spaced apart from each other by a predetermined interval. Accordingly, the channel defined by the source electrode 135 and the drain electrode 137 has an I shape, and has a channel length L and a channel width W.

In the ninth transistor 110, the width s of the source electrode 115 is designed to be larger than the width d of the drain electrode 117. Accordingly, the first parasitic capacitance Cgs between the gate electrode 111 and the source electrode 115 is larger than the second parasitic capacitance Cgd between the gate electrode 111 and the drain electrode 117.

Referring to FIG. 5B, the channel of the ninth transistor 130 according to another embodiment has a U shape. Specifically, the ninth transistor 130 may include a channel layer 133 formed on the gate electrode 131, a plurality of source electrodes 135 and a plurality of drain electrodes 137 formed on the channel layer 133. Include.

Each of the source electrodes 135 is formed in a U shape, and each of the drain electrodes 137 is inserted into the U-shaped source electrode 135 at a predetermined interval. Accordingly, the channel defined by the source electrode 135 and the drain electrode 137 has a U shape, and has a channel length L and a channel width W.

The ninth transistor 130 is designed such that the width s of the source electrode 135 is larger than the width d of the drain electrode 137. Accordingly, the first parasitic capacitance Cgs between the gate electrode 131 and the source electrode 135 is larger than the second parasitic capacitance Cgd between the gate electrode 131 and the drain electrode 137.

As shown in FIGS. 5A and 5B, a first node electrically connected to a source terminal of the ninth transistors 110 and 130 by forming the first parasitic capacitance Cgs larger than the second parasitic capacitance Cgd. The ripple component which arises in (N1) can be suppressed. Preferably, the ratio of the first parasitic dose Cgs to the second parasitic dose Csd is K: 1 (K> 1), for example 2: 1, 3: 1 or 4: 1.

FIG. 6 is a simulation waveform diagram of the ripple voltage of the first node shown in FIG. 3.

6, the channel width W of the fifth transistor T5 illustrated in FIG. 3 is 3500 μm, the channel width W of the ninth transistor T9 is 400 μm, and the fifth and ninth transistors ( The channel lengths L of T5 and T9 represent the ripple voltages of the first node N1 measured at room temperature when the channel length L is about 5 μm to 6 μm.

Referring to FIG. 6, a first ripple voltage waveform diagram R1 is measured at the first node N1 when the ratio of the first parasitic capacitance Cgs and the second parasitic capacitance Cgd is 1: 1. The ripple voltage, and the second ripple voltage waveform R2 is the ripple measured at the first node N1 when the ratio of the first parasitic capacitance Cgs and the second parasitic capacitance Cgd is 2: 1. Voltage. The first and second parasitic capacitances Cgs and Cgd are parasitic capacitances of the ninth transistor T9.

Referring to the first ripple voltage waveform R1, when the ratio of the first and second parasitic capacitances Cgs and Cgd is 1: 1, the gate electrode and the source electrode of the fifth transistor T5 of FIG. The voltage Vgs of the liver, that is, the first node N1, increased to 1.41 [V]. On the other hand, referring to the second ripple voltage waveform R2, when the ratio of the first and second parasitic capacitances Cgs and Cgd is 2: 1, the gate electrode and the source electrode of the fifth transistor T5 are disposed. The voltage Vgs, that is, the first node N1, rose to 1.29 [V]. The peak of the second ripple voltage was reduced by about 0.12 [V] than the peak of the first ripple voltage.

As a result, when the ratio of the first and second parasitic capacitances Cgs and Cgd is 2: 1, it was confirmed that the peak of the ripple voltage occurring at the first node N1 is small.

Meanwhile, Table 1 below shows long-term evaluation data for 3000 hours for the transistors shown in FIG. 3.

Referring to [Table 1], the ninth, tenth, and eighteenth transistors T9, T10, and T18 to which the clock signals CK / CKB are continuously applied are deteriorated by the gate bias stress, and thus the threshold voltage Vth. This shifted much compared to other relatively transistors, which degraded the current driving capability.

That is, when the channel width W of the transistor increases, the effect of inhibiting the driving capability of the fifth transistor T5 is large.

In consideration of the driving characteristics of the ninth transistor T9, in the embodiment of the present invention, the ratio of the first and second parasitic capacitances Cgs and Cgd of the ninth transistor T9 is increased but the ninth transistor T9 is increased. The channel width of the thirteenth transistor T13 having a small variation in the gate voltage Vth during long-term driving is increased to compensate for the lack of charge of the fifth transistor T5. It was designed to ensure a sufficient charge amount of the transistor T5.

The thirteenth transistor T13 charges the third capacitor C3 connected to the first node N1 in a turn-on state similarly to the ninth transistor T9. Accordingly, the channel width of the thirteenth transistor T13 may be increased to sufficiently secure the amount of charge of the fifth transistor T5 to improve driving reliability during long-term driving.

In general, the channel width of the thirteenth transistor T13 is approximately 1200 μm. Accordingly, the channel width of the thirteenth transistor T13 is designed to be larger than 1200 μm within an allowable area of formation.

Preferably a channel width of the ninth transistor is increased by a variation (△ W _T9) when reduced by, In response, the channel width of the thirteenth transistor (T13) variation (△ W _T9).

The variation ΔW _T9 is defined as in Equation 1 below. In this case, when the ratio between the first and second parasitic capacitances Cgs and Cgd of the ninth transistor _T9 is 1: 1 symmetrical, the channel width of the ninth transistor is W _T9 and the symmetric ninth transistor T9 is used. The first parasitic dose (Cgs) of) is reduced without changing the second parasitic dose (Cgd) to change the ratio of the first and second parasitic doses (Cgs, Cgd) to K: 1 (K> 1) asymmetry. depending defined as the variation of the ninth transistor _T9 △ W a channel width of (T9), down from W _T9.

For example, when the channel width W _T9 of the symmetric ninth transistor _T9 is 900 μm, the ratio of the first and second parasitic capacitances Cgs and Cgd is 900 μm, according to an embodiment of the present invention. Instead of increasing the channel width of T9, the ratio of the first and second parasitic capacitances of the ninth transistor T9 is designed to be Cgs: Cgd = 3: 1 to reduce the ripple component of the first node N1. Can be. In this case, the channel width of the thirteenth transistor T13 is increased by 600 μm in response to the variation (ΔW _T9 = 900 μm x (1-1 / 3) = 600 μm) in order to improve long-term driving characteristics. .

The range of the variation ΔW _T9 is preferably the ninth transistor described in Korean Patent Application No. 2006-0055654 filed by the same applicant, name "Gate driving circuit and display device having the same". In accordance with the formula for calculating the channel width (W _T8 <W _T9 <(W _T8 + W _T14 )) is defined as shown in Equation 2 below.

Here, W _T8 is the channel width of the eighth transistor T8, and W _T14 is the channel width of the fourteenth transistor T14.

7 is a graph illustrating frequency characteristics of a gate driving circuit during long term driving.

Referring to FIG. 7, the condition of Comparative Example (A) is that the capacitance ratio of the first and second parasitic capacitances Cgs and Cgd of the ninth transistor T9 is 1: 2 or 1: 3, and the thirteenth transistor T13 is used. ) Is designed to have the same channel width of 1200㎛. The condition of the embodiment (B) is that the capacitance ratio of the first and second parasitic capacitances Cgs and Cgd of the ninth transistor T9 is 1: 2 or 1: 3 and the channel width of the thirteenth transistor T13 is 1600. This is a case where the design is extended to a micrometer.

As shown, in the case of Comparative Example (A), the driving frequency is initially driven at 130 Hz, but is significantly reduced by about 20 Hz when used for a long time (more than 2000 hours). On the other hand, in the case of the embodiment (B), the driving frequency is initially driven at 130 Hz, but decreased by about 10 Hz when used for a long time (more than 2000 hours). In Example (B) it can be seen that the reduction of the driving frequency is less when used for a longer time than the comparative example (A).

As a result, by increasing the channel width of the thirteenth transistor to sufficiently increase the charging amount of the control terminal N1 for driving the pull-up unit, driving reliability may be improved during long-term driving.

As described above, according to the present invention, the ripple voltage of the first node connected to the source electrode of the ninth transistor can be reduced by increasing the first parasitic capacitance between the gate electrode and the source electrode of the ninth transistor.

In addition, by increasing the channel width of the thirteenth transistor which charges the capacitor connected to the first node, a sufficient amount of charge may be charged in the capacitor. Accordingly, it is possible to improve driving reliability in long-term use of the gate driving circuit which bootstraps according to the amount of charge charged in the capacitor and outputs the gate signal.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (16)

A plurality of stages are composed of shift registers that are cascaded The m stage A pull-up unit configured to receive a first clock signal and output the first clock signal as a gate signal in response to a signal of a first node switched to a high level by the first input signal; A pull-down part configured to discharge the gate signal to an off voltage in response to a second input signal; A discharge unit configured to discharge the signal of the first node to the off voltage in response to the second input signal; A first holding part maintaining the signal of the first node as the gate signal discharged to an off voltage in response to the first clock signal; And And a second holding part having a parasitic capacitance having an asymmetric structure and including a transistor configured to maintain a signal of the first node at an off voltage of a first input signal in response to a second clock signal. The transistor of claim 1, wherein the transistor of the second holding part comprises a gate electrode to which the second clock signal is input, a drain electrode to which the first input signal is input, and a source electrode connected to the first node, And a first parasitic capacitance between the gate electrode and the source electrode is greater than a second parasitic capacitance between the gate electrode and the drain electrode. The method of claim 1, wherein the first input signal is a vertical start signal or a gate signal of an m-th stage. And the second input signal is a gate signal or a vertical start signal of an m + 1th stage. The gate driving circuit of claim 2, further comprising a buffer unit connected to the first node and including a transistor configured to charge a high level of the first input signal to the first node. The gate driving circuit of claim 4, wherein the transistor width of the buffer unit is increased by ΔW _T in the following equation;

(W _T8 is a transistor channel width of the first holding portion, and the ratio of the first parasitic capacitance Cgs and the second parasitic capacitance Cgd of the transistor of the second holding portion is Cgs: Cgd = K: 1, (K> 1). The gate driving circuit of claim 4, further comprising a carry part configured to output the first clock signal as a carry signal in response to a signal of the first node. The gate driving circuit of claim 6, wherein the transistor channel width of the buffer unit is increased by ΔW _T in the following equation;

(W _T8 is the transistor channel width of the first holding part, W _T14 is the transistor channel width of the carry part, and the ratio of the first parasitic capacitance Cgs and the second parasitic capacitance Cgd is Cgs: Cgd = K: 1, (K> 1). The method of claim 7, wherein the first input signal is a vertical start signal or a carry signal of the m-th stage. And the second input signal is a gate signal or a vertical start signal of an m + 1th stage. A display panel including a display area in which a plurality of pixel portions are formed by gate lines and data lines crossing the gate lines, and a peripheral area surrounding the display area; A data driver which outputs a data signal to the data lines; And It is composed of a plurality of stages connected in a cascade form directly in the peripheral area to output the gate signals to the gate wirings, The m stage A pull-up unit configured to receive a first clock signal and output the first clock signal as a gate signal in response to a signal of a first node switched to a high level by the first input signal; A pull-down part configured to discharge the gate signal to an off voltage in response to a second input signal; A discharge unit configured to discharge the signal of the first node to the off voltage in response to the second input signal; A first holding part maintaining the signal of the first node as the gate signal discharged to an off voltage in response to the first clock signal; And A display device including a gate driving circuit having a parasitic capacitance having an asymmetric structure, and including a second holding part including a transistor configured to maintain a signal of the first node at an off voltage of a first input signal in response to a second clock signal. . The transistor of claim 9, wherein the transistor of the second holding part comprises a gate electrode to which the second clock signal is input, a drain electrode to which the first input signal is input, and a source electrode connected to the first node, And a first parasitic capacitance between the gate electrode and the source electrode is greater than a second parasitic capacitance between the gate electrode and the drain electrode. 10. The method of claim 9, wherein the first input signal is a vertical start signal or a gate signal of an m-th stage. And the second input signal is a gate signal or a vertical start signal of an m + 1th stage. The display device of claim 10, further comprising a buffer unit connected to the first node and including a transistor configured to charge a high level of the first input signal to the first node. The display device of claim 12, wherein the width of the transistor of the buffer unit is increased by ΔW _T in the following equation;

(W _T8 is a transistor channel width of the first holding portion, and the ratio of the first parasitic capacitance Cgs and the second parasitic capacitance Cgd of the transistor of the second holding portion is Cgs: Cgd = K: 1, (K> 1). The display device of claim 12, further comprising a carry part configured to output the first clock signal as a carry signal in response to a signal of the first node. The display device of claim 14, wherein the width of the transistor channel of the buffer unit is increased by ΔW _T in the following equation;

(W _T8 is the transistor channel width of the first holding part, W _T14 is the transistor channel width of the carry part, and the ratio of the first parasitic capacitance Cgs and the second parasitic capacitance Cgd is Cgs: Cgd = K: 1, (K> 1). The method of claim 15, wherein the first input signal is a vertical start signal or a carry signal of an m-th stage. And the second input signal is a gate signal or a vertical start signal of an m + 1th stage.

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