KR20080100637A - Thin film transistor array and fabrcating method thereof - Google Patents

Abstract

A TFT array and a method for manufacturing the same are provided to reduce the number of vacuum deposition processes and manufacturing cost. A first gate insulating pattern(45a) defines the aperture hole which is formed on the substrate and exposes substrate. A gate conductive pattern on the aperture hole is defines by the first gate insulating pattern. Second gate insulating pattern(45b) are formed on the gate conductive pattern and the first gate insulating pattern, and includes a groove. A semiconductor pattern(46) and the source/drain conductive pattern are filled in the groove of the second gate oxide. Protection pattern(47) defines the aperture hole which is formed on the second gate insulating pattern and exposes the second gate insulating pattern.

Description

Thin film transistor array and its manufacturing method {Thin Film Transistor Array and Fabrcating method

1 is a perspective view schematically showing a liquid crystal display panel.

2 shows a cross section of a thin film transistor array;

3 is a plan view illustrating a thin film transistor array according to an exemplary embodiment of the present invention.

FIG. 4 is a cross-sectional view of the thin film transistor array taken along the line "I-I '", the line "II-II'", and the line "III-III '" in FIG.

5A is a plan view illustrating a gate conductive pattern in accordance with an embodiment of the present invention.

FIG. 5B is a cross-sectional view of the gate conductive pattern taken along the line "I-I '", the line "II-II'", and the line "III-III '" in FIG. 5A;

6A through 6D are cross-sectional views illustrating the process of forming the gate conductive pattern shown in FIGS. 5A and 5B.

7A is a plan view illustrating a gate conductive pattern, a semiconductor pattern, and a source / drain conductive pattern according to an embodiment of the present invention.

FIG. 7B is a cross-sectional view of a gate conductive pattern, a cross-section of a semiconductor pattern, and a source / drain conductive pattern, taken along line "I-I '", line "II-II'", and line "III-III '" in FIG. 7A; Drawing showing a cross section of the wall.

8A through 8F are cross-sectional views illustrating the process of forming the semiconductor pattern and the source / drain conductive pattern shown in FIGS. 7A and 7B.

9A is a plan view showing a gate conductive pattern, a semiconductor pattern, a source / drain conductive pattern, and a transparent conductive pattern.

FIG. 9B is a cross-sectional view of the gate conductive pattern, the cross-section of the semiconductor pattern, and the source / drain conductive pattern, taken along the line "I-I '", the line "II-II'", and the line "III-III '" in FIG. 9A. A diagram showing a cross section and a cross section of a transparent conductive pattern.

10A to 10D are cross-sectional views showing stepwise steps of forming a transparent conductive pattern shown in FIGS. 9A and 9B.

<Explanation of symbols for the main parts of the drawings>

45a: first gate insulating pattern

141a, 141b, and 141c: opening holes defined by the first gate insulating pattern

32: gate line 32a: gate electrode

32b: gate pad lower electrode 45b: second gate insulating pattern

143a and 143b: grooves of the second gate insulating pattern

145: opening hole defined by the second gate insulating pattern

46 semiconductor pattern 34 data line

34a: source electrode 34b: drain electrode

34c: Data pad lower electrode 47: Protective pattern

147a, 147b, 147c: opening holes defined by the protection pattern

39: pixel electrode 48: gate pad upper electrode

49: data pad upper electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a thin film transistor array and a method of manufacturing the same, which reduce the number of vacuum deposition processes and reduce material costs.

A liquid crystal display (LCD) displays an image corresponding to a video signal on a liquid crystal display panel in which liquid crystal cells are arranged in a matrix by adjusting the light transmittance of the liquid crystal cells according to the video signal. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in an active matrix, and driving circuits for driving the liquid crystal display panel.

As shown in FIG. 1, the liquid crystal display panel includes an upper substrate 1 and a lower substrate 11 bonded together with a liquid crystal 8 interposed therebetween. The color filter array 10 is formed on the upper substrate 1, and the thin film transistor array 20 is formed on the lower substrate 11. The upper substrate 1 and the lower substrate 11 are bonded to face the color filter array 10 and the thin film transistor array 20.

The color filter array 10 includes a black matrix 2 for preventing light leakage, a color filter 4 for color implementation, and a common electrode 6 forming a vertical electric field with the pixel electrode 19.

The thin film transistor array 20 includes a gate line 12 and a data line 14 crossing each other to define a pixel region, a thin film transistor 16 connected to the signal lines 12 and 14, and a thin film transistor ( 16 connected to the pixel electrode 19 connected to the pixel electrode 19, the storage capacitor 18 connected to the pixel electrode 19, the gate pad 22 connected to the gate line 12, and the data line 14. A data pad 24.

An alignment layer for orienting the liquid crystal 8 is formed on the color filter array 10 and the thin film transistor array 20.

The liquid crystal 8 oriented on the alignment film rotates according to the potential difference between the common electrode 6 and the pixel electrode 19 to adjust the light transmittance to display an image on the liquid crystal display panel. Since the degree of rotation of the liquid crystal 8 varies depending on the potential difference formed between the common electrode 6 and the pixel electrode 19, the light transmittance may be adjusted. The potential difference between the common electrode 6 and the pixel electrode 19 depends on the video signal charged in the pixel electrode 19.

Hereinafter, a method of charging a video signal to the pixel electrode 19 will be described with reference to FIG. 2 showing the thin film transistor array 20 in detail.

The pixel electrode 19 is connected to the thin film transistor 16 to charge the video signal to the pixel electrode 19.

The thin film transistor 16 responds to the scan signal from the gate line 12, causing the video signal from the data line 14 to charge the pixel electrode 19. To this end, the thin film transistor 16 includes a gate electrode 12a connected to the gate line 12, a source electrode 14a connected to the data line 14, and a drain electrode facing the source electrode 14a with a semiconductor channel interposed therebetween. 14b and a semiconductor pattern 26 in ohmic contact with each of the source electrode 14a and the drain electrode 14b. The semiconductor pattern 26 includes an active layer 26a and an ohmic contact layer 26b. The active layer 26a overlaps the gate electrode 12a with the gate insulating layer 25 therebetween, and is exposed between the source electrode 14a and the drain electrode 14b to form a semiconductor channel. The ohmic contact layer 26b is disposed between the source electrode 14a and the active layer 26a so that the source electrode 14a and the drain electrode 14b are in ohmic contact with the active layer 26a, and the drain electrode 14b and the active layer 26a. Overlap between. The thin film transistor 16 is protected through the protective film pattern 37. The pixel electrode 19 is connected to the thin film transistor 16 by contacting the drain electrode 14b through the first contact hole 121 penetrating the passivation layer 37.

The video signal charged in the pixel electrode 19 is held by the storage capacitor 18. To this end, the storage capacitor 18 includes a gate line 12 and a pixel electrode 19 overlapping each other with the gate insulating layer 25 and the passivation layer 27 interposed therebetween.

The gate line 12 is connected to the gate driver through the gate pad 22 to supply a scan signal to the thin film transistor 16. The gate pad 22 includes a gate pad lower electrode 12b connected to the gate line 12, and a gate pad upper electrode 28 connected to the gate pad lower electrode 12b. The gate pad upper electrode 28 is connected to the gate pad lower electrode 12b through a second contact hole 122 penetrating the gate insulating film 25 and the passivation layer 27 to expose the gate pad lower electrode 12b. .

The data line 14 is connected to the data driver through the data pad 24 to supply a video signal to the thin film transistor 16. The data pad 24 is composed of a data pad lower electrode 14c connected to the data line 14 and a data pad upper electrode 29 connected to the data pad 14c. The data pad upper electrode 29 is connected to the data pad lower electrode 14c through a third contact hole 123 penetrating the gate insulating layer 25 and the passivation layer 27 to expose the data pad lower electrode 14c. .

The thin film transistor array 20 is formed by a plurality of mask processes. One mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist strip process, an inspection process, and the like. The photolithography process requires expensive equipment, including photoresist coating, exposure, photodevelopment, and stripping of photoresist, as well as a large number of processes and a high waste of photoresist. The thin film deposition process requires expensive vacuum equipment to increase the manufacturing cost of the liquid crystal display panel.

An object of the present invention is to provide a thin film transistor array and a method of manufacturing the same to reduce the number of vacuum deposition process and to reduce the material cost.

In order to achieve the above object, a thin film transistor array according to an embodiment of the present invention is formed on the substrate first gate insulating patterns defining an opening hole for exposing the substrate; A gate conductive pattern filled in the opening hole defined by the first gate insulating patterns; Second gate insulating patterns formed on the gate conductive pattern and the first gate insulating pattern and including grooves; A semiconductor pattern and a source / drain conductive pattern filled in the groove of the second gate insulating pattern; Protective patterns formed on the second gate insulating pattern to define opening holes exposing the second gate insulating pattern; And a transparent conductive pattern filled in the opening hole defined by the protection patterns.

According to an aspect of the present invention, there is provided a method of fabricating a thin film transistor array, the method comprising: forming first gate insulating patterns on the substrate to define an opening hole exposing the substrate; Filling a gate conductive pattern into an opening defined by the first gate insulating patterns; Forming second gate insulating patterns including grooves on the gate conductive pattern and the first gate insulating pattern; Filling a semiconductor pattern and a source / drain conductive pattern in the groove of the second gate insulating pattern; Forming protective patterns on the second gate insulating pattern to define an opening hole exposing the second gate insulating pattern; And filling a transparent conductive pattern in the opening hole defined by the protection patterns.

The gate conductive pattern includes a gate line, a gate electrode connected to the gate line, and a gate pad lower electrode connected to the gate line.

The transparent conductive pattern includes a gate pad upper electrode connected to the gate pad lower electrode through an opening hole defined by the second insulating patterns and an opening hole defined by the protection pattern.

The source / drain conductive pattern may include a data line crossing the gate line to define a pixel area, a source electrode connected to the data line, a drain electrode separated from the source electrode, and a data pad lower electrode connected to the data line. do.

The transparent conductive pattern includes a data pad upper electrode connected to the data pad lower electrode through an opening hole defined by the protective pattern.

The transparent conductive pattern includes a pixel electrode connected to the drain electrode through an opening hole defined by the protective pattern.

The forming of the first gate insulating patterns may include applying a liquid gate insulating material on the substrate; Arranging a soft mold having an intaglio pattern and an embossed pattern on the liquid gate insulating material to contact the protrusion with a substrate; Curing the gate insulating material of the liquid phase.

The filling of the gate conductive pattern may include applying a gate conductive powder solution into the opening hole defined by the first gate insulating patterns; And curing the gate conductive powder solution.

Hydrophobic treatment of the upper surface of the first gate insulation patterns prior to applying the gate conductive powder solution.

The hydrophobic treatment of the upper surface of the first gate insulating pattern may include contacting a flat plate mold including a hydrophobic material with the upper surface of the first gate insulating pattern; And transferring a hydrophobic material of the plate mold to an upper surface of the first gate insulating pattern in contact with the plate mold.

The gate conductive powder solution includes a hydrophilic solvent.

The forming of the second gate insulating patterns may include applying a liquid gate insulating material on the gate conductive pattern and the first gate insulating pattern; Arranging a first intaglio pattern, a second intaglio pattern having a deeper depth than the first intaglio pattern, and a soft mold having an embossed pattern on the liquid gate insulating material; Curing the liquid gate insulating material to form a groove of the second gate insulating pattern inverted to the shape of the first intaglio pattern, and the second gate insulating pattern of a shape inverted to the shape of the second intaglio pattern Forming an opening defined by.

The filling of the semiconductor pattern and the source / drain conductive pattern may include applying a liquid semiconductor material to the groove of the second gate insulating pattern; Curing the liquid semiconductor material to form an active layer; Applying a source / drain conductive powder solution to the opening hole by bypassing the surface of the active layer corresponding to the semiconductor channel portion between the source electrode and the drain electrode; And applying the source / drain conductive powder solution.

Applying a dopant-containing solution to the semiconductor material prior to applying the source / drain conductive powder solution to the groove of the second gate insulating pattern by bypassing the semiconductor channel part; And curing the solution including the dopant in the semiconductor material to form an ohmic contact layer.

Arranging a soft mold including a hydrophobic material and having a flat portion and an embossed pattern to contact the embossed pattern with the semiconductor channel portion; And transferring the hydrophobic material of the soft mold to the semiconductor channel portion.

Either the source / drain conductive powder solution or a solution in which a dopant is included in the semiconductor material includes a hydrophilic solvent.

The forming of the protective patterns may include applying a liquid insulating material on the second gate insulating pattern and the source / drain conductive pattern; The first embossed pattern corresponds to the pixel area by arranging a soft mold including an intaglio pattern, a first embossed pattern, and a second embossed pattern having a height higher than that of the first embossed pattern on the liquid insulating material. Contacting a second gate insulating pattern and contacting a second embossed pattern to the gate pad lower electrode; And curing the liquid insulating material.

The filling of the transparent conductive pattern may include applying a transparent conductive powder solution into the opening hole defined by the protective patterns; And curing the transparent conductive powder solution.

Hydrophobic treatment of the upper surface of the protective patterns prior to the step of applying the transparent conductive powder solution.

The hydrophobic treatment of the upper surface of the protective pattern may include contacting a flat mold including a hydrophobic material with the upper surface of the protective pattern; And transferring the hydrophobic material of the plate mold to the upper surface of the protective pattern in contact with the plate mold.

The transparent conductive powder solution includes a hydrophilic solvent.

Other objects and advantages of the present invention other than the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 10D.

3 is a plan view illustrating a thin film transistor array according to an exemplary embodiment of the present invention, and FIG. 4 is a line "I-I '", a line "II-II'", and a line "III-" of the thin film transistor array shown in FIG. It is sectional drawing cut out along III '".

3 and 4, a thin film transistor array according to an exemplary embodiment of the present invention may include a gate line 32 and a data line 34 and signal lines 32 and 34 defining a pixel area crossing each other. A thin film transistor 36 connected to the thin film transistor 36, a pixel electrode 39 connected to the thin film transistor 36, a storage capacitor 38 connected to the pixel electrode 39, and a gate pad connected to the gate line 32. 42 and a data pad 44 connected to the data line 34.

The thin film transistor 36 supplies the video signal from the data line 34 to the pixel electrode 39 in response to the scan signal from the gate line 32. To this end, the thin film transistor 36 includes a gate electrode 32a connected to the gate line 32, a source electrode 34a connected to the data line 34, and a drain facing the source electrode 34a with a semiconductor channel interposed therebetween. The semiconductor pattern 46 is in ohmic contact with each of the electrode 34b and the source electrode 34a and the drain electrode 34b. The semiconductor pattern 46 may be formed of a single layer of the active layer 46a or a double layer of the active layer 46a and the ohmic contact layer 46b according to the characteristics of the material of the semiconductor pattern 46. Hereinafter, the semiconductor pattern 46 will be described based on the example including the active layer 46a and the ohmic contact layer 46b. The active layer 46a overlaps the gate electrode 32a with the second gate insulating pattern 45b interposed therebetween, and is exposed between the source electrode 34a and the drain electrode 34b to form a semiconductor channel. The ohmic contact layer 46b is formed between the source electrode 34a and the active layer 46a and the drain electrode 34b and the active layer 46a such that the source electrode 34a and the drain electrode 34b are in ohmic contact with the active layer 36a. Overlap between. The protection pattern 47 is formed on the thin film transistor 36. The pixel electrode 39 is filled in the fifth opening hole 147a exposing the drain electrode 34b and connected to the drain electrode 34b of the thin film transistor 36.

The video signal charged in the pixel electrode 39 is held by the storage capacitor 38. To this end, the storage capacitor 38 includes a second gate insulating pattern 45b and a gate line 32 and a pixel electrode 39 overlapping each other with the second gate insulating pattern 45b interposed therebetween.

The gate line 32 is connected to the gate driver through the gate pad 42, and is connected to the gate electrodes 32a of the thin film transistor 36 included in one pixel row, thereby receiving a scan signal from the gate driver. It supplies to the gate electrode 32a of 36. The gate pad 42 includes a gate pad lower electrode 32b connected to the gate line 32 and a gate pad upper electrode 48 connected to the gate pad lower electrode 32b. The gate pad upper electrode 48 is filled in the fourth opening hole 145 exposing the gate pad lower electrode 42b and the sixth opening hole 147b overlapping the fourth opening hole 145 to form a lower portion of the gate pad. It is connected to the electrode 32b.

The data line 34 is connected to the data driver through the data pad 44 to supply a video signal to the thin film transistor 36. The data pad 44 includes a data pad lower electrode 34c connected to the data line 34 and a data pad upper electrode 49 connected to the data pad lower electrode 34c. The data pad upper electrode 49 is filled in the seventh opening hole 147c exposing the data pad lower electrode 34c and connected to the data pad lower electrode 34c.

The thin film transistor array according to the exemplary embodiment of the present invention includes a plurality of conductive patterns and insulating patterns. The insulating pattern according to the present invention includes a groove or defines an opening hole, and the conductive pattern is filled in the opening hole or the groove. The surface of the thin film transistor array according to the exemplary embodiment of the present invention may have a flattened surface because the surface of the conductive pattern filled in the opening hole or the groove is flat with the surface of the insulating pattern.

Insulating patterns according to an embodiment of the present invention are formed on the first gate insulating pattern 45a, the second gate insulating pattern 45b formed on the first gate insulating pattern 45a, and the second gate insulating pattern 45b. The protective pattern 47 is formed. The first gate insulating pattern 45a may include first to third opening holes 141a, 141b, and 141c to which the gate conductive pattern including the gate line 32, the gate electrode 32a, and the gate pad lower electrode 32b is filled. ). The second gate insulating pattern 45b exposes the gate pad lower electrode 32b and defines a fourth opening hole 145 to which the gate pad upper electrode 48 is filled. The protective pattern 47 may include the fifth to seventh opening holes 147a, 147b, and 147c to be filled with the transparent conductive pattern including the pixel electrode 39, the gate pad upper electrode 48, and the data pad upper electrode 49. Define. The fifth opening hole 147a exposes the drain electrode 34b, the sixth opening hole 147b overlaps the fourth opening hole 145 to expose the gate pad lower electrode 32b, and the seventh opening hole. 147c exposes the data pad lower electrode 34c.

The second gate insulating pattern 45b further includes first and second grooves 143a and 143b to be filled with the semiconductor pattern 46 and the source / drain conductive pattern. The source / drain conductive pattern includes a data line 34, a source electrode 34a, a drain electrode 34b, and a data pad upper electrode 34c. A semiconductor overlapping the data line 34, the source electrode 34a and the drain electrode 34b in the first groove 143a and the lower portion of each of the data line 34, the source electrode 34a and the drain electrode 34b. Pattern 46 is filled. The second pad 143b is filled with the data pad upper electrode 34c and the semiconductor pattern 46 overlapping the lower portion of the data pad upper electrode 34c.

The thin film transistor array according to the embodiment of the present invention described above is manufactured by a soft mold process, excluding a mask process including a photolithography process. Hereinafter, a manufacturing process of a thin film transistor array according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 5A to 10D.

As shown in FIGS. 5A and 5B, a first gate insulating pattern 45a defining first to third opening holes 141a, 141b, and 141c is formed on the substrate 31 through a soft mold process. In the first to third opening holes 141a, 141b, and 141c, a gate conductive pattern including a gate line 32, a gate electrode 32a, and a gate pad lower electrode 32b is formed.

Hereinafter, the gate conductive pattern forming process will be described step by step with reference to FIGS. 6A to 6D.

As shown in FIG. 6A, a gate insulating material 61 is coated on the substrate 31. The gate insulating material 61 is a material in a solution state in which either an inorganic insulator or an organic insulator is dissolved in a solvent. The inorganic insulator includes a mixture of silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxide (SiO _x ) and titanium oxide (TiO _x ), and the organic insulator is an acrylic organic compound, a benzo cyclobutene (BCB), PFBC (Perfluorocyclobutane), Teflon (Ceftop), Cytop (Cytop).

Thereafter, as illustrated in FIG. 6B, the first soft mold 63 including the intaglio pattern 63a and the embossed pattern 63b is aligned on the gate insulating material 61. The intaglio pattern 63a of the first soft mold corresponds to the region where the first gate insulating pattern is to be formed. The soft mold 63 is made of a highly elastic rubber material, for example, poly dimethyl siloxane (PDMS), polyurethane (polyurethane), cross-linked Novolac Resin.

The gate insulating material 61 is formed in correspondence with the intaglio pattern 63a of the first soft mold 63, and ultraviolet rays (hereinafter referred to as “UV”) are irradiated or heat is applied to the molded gate insulating material 61. Curing The gate insulating material 61 moves to the intaglio pattern 63a of the first soft mold by capillary force, and the embossed pattern 63b of the first soft mold is in contact with the substrate 31. As a result, as illustrated in FIG. 6C, the first gate insulating pattern 45a having a shape inverted from that of the first soft mold 63 is formed. After the first gate insulating pattern 45a is formed, the first soft mold 63 is separated from the substrate 31. Adjacent first gate insulating patterns 45a define first to third opening holes 141a, 141b, and 141c.

Thereafter, the top surface of the first gate insulating pattern 45a is modified to be hydrophobic in contact with the surface of the flat second soft mold 65 as shown in FIG. 6C.

Like the first soft mold 63 described above, the second soft mold 65 is made of a material having hydrophobicity such as polydimethylsiloxane, polyurethane, and cross linked novolac resin. The hydrophobic material is present in the oligomer form in the second soft mold 65. When the second soft mold 65 contacts the upper surface of the first gate insulating pattern 45a and is heated or irradiated with UV, an oligomeric hydrophobic material included in the second soft mold 65 may be formed in the first gate. The upper surface of the insulating pattern 45a is transferred. Accordingly, the upper surface of the first gate insulating pattern 45a is hydrophobic.

Another method of hydrophobicly treating the upper surface of the first gate insulating pattern 45a may be a method using a self assembly monolayer (hereinafter, referred to as “SAM”). In the hydrophobic treatment using SAM, the hydrophobic SAM is coated on the surface of the second soft mold 65, and then the second soft mold 65 is instantaneously contacted with the upper surface of the first gate insulating pattern 45a to form the hydrophobic SAM. It is made by transferring to the gate insulating pattern 45a. Hydrophobic SAM for hydrophobic treatment of the upper surface of the first gate insulating pattern 45a includes OTS (Octadecyltrichlorosilane).

After the upper surface of the first gate insulating pattern 45a is modified, the second soft mold 65 is separated from the substrate 31.

The metal powder solution in which the gate metal powder is dispersed is applied to the first to third opening holes 141a, 141b, and 141c in a solvent having characteristics opposite to the top surface of the first gate insulating pattern 45a. Since the top surface of the first gate insulating pattern 45a is hydrophobic, the solvent for dispersing the gate metal powder is hydrophilic. Hydrophilic solvents include ethylene glycol n-butyl ether acetate (EGBEA), carbitol acetate (CA), propylene glycol methyl ether acetate (PGMEA), propylene carbonate (PC), N-methyl pyrrolidone (NMP), and AMP (2-Amino2- methyl-1-propanol), 4-HMP (4-hydroxy-4-methyl-2-pentanone), PM (Propylene glycol methyl ether), IPA (Isopropyl alcohol), DPM (Dipropylene glycol methyl ether) and the like.

The gate metal powder solution may be applied to the first to third gate conductive pattern holes 141a, 141b, and 141c by an aerosol-jet method, an ink-jet method, a dip-pen method, or the like. In addition, the gate metal powder solution is more stably formed by the repulsive force between the upper surface of the first gate insulating pattern 45a and the gate metal powder solution (that is, the repulsive force between the hydrophilic material and the hydrophobic material). And 141b and 141c. Further, even when the gate metal powder solution is sprayed on the entire surface of the gate insulating pattern 45a, the gate metal powder solution may form the first to third gate conductive patterns by the repulsive force between the upper surface of the first gate insulating pattern 45a and the gate metal powder solution. Only inside the holes 141a, 141b, and 141c may be left.

The gate metal powder includes at least one metal among metals such as Mo, Ti, Cu, AlNd, Al, Cr, Ni, Ag, Au, Pt, Mo alloys, Cu alloys, Al alloys, and the like.

As the gate metal powder solution is cured after coating, the gate electrode 32a filled in the first opening hole 141a, the gate line 32 filled in the second opening hole 141b, and the third, as shown in FIG. 6D. The gate pad lower electrode 32c filled in the opening hole 141c is formed.

Subsequently, as illustrated in FIGS. 7A and 7B, the second gate insulating pattern including the first and second grooves 143a and 143b as well as defining the fourth opening hole 145 through a soft mold process may be used. 45b) is formed on the first gate insulating pattern 45a. The first and second grooves 143a and 143b include a semiconductor pattern 46 and a source / source including a data line 34, a source electrode 34a, a drain electrode 34b, and a data pad lower electrode 34c. A drain conductive pattern is formed.

Hereinafter, a process of forming the semiconductor pattern 46 and the source / drain conductive pattern will be described step by step with reference to FIGS. 8A to 8F.

As illustrated in FIG. 8A, a gate insulating material 61 is coated on the first gate insulating pattern 45a to cover the gate conductive pattern. A detailed description of the gate insulating material 61 is the same as in FIG. 6A described above.

Thereafter, as illustrated in FIG. 8B, a third soft mold including a first intaglio pattern 81a, a second intaglio pattern 81b, and a second embossed pattern 81c on the gate insulating material 61. 81 is aligned. The first and second intaglio patterns 81a and 81b of the third soft mold correspond to the region where the second gate insulating pattern 45b is to be formed. The depth d1 of the first intaglio pattern 81a is shallower than the depth d2 of the second intaglio pattern 81b, and the first intaglio pattern 81a is formed by the first and second grooves 143a and 143b. Corresponds to the area to be.

The gate insulating material 61 is molded through the shape of the third soft mold 81, and the molded gate insulating material 61 is cured. The gate insulating material 61 is moved into the first and second intaglio patterns 81a and 81b of the third soft mold by capillary force, and the embossed pattern 81c is in contact with the first gate insulating pattern 45a. . As a result, as illustrated in FIG. 8C, the second gate insulating patterns 45b having the shapes inverted from those of the first and second intaglio patterns 81a and 81b of the second soft mold 81 are formed. After the second gate insulating pattern 45b is formed, the second soft mold 81 is separated from the substrate 31. The second gate insulating patterns 45b adjacent to each other define a fourth opening hole 145. In addition, the second gate insulating pattern 45b includes first and second grooves 143a and 143b formed at a lower height than other portions. The first and second grooves 143a and 143b are formed to be the same as the heights of the semiconductor pattern and the source / drain pattern as a portion to be filled with the semiconductor pattern and the source / drain conductive pattern in a subsequent process.

Subsequently, active layers 46a are formed in the first and second grooves 143a and 143b as shown in FIG. 8D. The active layer 46a may include a liquid semiconductor material including liquid silicon (Si), liquid zinc oxide (ZnO), a mixture of liquid zinc oxide, a liquid organic semiconductor, a liquid organic-inorganic hybrid semiconductor, and the like. 143a, 143b) and then formed by curing.

Subsequently, as shown in FIG. 8E, the surface of the first groove 143a on which the semiconductor channel is to be formed is hydrophobized using the fourth soft mold 83 having the flat portion 83a and the relief pattern 83b. . To this end, the flat portion 83a of the fourth soft mold 83 is in contact with the top surface of the second gate insulating pattern 45b, and the relief pattern 83b is a gate electrode 32a of the surface of the first groove 143a. Contact with the part overlapping with). As described above with reference to FIG. 6C, the surface in contact with the fourth soft mold 83 is transferred to the hydrophobic material included in the fourth soft mold 83 to be hydrophobic. After the hydrophobic treatment, the crab soft mold 83 is separated from the substrate 31.

Thereafter, as shown in FIG. 8F, the ohmic contact layer 46b and the source / drain conductive pattern may be formed in the first groove 143a and the second groove 143b of the non-hydrophobic second gate insulating pattern 45b. Is formed. The ohmic contact layer 46b may not be formed depending on the characteristics of the semiconductor material constituting the active layer 46a. The first groove 143a includes a source electrode 34a and a drain electrode 34b facing each other with the semiconductor channel portion interposed therebetween, and a data line 34 connected to the source electrode 34a and intersecting with the gate line 32. Is formed. The data pad lower electrode 34c is formed in the second groove 143b. The ohmic contact layer 46b is formed under the source / drain conductive pattern. The ohmic contact layer 46b is formed by coating and curing liquid silicon or the like containing a dopant (n + or p +), and the source / drain conductive pattern is formed by coating and curing a source / drain metal powder solution. The ohmic contact layer 46b forming material and the source / drain metal powder are dispersed and coated in a hydrophilic solvent. The hydrophilic ohmic contact layer 46b forming material and the source / drain metal powder are not coated on the hydrophobic side by the repelling force between hydrophilic and hydrophobic.

The source / drain metal powder includes at least one metal among metals such as Mo, Ti, Cu, AlNd, Al, Cr, Ni, Ag, Au, Pt, Mo alloys, Cu alloys, Al alloys, and the like.

Thereafter, as shown in FIGS. 9A and 9B, a protective pattern 47 defining the fifth to seventh opening holes 147a, 147b, and 147c is formed through a soft mold process, and the fourth to seventh openings are formed. In the holes 145, 147a, 147b, and 147c, a transparent conductive pattern including the pixel electrode 39, the gate pad upper electrode 48, and the data pad upper electrode 49 is formed.

Hereinafter, referring to FIGS. 10A to 10D, the transparent conductive pattern forming process will be described step by step.

As shown in FIG. 10A, an insulating material 91 is coated on the second gate insulating layer pattern 45b to cover the semiconductor channel portion and the source / drain conductive pattern. The insulating material 91 is a solution material in which either an inorganic insulator or an organic insulator is dissolved in a solvent. The inorganic insulator includes a mixture of silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxide (SiO _x ) and titanium oxide (TiO _x ), and the organic insulator is an acrylic organic compound, a benzo cyclobutene (BCB), PFBC (Perfluorocyclobutane), Teflon (Ceftop), Cytop (Cytop).

Thereafter, as illustrated in FIG. 10B, the fifth soft mold 93 including the intaglio pattern 93a, the first embossed pattern 93b, and the second embossed pattern 93c is formed on the insulating material 91. Aligned. The intaglio pattern 93a of the fifth soft mold corresponds to the region where the protective pattern is to be formed.

The insulating material 91 is molded through the shape of the fifth soft mold 93, and cured by irradiating UV or applying heat to the molded insulating material 91. The insulating material 91 is moved into the intaglio pattern 93a of the fifth soft mold by capillary force, and the first relief pattern 93b of the fifth soft mold is the drain electrode 34b and the data pad upper electrode 34c. ) And the second gate insulating pattern 45b of the pixel area. In addition, the second embossed pattern 93c of the fifth soft mold contacts the gate pad lower electrode 32b. Accordingly, as shown in FIG. 10C, a protective pattern 47 having a shape inverted from that of the intaglio pattern 93a of the fifth soft mold 93 is formed. After the protective pattern 47 is formed, the fifth soft mold 93 is separated from the substrate 31. Adjacent protective patterns 47 define the fifth to seventh opening holes 147a, 147b, and 147c. In particular, the sixth opening hole 147b is formed to overlap the fourth opening hole 145 by the shape of the first and second relief patterns 93a and 93b of the fifth soft mold 93. The gate pad lower electrode 32b is exposed through the fourth and sixth opening holes 145 and 147b.

Subsequently, the top surface of the protective pattern 47 is modified to be hydrophobic in contact with the surface of the sixth soft mold 95 which is flat as shown in FIG. 10C. Since the method of modifying the upper surface of the protective pattern 47 is the same as described above with reference to FIG. 6C, it is omitted. After the upper surface of the protective pattern 47 is modified, the sixth soft mold 95 is separated from the substrate 31.

The fourth to seventh opening holes 145, 147a, 147b, and 147c are coated with a metal powder solution in which the transparent metal powder is dispersed in a solvent having properties opposite to those of the upper surface of the passivation layer pattern 47. Since the upper surface of the protective film pattern 47 is hydrophobic, the solvent for dispersing the transparent metal powder is hydrophilic.

The transparent metal powder solution may be applied only to the fourth to seventh opening holes 145, 147a, 147b, and 147c in the same manner as described above with reference to FIGS. 6C and 6D.

Transparent metal powders include indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (ITZO), and indium zinc oxide (IZO). do.

Thereafter, when the transparent metal powder solution is cured, the pixel electrode 39 in the fifth opening hole 147a and the gate pad upper electrode 48 in the fourth and sixth opening holes 145 and 147b as shown in FIG. 10D. ), The data pad upper electrode 147c is formed in the fifth opening hole 147c.

As described above, the thin film transistor array and the method of manufacturing the same according to the embodiment of the present invention use a soft mold process to define the openings between the insulating patterns or form grooves having a predetermined depth in the insulating patterns, thereby increasing the number of processes and waste of material costs. The large photolithography process can be eliminated, and since the thin film material is filled in the grooves and the openings, the vacuum deposition process can be excluded so that a plurality of conductive patterns are filled in the grooves or the openings through the coating and curing process.

In addition, the thin film transistor array according to an exemplary embodiment of the present invention may planarize the surface of the thin film transistor array by adjusting the surface of the thin film pattern filled in the groove or the opening hole to be flat with the top surface of the insulating pattern.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (27)

First gate insulating patterns formed on a substrate to define opening holes exposing the substrate; A gate conductive pattern filled in the opening hole defined by the first gate insulating patterns; Second gate insulating patterns formed on the gate conductive pattern and the first gate insulating pattern and including grooves; A semiconductor pattern and a source / drain conductive pattern filled in the groove of the second gate insulating pattern; Protective patterns formed on the second gate insulating pattern to define opening holes exposing the second gate insulating pattern; And And a transparent conductive pattern filled in the openings defined by the protection patterns. The method of claim 1, The gate conductive pattern may include a gate line, a gate electrode connected to the gate line, and a gate pad lower electrode connected to the gate line. The method of claim 2, The transparent conductive pattern is And a gate pad upper electrode connected to the gate pad lower electrode through an opening hole defined by the second insulating patterns and an opening hole defined by the protection pattern. The method of claim 2, The source / drain conductive pattern may include a data line crossing the gate line to define a pixel area, a source electrode connected to the data line, a drain electrode separated from the source electrode, and a data pad lower electrode connected to the data line. Thin film transistor array, characterized in that. The method of claim 4, wherein The transparent conductive pattern is And a data pad upper electrode connected to the data pad lower electrode through an opening hole defined by the protection pattern. The method of claim 4, wherein The transparent conductive pattern is And a pixel electrode connected to the drain electrode through an opening hole defined by the protection pattern. Forming first gate insulating patterns on the substrate, the first gate insulating patterns defining opening holes exposing the substrate; Filling a gate conductive pattern into an opening defined by the first gate insulating patterns; Forming second gate insulating patterns including grooves on the gate conductive pattern and the first gate insulating pattern; Filling a semiconductor pattern and a source / drain conductive pattern in the groove of the second gate insulating pattern; Forming protective patterns on the second gate insulating pattern to define an opening hole exposing the second gate insulating pattern; And And filling a transparent conductive pattern in the openings defined by the protective patterns. The method of claim 7, wherein The gate conductive pattern includes a gate line, a gate electrode connected to the gate line, and a gate pad lower electrode connected to the gate line. The method of claim 8, The transparent conductive pattern is And a gate pad upper electrode connected to the gate pad lower electrode through an opening hole defined by the second insulating patterns and an opening hole defined by the protection pattern. The method of claim 8, The source / drain conductive pattern may include a data line crossing the gate line to define a pixel area, a source electrode connected to the data line, a drain electrode separated from the source electrode, and a data pad lower electrode connected to the data line. Method for manufacturing a thin film transistor array, characterized in that. The method of claim 10, The transparent conductive pattern is And a data pad upper electrode connected to the data pad lower electrode through the opening hole defined by the protection pattern. The method of claim 10, The transparent conductive pattern is And a pixel electrode connected to the drain electrode through the opening hole defined by the protection pattern. The method of claim 7, wherein Forming the first gate insulating patterns Applying a liquid gate insulating material on the substrate; Arranging a soft mold having an intaglio pattern and an embossed pattern on the liquid gate insulating material to contact the protrusion with a substrate; And curing the liquid gate insulating material. The method of claim 7, wherein Filling the gate conductive pattern Applying a gate conductive powder solution into the openings defined by the first gate insulating patterns; And Curing the gate conductive powder solution comprising the step of manufacturing a thin film transistor array. The method of claim 14, And hydrophobicly treating an upper surface of the first gate insulating patterns before applying the gate conductive powder solution. The method of claim 15, Hydrophobic treatment of the top surface of the first gate insulating pattern Contacting a planar mold including a hydrophobic material to an upper surface of the first gate insulating pattern; And And transferring a hydrophobic material of the plate mold to an upper surface of the first gate insulating pattern in contact with the plate mold. The method of claim 15, The gate conductive powder solution is a method of manufacturing a thin film transistor array, characterized in that it comprises a hydrophilic solvent. The method of claim 9, Forming the second gate insulating patterns Applying a liquid gate insulating material on the gate conductive pattern and the first gate insulating pattern; Arranging a first intaglio pattern, a second intaglio pattern having a deeper depth than the first intaglio pattern, and a soft mold having an embossed pattern on the liquid gate insulating material; Curing the liquid gate insulating material to form a groove of the second gate insulating pattern inverted to the shape of the first intaglio pattern, and the second gate insulating pattern of a shape inverted to the shape of the second intaglio pattern And forming an opening defined by the thin film transistor array. The method of claim 10, The filling of the semiconductor pattern and the source / drain conductive pattern may include Applying a liquid semiconductor material to the groove of the second gate insulating pattern; Curing the liquid semiconductor material to form an active layer; Applying a source / drain conductive powder solution to the opening groove by bypassing the surface of the active layer corresponding to the semiconductor channel portion between the source electrode and the drain electrode; And And applying the source / drain conductive powder solution to the thin film transistor array. The method of claim 19, Before applying the source / drain conductive powder solution Applying a solution including a dopant in the semiconductor material to the groove of the second gate insulating pattern bypassing the semiconductor channel part; And Forming a ohmic contact layer by curing a solution containing a dopant in the semiconductor material. The method of claim 20, Arranging a soft mold including a hydrophobic material and having a flat portion and an embossed pattern to contact the embossed pattern with the semiconductor channel portion; And And transferring the hydrophobic material of the soft mold to the semiconductor channel portion. The method of claim 21, Any one of the source / drain conductive powder solution or a solution containing a dopant in the semiconductor material includes a hydrophilic solvent. The method of claim 9, Forming the protective patterns Applying a liquid insulating material on the second gate insulating pattern and the source / drain conductive pattern; Aligning the first embossed pattern to the pixel area by aligning the soft mold including an intaglio pattern, a first embossed pattern, and a second embossed pattern having a height higher than that of the first embossed pattern on the liquid insulating material Contacting a second gate insulating pattern and contacting a second embossed pattern to the gate pad lower electrode; And And curing the liquid insulating material. The method of claim 7, wherein Filling the transparent conductive pattern is Applying a transparent conductive powder solution into the opening hole defined by the protective patterns; And Curing the transparent conductive powder solution comprising the step of manufacturing a thin film transistor array. The method of claim 24, And hydrophobicly treating the upper surfaces of the protective patterns before applying the transparent conductive powder solution. The method of claim 25, Hydrophobic treatment of the upper surface of the protective pattern Contacting a flat mold including a hydrophobic material with an upper surface of the protective pattern; And And transferring the hydrophobic material of the plate mold to the upper surface of the protective pattern in contact with the plate mold. The method of claim 25, The transparent conductive powder solution is a method of manufacturing a thin film transistor array, characterized in that it comprises a hydrophilic solvent.

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