KR20080099423A - Method of fabricating semiconductor device having highly integrated cell structure and semiconductor device fabricated thereby - Google Patents

Abstract

The plane area(planar area) of the memory cell can be minimized and defects generated in burying metal in a contact hole having a big aspect rate can be prevented. The word line(WL2) having the first conductivity type and the other second conductive type is formed on the semiconductor substrate(100) of the first conductivity type. The laminated semiconductor patterns and the metal pattern which passes through the mold dielectric film are formed. The above semiconductor pattern(128) overlaps with the word line. The mold dielectric film(110) is formed on the semiconductor substrate having word line. The interlayer insulating film(150) is formed on the semiconductor substrate having metal pattern. The first electrode(160) which is electrically connected with the metal pattern is formed. The first electrode has the plane area which is smaller than that of the metal pattern. The intermetal insulator(177) is formed on the semiconductor substrate having the second electrode. The metal line(195) overlapping the word line on the intermetal insulator layer is formed.

Description

Method of manufacturing a semiconductor device having a highly integrated cell structure and a semiconductor device manufactured thereby

1 is a cross-sectional view showing a conventional semiconductor device.

2 is a plan view illustrating a semiconductor device according to example embodiments.

3A through 8A and FIGS. 3B through 8B are cross-sectional views illustrating semiconductor devices in accordance with some embodiments of the inventive concept.

9 is a cross-sectional view illustrating a semiconductor device according to another exemplary embodiment of the present invention.

10 is a cross-sectional view illustrating a semiconductor device according to still another embodiment of the present invention.

11 is a sectional view of a semiconductor device according to still another embodiment of the present invention.

12A and 12B are cross-sectional views illustrating semiconductor devices in accordance with still other embodiments.

13 is a cross-sectional view illustrating a semiconductor device according to still another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a highly integrated cell structure and a semiconductor device manufactured thereby.

Nonvolatile memory devices have a feature that data stored therein is not destroyed even if their power is cut off. Among the nonvolatile memory devices, the unit cell of the phase change memory devices includes one cell switching device and a phase change material layer connected to the switching device. In this case, upper and lower electrodes are provided on the upper and lower portions of the phase change material film, respectively. The lower electrode may be electrically connected to the switching element, and the upper electrode may be electrically connected to a bit line provided on the phase change material layer. The switching element may be an active element such as a MOS transistor.

A large program current of at least several mA is required to program the phase change memory cell, and the program current is provided through the MOS transistor. In order to reduce the area occupied by the unit cells of the memory device, it is necessary to reduce the area occupied by the MOS transistor used as the switching element. However, there is a limit in reducing the area occupied by the MOS transistor.

1 is a cross-sectional view showing a conventional semiconductor device.

Referring to FIG. 1, the word line 5 is formed by implanting impurity ions into a predetermined region of the semiconductor substrate 1. A lower interlayer insulating film 10 is formed on the semiconductor substrate having the word line 5. Subsequently, an opening penetrating the lower interlayer insulating film 10 is formed, and the semiconductor pattern 20 and the metal silicide film 25 are sequentially formed while partially filling the opening. The semiconductor pattern 20 is formed of a lower semiconductor pattern 12 and an upper semiconductor pattern 17 that are sequentially stacked. The semiconductor pattern 20 may form a cell diode. Subsequently, a spacer insulating film having a uniform thickness is formed on the semiconductor substrate having the metal silicide film 25, and the spacer insulating film is anisotropically etched to form the spacers 27 remaining on the sidewalls of the remaining portions of the openings. do. In general, the anisotropic etching process for forming the spacer proceeds to a dry etching process using a plasma. Therefore, during the anisotropic etching process using plasma, the metal silicide layer 25 may be etched by plasma.

A metal film is formed on the semiconductor substrate having the spacers 27, and the metal film is planarized until the lower interlayer insulating film 10 is exposed to form a lower electrode 30 remaining in the opening. Subsequently, a phase change material pattern 35 and an upper electrode 40 are sequentially formed on the lower electrode 30. An upper interlayer insulating layer 45 is formed on the semiconductor substrate having the upper electrode 40. A bit line plug 47 penetrates the upper interlayer insulating layer 45 and is electrically connected to the upper electrode 40, and a bit line 50 covering the bit line plug 47 is formed. An intermetallic insulating film 55 is formed on the semiconductor substrate having the bit line 50.

As described above, the metal silicide layer 25 may be etched while forming the spacers 27. Meanwhile, when the phase change memory device is driven, heat generated in the phase change material pattern 35 should be dissipated through the lower electrode 30. However, as the semiconductor device is increasingly integrated, the lower electrode 30 is formed to have a very narrow width, and thus there is a limit to efficiently dissipating heat through the lower electrode 30.

The intermetallic insulating layer 55, the upper interlayer insulating layer 45, and the lower interlayer insulating layer 10 are patterned to form a word line contact hole 60 exposing a predetermined region of the word line 5. A word line contact plug 65 is formed to fill the word line contact hole 60. The wordline contact plug 65 has a very large aspect ratio. Accordingly, there is a difficulty in photographic and etching processes for forming the word line contact hole 60 having a large aspect ratio. In addition, there is a difficulty in the process of filling the word line contact hole 60 with metal to form the word line contact plug 65. The reason is that the planar area of the wordline contact plug 65 should be minimized in accordance with the recent trend of high integration, so that the wordline contact hole 60 should have a large aspect ratio, and fill a contact hole having a large aspect ratio with metal. This is because there is a limit.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for manufacturing a semiconductor device having a highly integrated cell structure, and to provide semiconductor devices manufactured thereby.

According to one aspect of the present invention, a method of manufacturing a semiconductor device having a highly integrated cell structure is provided. The method includes forming a word line having a second conductivity type different from the first conductivity type on a semiconductor substrate of the first conductivity type. A mold insulating film is formed on the semiconductor substrate having the word line. The semiconductor patterns and the metal pattern are sequentially formed through the mold insulating layer, and the semiconductor patterns overlap the word line. An interlayer insulating film is formed on the semiconductor substrate having the metal pattern. A first electrode penetrating the interlayer insulating layer and electrically connected to the metal pattern is formed, and the first electrode has a planar area narrower than the metal pattern. An information storage element and a second electrode, which are sequentially stacked on the intermetallic insulating film and overlap with the first electrode, are formed. An intermetallic insulating film is formed on the semiconductor substrate having the second electrode. A metal line overlapping the word line is formed on the intermetallic insulating layer.

In some embodiments of the present invention, the semiconductor patterns may be formed of a vertical diode.

In another embodiment, after forming the semiconductor patterns, the method may further include forming a metal silicide layer on the semiconductor patterns.

In still another embodiment, after forming the metal pattern, the method may further include forming a metal buffer film on the semiconductor substrate having the metal pattern and planarizing the metal buffer film, wherein the metal buffer film is formed on the upper surface of the metal pattern. May remain in the middle.

In another embodiment, after the metal pattern is formed, the method may further include forming an insulating buffer layer having a uniform thickness on the semiconductor substrate having the metal pattern.

In another embodiment, the metal pattern may be formed to have negative inclined sidewalls.

In another embodiment, the metal pattern is formed such that a center portion of the upper surface is recessed, and the recessed region of the upper surface of the metal pattern may be in direct contact with the first electrode.

In another embodiment, the forming of the semiconductor patterns and the metal pattern may form a lower mold insulating layer having a word line opening exposing a predetermined region of the word line on the semiconductor substrate having the word line. Forming semiconductor patterns filling a line opening to form the semiconductor patterns, forming an upper mold insulating film having a contact hole exposing an upper portion of the semiconductor patterns on the lower mold insulating film, and forming the metal pattern in the contact hole It may include doing.

In another embodiment, the information storage element may comprise a phase change material film.

In yet another embodiment, before forming the intermetallic insulating film, a bit line for forming a lower intermetallic insulating film on the semiconductor substrate having the second electrode and patterning the lower intermetallic insulating film to expose the second electrode. The method may further include forming a contact hole and forming a bit line on the lower intermetallic insulating layer to cover the bit line contact hole and to have a direction intersecting the word line.

In another embodiment, after forming the first electrode, a lower contact plug penetrating the interlayer insulating film and the mold insulating film is formed, wherein the lower contact plug is electrically connected to a predetermined region of the word line. After the semiconductor pattern is spaced apart from the semiconductor pattern, the upper contact plug penetrates the intermetallic insulating film and overlaps the lower contact plug, wherein the upper contact plug is the metal line. Can be covered by.

In another exemplary embodiment, after forming the metal pattern, a lower contact plug penetrating the mold insulating layer is formed, wherein the lower contact plug is electrically connected to a predetermined region of the word line, and the semiconductor pattern is connected to the semiconductor patterns. Spaced apart and after forming the intermetallic insulating film, forming an upper contact plug penetrating the intermetallic insulating film and the interlayer insulating film and overlapping the lower contact plug, wherein the upper contact plug is connected to the metal line. Can be covered by.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

2 is a plan view illustrating a semiconductor device in accordance with embodiments of the present invention, and FIGS. 3A, 4A, 5A, 6A, 7A, and 8A illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention. 2B are cross-sectional views taken along line II ′ of FIG. 2, and FIGS. 3B, 4B, 5B, 6B, 7B, and 8B illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. 2 is a cross-sectional view taken along the line II-II 'of FIG. 2, FIG. 9 is a cross-sectional view taken along the line II ′ of FIG. 2 to explain a semiconductor device according to another embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 2 to illustrate a semiconductor device according to another embodiment, and FIG. 11 is a view taken along line II ′ of FIG. 2 to describe a semiconductor device according to another embodiment of the present invention. 12A and 12B show another embodiment of the present invention. 2 is a cross-sectional view taken along line II ′ of FIG. 2 to describe a semiconductor device according to another embodiment, and FIG. 13 is a line taken along line II ′ of FIG. 2 to describe a semiconductor device according to another embodiment of the present invention. It is a cross section.

First, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2, 3A to 8A, and 3B to 8B.

2, 3A, and 3B, a first conductive semiconductor substrate 100 is prepared. A word line isolation layer 105 may be formed in a predetermined region of the semiconductor substrate 100 to define a plurality of active regions. The word line isolation layer 105 may be formed using a shallow trench isolation technique. The active regions may be defined to be substantially parallel. Impurity ions of a second conductivity type different from the first conductivity type may be implanted into the active regions to form word lines WL1, WL2,..., WLm of the second conductivity type. As a result, the word line isolation layer 105 serves to electrically isolate the second conductive word lines WL1, WL2,..., WLm from each other. The first conductivity type may be P type, and the second conductivity type may be N type. Alternatively, the first and second conductivity types may be N type and P type, respectively.

A mold insulating layer 110 is formed on the entire surface of the semiconductor substrate having the word lines WL1, WL2,..., WLm. The mold insulating layer 110 may be formed of a silicon oxide layer. The mold insulating layer 110 is patterned to form a plurality of openings, that is, cell diode holes 115 exposing predetermined regions of the word lines WL1, WL2,..., WLm.

2, 4A, and 4B, semiconductor patterns 128 are formed in the cell diode holes 115. Each of the semiconductor patterns 128 may be formed to partially fill the cell diode holes 115. The semiconductor patterns 128 use a selective epitaxial growth technique that employs the word lines WL1, WL2,..., WLm exposed by the cell diode holes 115 as seed layers, respectively. Can be formed. Therefore, when the word lines WL1, WL2,..., WLm have a single crystal semiconductor structure, the semiconductor patterns 128 may be formed to have a single crystal semiconductor structure. When the selective epitaxial growth technique is performed using a silicon source gas, the semiconductor patterns 128 may be silicon layers. Alternatively, the semiconductor patterns 128 may be formed using solid phase epitaxial (SPE) technology.

 Each of the semiconductor patterns 128 may be formed of a first semiconductor pattern 120 and a second semiconductor pattern 125 that are sequentially stacked. The first and second semiconductor patterns 120 and 125 constitute cell diodes. Alternatively, the semiconductor patterns 128 may form a cell diode together with the word lines WL1, WL2,..., WLm. The cell diodes may be switching elements.

2, 5A, and 5B, a metal silicide layer 135 such as a cobalt silicide layer, a nickel silicide layer, or a titanium silicide layer may be formed on the semiconductor patterns 128. The metal silicide film may be formed using a conventional silicide technique.

A conductive barrier film having a uniform thickness is formed on the semiconductor substrate having the metal silicide layer 135, a metal layer is formed on the semiconductor substrate having the barrier layer, and an upper surface of the mold insulating layer 110 is exposed. The metal layer and the barrier layer may be planarized until it is. As a result, metal patterns 145 filling the remaining portions of the cell diode holes 115 and barrier patterns 140 covering the bottom and sidewalls of the metal patterns may be formed. The barrier pattern 140 may include a metal nitride layer, such as a titanium nitride layer. The metal patterns 145 may be formed of a metal film such as tungsten (W), molybdenum (Mo), or ruthenium (Ru).

2, 6A, and 6B, an interlayer insulating layer 150 may be formed on the mold insulating layer 110. Contact holes may be formed by patterning the interlayer insulating layer 150. A conformal spacer insulating layer may be formed on the semiconductor substrate having the contact holes. Subsequently, the spacer insulating layer may be anisotropically etched to form spacers 155 on sidewalls of the contact holes to expose the metal patterns 145 in the contact hole. Therefore, the metal silicide layers 135 may be prevented from being etched by the metal patterns 145 by the process of forming the spacers 155.

A metal film may be formed on the semiconductor substrate having the spacers 155, and the first electrode 160 may be formed by planarizing the metal film until the upper surface of the interlayer insulating film 150 is exposed. Each of the first electrodes 160 may be formed to have a smaller planar area than each of the metal patterns 145. The first electrodes 160 may be formed of a conductive film that does not react with the phase change material film formed in a subsequent process. For example, the first electrodes 160 may be formed to include a metal film such as titanium or a metal nitride film such as a titanium nitride film.

Patterning the interlayer insulating layer 150 and the mold insulating layer 110 to form lower contact holes 165 exposing predetermined regions of the word lines WL1, WL2,..., WLm, and forming the lower contact. Conductive lower barrier patterns 167 may be formed on an inner wall of the holes 165, and lower contact plugs 170 may be formed on the lower barrier patterns 167 to fill the lower contact holes 165. .

In another embodiment, as shown in FIG. 9, before forming the interlayer insulating layer 150, the mold insulating layer 110 is patterned to define predetermined regions of the word lines WL1, WL2,..., WLm. Lower contact plugs 270 forming lower contact holes exposing the lower contact holes, forming lower barrier patterns 267 on inner walls of the lower contact holes, and filling the lower contact holes on the lower barrier patterns 267. ) Can be formed.

2, 7A, and 7B, information storage elements 172 and second electrodes 174 sequentially stacked on a semiconductor substrate having the first electrodes 160 may be formed. The information storage elements 172 may be formed to cover the first electrodes 160. The information storage elements 172 may be formed of a phase change material film. For example, the phase change material layer may be formed of a chalcogenide layer such as a GST layer. The second electrode 174 may be a material film that does not react with the phase change material film. For example, the second electrode 174 may be formed to include a metal film such as a titanium film or a metal nitride film such as a titanium nitride film.

The lower intermetallic insulating layer 177 may be formed on the semiconductor substrate including the information storage elements 172 and the second electrode 174 that are sequentially stacked. The lower intermetallic insulating layer 177 may be patterned to form bit line contact holes exposing the second electrode 174. Subsequently, bit lines BL1, BL2,..., BLn covering the bit line contact holes may be formed. The bit lines BL1, BL2,..., BLn may be formed to have a direction that intersects the word lines WL1, WL2,..., WLm. Meanwhile, bit line plugs 183 may be interposed between the bit lines BL1, BL2,..., BLn and the second electrodes 174.

2, 8A, and 8B, an upper intermetallic insulating layer 187 may be formed on a semiconductor substrate having the bit lines BL1, BL2,..., BLn. Subsequently, upper contact holes 165 may be formed by patterning the upper intermetallic insulating layer 187 and the lower intermetallic insulating layer 177. Subsequently, upper barrier patterns 192 are formed on inner walls of the upper contact holes, and the upper contact holes 165 are filled on the upper barrier patterns 192, and the lower contact plugs 170 are electrically connected to the lower contact plugs 170. The upper contact plugs 193 connected to each other may be formed. The lower contact plugs 170 and the upper contact plugs 193 may constitute contact plug structures 194. Therefore, rather than forming the contact plug structures 194 into a single structure, the contact plug structures 194 are formed in a stacked structure of the lower contact plugs 170 and the upper contact plugs 193. As a result, process difficulty for forming the contact plug structures 194 may be improved. That is, by forming a contact plug structure having a large aspect ratio into a lower contact plug and an upper contact plug having a small aspect ratio, a defect caused by embedding a metal in a contact hole having a large aspect ratio (for example, a hole inside a plug or Voids) can be prevented.

As illustrated in FIG. 9, before forming the interlayer insulating layer 150, when the lower contact plugs 270 penetrating the mold insulating layer 110 are formed, the upper intermetallic insulating layer ( 187, the upper contact plugs penetrating the lower intermetallic insulating layer 177 and the interlayer insulating layer 150 may be formed.

Subsequently, a plurality of metal lines 195 may be formed on the upper intermetallic insulating layer 187. The metal lines 195 may have a direction crossing the bit lines BL1, BL2,..., BLn and may cover the upper contact plugs 193. In addition, the metal lines 195 may overlap the word lines WL1, WL2,..., WLm.

The phase change memory device manufactured using the method of manufacturing a semiconductor device as described above can effectively dissipate heat generated in a cell. That is, in the structure of the phase change memory device of the present invention, heat generated in the information storage element 170 may be efficiently dissipated through the first electrode 160 and the metal pattern 145.

Hereinafter, a method and a structure of a semiconductor device according to other embodiments of the present invention will be described.

First, a semiconductor device according to another exemplary embodiment of the present invention will be described with reference to FIG. 10.

Referring to FIG. 10, a semiconductor substrate having the word lines WL1, WL2,..., WLm as described with reference to FIGS. 3A and 3B is prepared. The lower mold insulating layer 310 may be formed on the semiconductor substrate prepared as described above. The lower mold insulating layer 310 may be patterned to form cell diode holes exposing predetermined regions of the word lines WL1, WL2,..., WLm. Subsequently, semiconductor patterns 328 may be formed to fill the cell diode holes. Each of the semiconductor patterns 328 may be formed of a first semiconductor pattern 320 and a second semiconductor pattern 325 that are sequentially stacked. The first and second semiconductor patterns 320 and 325 constitute cell diodes. Alternatively, the semiconductor patterns 328 may form a cell diode together with the word lines WL1, WL2,..., WLm. The cell diodes may serve as switching elements.

An upper mold insulating layer 330 may be formed on the semiconductor substrate having the semiconductor patterns 328. Subsequently, the upper mold insulating layer 330 may be patterned to form plug holes exposing the semiconductor patterns 328. The plug holes may be formed to have positive inclined sidewalls. A metal silicide layer 335 may be formed in the semiconductor patterns 328 exposed by the plug holes. Meanwhile, before forming the upper mold insulating layer 330, the metal silicide layer 335 may be formed on the surfaces of the semiconductor patterns 328.

Subsequently, conductive barrier patterns 340 may be formed on inner walls of the plug holes. Metal patterns 345 may be formed on the conductive barrier patterns 340 to fill the plug holes. In this case, the metal patterns 345 may be formed to have negative inclined sidewalls. Accordingly, since the upper widths of the metal patterns 345 are greater than the lower widths, defects such as seams in the metal patterns 345 may be suppressed.

Lower contact holes may be formed by patterning the upper mold insulating layer 330 and the lower mold insulating layer 310. Predetermined regions of the word lines WL1, WL2,..., WLm may be exposed by the lower contact holes. Lower barrier patterns 367 may be formed on inner walls of the lower contact holes. Subsequently, lower contact plugs 370 may be formed on the lower barrier patterns 367 to fill the lower contact holes. Subsequently, the first electrode 160, the information storage element 172, shown in FIGS. 8A and 8B using substantially the same method as described in FIGS. 6A to 8A and 6B to 8B, A semiconductor device having the second electrode 174, the bit lines BL1, BL2,..., BLn, the contact plug structures 194, and the metal lines 195 may be manufactured.

Next, a semiconductor device according to another exemplary embodiment of the present invention will be described with reference to FIG. 11.

Referring to FIG. 11, a semiconductor substrate having the word lines WL1, WL2,..., WLm as described with reference to FIGS. 3A and 3B is prepared. The lower mold insulating layer 410 may be formed on the semiconductor substrate prepared as described above. Semiconductor patterns 428 penetrating the lower mold insulating layer 410 may be formed. Each of the semiconductor patterns 428 may be formed of a first semiconductor pattern 420 and a second semiconductor pattern 425 which are sequentially stacked. The first and second semiconductor patterns 420 and 425 constitute cell diodes. Alternatively, the semiconductor patterns 428 may form a cell diode together with the word lines WL1, WL2,..., WLm.

An upper mold insulating layer 430 may be formed on the semiconductor substrate having the semiconductor patterns 428. Subsequently, the upper mold insulating layer 430 may be patterned to form openings that expose the semiconductor patterns 428, that is, plug holes. A metal silicide layer 435 may be formed in the semiconductor patterns 428 exposed by the plug holes. Meanwhile, before forming the upper mold insulating layer 430, the metal silicide layer 435 may be formed on the surfaces of the semiconductor patterns 428.

A barrier film, a metal film, and a metal buffer film may be sequentially formed on the semiconductor substrate having the plug holes. Subsequently, the barrier layer, the metal layer, and the metal buffer layer are planarized until the upper surface of the upper mold insulating layer 430 is exposed, so that the barrier patterns 440 and the metal patterns 445 remaining in the plug holes are formed. And metal buffer patterns 447. Here, the metal buffer patterns 445 may remain in the middle of the upper region of the metal patterns 445. Accordingly, the metal buffer patterns 445 may prevent a defect such as a seam from occurring in a center portion of an upper region of the metal patterns 445. Subsequently, the first electrode 160, the information storage element 172, and the first electrode 160 illustrated in FIGS. 8A and 8B using substantially the same method as described in FIGS. 6A to 8A and 6B to 8B. A semiconductor device having a second electrode 174, the bit lines BL1, BL2,..., BLn, the contact plug structures 194, and the metal lines 195 may be manufactured.

Next, a semiconductor device according to still another embodiment of the present invention will be described with reference to FIGS. 12A and 12B.

Referring to FIG. 12A, a semiconductor substrate having the word lines WL1, WL2,..., WLm as described with reference to FIGS. 3A and 3B is prepared. The lower mold insulating layer 510 may be formed on the semiconductor substrate prepared as described above. Semiconductor patterns 528 may be formed to penetrate the lower mold insulating layer 510. Each of the semiconductor patterns 528 may be formed of a first semiconductor pattern 520 and a second semiconductor pattern 525 that are sequentially stacked. As described above, the semiconductor patterns 528 may form a diode. Alternatively, the semiconductor patterns 528 may form a diode together with the word lines WL1, WL2,..., WLm.

An upper mold insulating layer 530 may be formed on the semiconductor substrate having the semiconductor patterns 528. Subsequently, the upper mold insulating layer 530 may be patterned to form openings that expose the semiconductor patterns 528, that is, plug holes. A metal silicide layer 535 may be formed in the semiconductor patterns 528 exposed by the plug holes. Meanwhile, before forming the upper mold insulating layer 530, the metal silicide layer 535 may be formed on the surfaces of the semiconductor patterns 528.

A barrier film and a metal film may be sequentially formed on the semiconductor substrate having the plug holes. Subsequently, the barrier layer and the metal layer may be planarized until the upper surface of the upper mold insulating layer 530 is exposed to form barrier patterns 540 and metal patterns 545 remaining in the plug holes. . A recess region may be formed in a center portion of an upper surface of the metal patterns 545.

An insulating buffer layer 548 may be formed on the semiconductor substrate having the metal patterns 545. The insulating buffer layer 548 may be formed of a silicon oxide layer or a silicon nitride layer.

Referring to FIG. 12B, an interlayer insulating layer 550 may be formed on the insulating buffer layer 548. The interlayer insulating layer 550 may include a material layer having an etching selectivity with respect to the insulating buffer layer 548. For example, the interlayer insulating layer 550 in a portion in contact with the insulating buffer layer 548 may be formed of a material having an etch selectivity with respect to the insulating buffer layer 548. For example, when the insulating buffer layer 548 is formed of a silicon oxide layer, the interlayer insulating layer 550 may be formed of a silicon nitride layer and a silicon oxide layer that are sequentially stacked.

Contact holes may be formed by patterning the interlayer insulating layer 550. A conformal spacer insulating layer may be formed on the semiconductor substrate having the contact holes. Subsequently, the spacer insulating layer may be anisotropically etched to form spacers 555 on sidewalls of the contact holes to expose the insulating buffer layer 548 in the contact hole. The spacers 555 may be formed of a material having an etch selectivity with respect to the insulating buffer layer 548. For example, when the insulating buffer layer 548 is formed of a silicon oxide layer, the spacers 555 may be formed of a silicon nitride layer. Subsequently, the insulating buffer layer 548 exposed by the spacers 555 may be etched to expose the metal patterns 540. Thus, the spacers 555 may be prevented from remaining in the middle of the upper regions of the metal patterns 540. In addition, the metal patterns 545 may prevent the metal silicide layers 535 from being etched by the process of forming the spacers 555.

Subsequently, a metal film is formed on the semiconductor substrate having the exposed metal patterns 540, and the metal film is planarized and remains in the contact holes until the upper surface of the interlayer insulating film 550 is exposed. The first electrodes 556 may be formed to be electrically connected to the fields 540. Subsequently, the information storage element 172, the second electrode 174, shown in FIGS. 8A and 8B, using substantially the same method as described in FIGS. 7A, 7B, 8A, and 8B. A semiconductor device having the bit lines BL1, BL2,..., BLn, the contact plug structures 194, and the metal lines 195 may be manufactured.

The semiconductor device manufactured using the method of manufacturing the semiconductor device may improve electrical characteristics. More specifically, the metal patterns 545 may be formed to have a recessed region in the center portion of the upper surface which does not act as a defect such as a seam. That is, the recess region at the center of the upper surface of each of the metal patterns 545 may be formed to have a width enough to fill the first electrodes 556. Therefore, the first electrodes 556 and the metal patterns 545 may directly contact each other, and their contact area may increase. Accordingly, the contact area between the metal patterns 545 and the first electrodes 556 having a recessed area in the center portion of the upper surface is increased, so that the metal patterns 545 and the first electrodes are increased. Contact resistance characteristics between the electrodes 556 may be improved.

Next, a semiconductor device according to still another embodiment of the present invention will be described with reference to FIG. 13.

Referring to FIG. 13, a semiconductor substrate as described with reference to FIG. 12A is prepared. An interlayer insulating film 650 may be formed on the semiconductor substrate prepared as described above. The interlayer insulating layer 650 may include a material layer having an etching selectivity with respect to the insulating buffer layer 548. The interlayer insulating layer 550 and the insulating buffer layer 548 may be patterned to form contact holes exposing the metal patterns 540. First electrodes 660 uniformly covering inner walls of the contact holes in the contact holes and insulating patterns 662 filling the contact holes may be formed on the first electrodes 660. Therefore, the top surfaces of the first electrodes 660 may have a ring shape when viewed in plan view. Subsequently, the information storage element 172, the second electrode 174, and the information storage element 172 shown in FIGS. 8A and 8B are used using substantially the same method as described in FIGS. 7A, 7B, 8A, and 8B. A semiconductor device having bit lines BL1, BL2,..., BLn and the metal lines 195 may be manufactured.

According to the present invention as described above, when one cell is viewed, the cell diode, the metal silicide film, the metal pattern, the lower electrode and the information storage element may be sequentially aligned in the vertical direction from the semiconductor substrate. Therefore, the planar area of the memory cell can be minimized. Thus, a highly integrated cell structure can be implemented. In addition, since the lower electrode and the metal pattern are interposed between the information storage element and the cell diode, heat generated in the information storage element can be easily released through the lower electrode and the metal pattern. In addition, by forming the contact plug structure having a large aspect ratio into a lower contact plug and an upper contact plug having a small aspect ratio, it is possible to prevent defects occurring when the metal is embedded in the contact hole having a large aspect ratio.

Claims (20)

Forming a word line having a second conductivity type different from the first conductivity type on a first conductivity type semiconductor substrate, Forming a mold insulating film on the semiconductor substrate having the word line, The semiconductor patterns and the metal pattern are sequentially formed through the mold insulating layer, the semiconductor patterns overlap the word line, An interlayer insulating film is formed on the semiconductor substrate having the metal pattern; Forming a first electrode penetrating the interlayer insulating layer and electrically connected to the metal pattern, wherein the first electrode has a narrower planar area than the metal pattern; Forming an information storage element and a second electrode which are sequentially stacked on the intermetallic insulating layer and overlap with the first electrode; An intermetallic insulating film is formed on the semiconductor substrate having the second electrode, And forming a metal line overlapping the word line on the intermetallic insulating film. The method of claim 1, The semiconductor pattern is a manufacturing method of a semiconductor device, characterized in that formed by a vertical diode. The method of claim 1, After forming the semiconductor patterns, And forming a metal silicide layer on the semiconductor patterns. The method of claim 1, After forming the metal pattern, Forming a metal buffer film on the semiconductor substrate having the metal pattern; And planarizing the metal buffer layer, wherein the metal buffer layer remains at a center portion of an upper surface of the metal pattern. The method of claim 1, After forming the metal pattern, And forming an insulating buffer film having a uniform thickness on the semiconductor substrate having the metal pattern. The method of claim 1, The metal pattern is a method of manufacturing a semiconductor device, characterized in that formed to have a negative inclined sidewall. The method of claim 1, The metal pattern is formed so that the center portion of the upper surface is recessed, wherein the recessed region of the upper surface of the metal pattern is in direct contact with the first electrode. The method of claim 1, Forming the semiconductor patterns and the metal pattern Forming a lower mold insulating film having a word line opening exposing a predetermined region of the word line on a semiconductor substrate having the word line, Forming semiconductor patterns filling the word line openings to form the semiconductor patterns, Forming an upper mold insulating film having a contact hole exposing an upper portion of the semiconductor patterns on the lower mold insulating film, And forming the metal pattern in the contact hole. The method of claim 1, And the information storage element comprises a phase change material film. The method of claim 1, Before forming the intermetallic insulating film, A lower intermetallic insulating film is formed on the semiconductor substrate having the second electrode, Patterning the lower intermetallic insulating layer to form a bit line contact hole exposing the second electrode, And forming a bit line on the lower intermetallic insulating layer to cover the bit line contact hole and have a directionality intersecting the word line. The method of claim 1, After forming the first electrode, a lower contact plug penetrating the interlayer insulating film and the mold insulating film is formed, wherein the lower contact plug is electrically connected to a predetermined region of the word line and spaced apart from the semiconductor patterns. Become, After forming the intermetallic insulating film, the method further comprises forming an upper contact plug penetrating the intermetallic insulating film and overlapping the lower contact plug, wherein the upper contact plug is covered by the metal line. A method of manufacturing a semiconductor device. The method of claim 1, After forming the metal pattern, a lower contact plug penetrating the mold insulating layer is formed, wherein the lower contact plug is electrically connected to a predetermined region of the word line and spaced apart from the semiconductor patterns. After forming the intermetallic insulating film, further forming an upper contact plug penetrating the intermetallic insulating film and the interlayer insulating film and overlapping the lower contact plug, wherein the upper contact plug is covered by the metal line. Method for manufacturing a semiconductor device, characterized in that. A word line provided on the semiconductor substrate of a first conductivity type and having a second conductivity type different from the first conductivity type; Semiconductor patterns and metal patterns sequentially stacked on the word line; A first electrode provided on the metal pattern and having a planar area smaller than the metal pattern; An information storage element and a second electrode sequentially stacked on the first electrode; A bit line on the second electrode; An insulating layer surrounding sidewalls of the semiconductor patterns, the metal pattern, the first electrode, the information storage element, and the second electrode and covering the bit line; A contact plug structure penetrating the insulating film, the contact plug structure including a lower contact plug and an upper contact plug sequentially stacked; And And a metal line provided on the insulating film and covering the contact plug structure. The method of claim 13, And a metal silicide layer interposed between the semiconductor patterns and the metal pattern. The method of claim 13, And the lower contact plug is positioned at the same level as the semiconductor patterns, the metal pattern, and the first electrode which are sequentially stacked. The method of claim 13, And the lower contact plug is positioned at the same level as the semiconductor patterns and the metal pattern that are sequentially stacked. The method of claim 13, And the first electrode extends into the metal pattern. The method of claim 13, And the metal line overlaps the word line. A word line provided on the semiconductor substrate of a first conductivity type and having a second conductivity type different from the first conductivity type; Semiconductor patterns on the word line; A metal pattern provided on the semiconductor patterns and recessed in a central portion of an upper surface thereof; A first electrode provided on the metal pattern and having a bottom portion in contact with a recessed center portion of the upper surface of the metal pattern; And And a information storage element on said first electrode. The method of claim 19, And a metal silicide layer interposed between the semiconductor patterns and the metal pattern.

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