KR20080089065A - Method for forming contact in semiconductor device using solid phase epitaxy - Google Patents

Method for forming contact in semiconductor device using solid phase epitaxy Download PDF

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KR20080089065A
KR20080089065A KR1020070032049A KR20070032049A KR20080089065A KR 20080089065 A KR20080089065 A KR 20080089065A KR 1020070032049 A KR1020070032049 A KR 1020070032049A KR 20070032049 A KR20070032049 A KR 20070032049A KR 20080089065 A KR20080089065 A KR 20080089065A
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contact
contact layer
forming
semiconductor device
epitaxial
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KR1020070032049A
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Korean (ko)
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안태항
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method for forming a contact of a semiconductor device using a solid phase epitaxy is provided to reduce contact resistance by performing a cell spacer process after a first contact layer is formed to realize a wider contact volume. Plural gate patterns are formed on a semiconductor substrate(21). A first spacer is formed on a sidewall of the gate pattern. A first contact layer(26) is formed to gap-fill a part between the gate patterns. A second spacer is formed on an upper sidewall of the gate pattern exposed by the first contact layer. An interlayer dielectric having a contact hole is formed. The contact hole exposes the first contact layer. A second contact layer(32) is formed to be gap-filled in the contact hole. The first and second contact layers are used by solid phase epitaxy(SPE) process. Each first and second contact layer is one epitaxial layer selected from epitaxial silicon, epitaxial germanium, and epitaxial silicon germanium formed by the solid phase epitaxy process.

Description

Method for forming contact of semiconductor device using solid phase epitaxy process {METHOD FOR FORMING CONTACT IN SEMICONDUCTOR DEVICE USING SOLID PHASE EPITAXY}

1 is a diagram illustrating a doping profile of phosphorus (P) according to depth when an interfacial oxide film is present.

2A and 2B illustrate a concept of a solid phase epitaxy process according to an embodiment of the present invention.

3 is a result of quantitative analysis of oxygen element (interface oxide film presence) at each interface of epitaxial silicon by polysilicon and solid phase epitaxy.

4A to 4E are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 gate insulating film

23: gate electrode 24: gate hard mask

25: gate spacer 26: the first contact layer

27: cell spacer 32: second contact layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact for a semiconductor device.

In the situation where semiconductor devices are becoming more and more direct, in the case of DRAM, the contact region in the cell transistor is also affected. In other words, as the semiconductor device becomes smaller and more direct, the contact area gradually decreases, resulting in an increase in contact resistance and a decrease in drive current. As a result, the write recovery time of the semiconductor device is increased. In addition to device degradation such as defects, the yield is also affected. Therefore, in order to reduce the contact resistance of the device, a method of increasing the contact area, a method of increasing the phosphorus doping concentration in the contact material, and a method of removing the interfacial oxide film formed when using polysilicon should be applied.

In the current semiconductor manufacturing process, the contact area also tends to decrease due to the reduction of the circuit line width and the miniaturization of the semiconductor device. Therefore, the increasing contact resistance must be reduced.

The prior art uses polysilicon as the contact material. For example, polysilicon having a Phosphorus doping concentration of 1.0 to 5.0 E20 atoms / cm 3 is deposited in a batch-type furnace using a temperature of 500 to 550 ° C. and SiH 4 / PH 3 gas.

However, in polysilicon deposition, the surface oxide film (fine surface oxide film) is finely formed at the interface between the polysilicon and the silicon substrate by the oxygen concentration (tens of ppm) present when the silicon substrate on which the polysilicon is to be deposited is loaded into the furnace under atmospheric pressure. For example, there is a problem that SiO 2 ) is formed.

Such an interfacial oxide film is a cause for increasing the contact resistance of an element. On the other hand, the interfacial oxide film thus formed reduces the contact resistance improvement effect of the contact obtained by increasing the concentration of phosphorus (phosporus) by significantly piling up the dopant phosphorus (phosporus).

FIG. 1 is a diagram illustrating a doping profile of phosphorus (P) according to a depth when an interfacial oxide film is present. The doped phosphorus is concentrated in a portion adjacent to the interfacial oxide film (particularly, 2000Å deep). It can be seen that.

As described above, according to the method of forming a contact using polysilicon, it is difficult to reduce contact resistance and improve device characteristics in accordance with a trend that semiconductor devices continue to become more direct.

In order to overcome the above problems and lower the contact resistance of the device as well as to improve the device characteristics, epitaxial silicon (epitaxial-Si) is being developed. Among them, SEG (selective epitaxial growth) has a very low contact resistance by forming a good quality epitaxial silicon without the interfacial oxide film between the contacts, and has been actively researched and developed domestically and internationally.

However, since the SEG process is a high temperature process (820 ° C or higher) that requires in-situ H 2 -bake pretreatment, the cell / junction will be used in the future manufacturing process of sub 60nm class semiconductor devices. In addition to a significant burden in terms of thermal budget, such as very deterioration of the cell / junction characteristics, the epitaxial layer grows only on the areas where the selective epitaxial growth is exposed. It is a big disadvantage that there is a limit to increase the doping concentration because the flow rate of the dopant gas (PH 3 ) can not be increased. In other words, in order to selectively grow the epitaxial layer, the flow rate of the dopant gas must be reduced, thereby making it difficult to obtain a high doping concentration.

The present invention has been proposed to solve the above problems of the prior art, and provides a method for forming a contact of a semiconductor device capable of increasing the contact area without increasing the contact area and interfacial oxide film and increasing the concentration of the dopant. There is a purpose.

Another object of the present invention is to provide a semiconductor device having a contact with reduced contact resistance.

Contact forming method of the present invention for achieving the above object comprises the steps of forming a plurality of gate patterns on a semiconductor substrate; Forming a first spacer on sidewalls of the gate pattern; Forming a first contact layer having a thickness partially filling the gate patterns; Forming a second spacer on an upper sidewall of the gate pattern exposed by the first contact layer; Forming an interlayer insulating film having a contact hole exposing the first contact layer; And forming a second contact layer embedded in the contact hole, wherein the first contact layer and the second contact layer are formed using a solid state epitaxy (SPE) process. The first and second contact layers may be any one epitaxial layer selected from epitaxial silicon, epitaxial germanium, and epitaxial silicon germanium formed by the solid phase epitaxy process. The epitaxial layer is characterized in that the dopant having a doping concentration in the range of 1.0 × 10 19 to 1.0 × 10 22 atoms / cm 3 is doped.

In addition, the semiconductor device of the present invention is a semiconductor substrate; A plurality of gate patterns formed on the semiconductor substrate; First spacers formed on both sidewalls of the gate pattern; A first contact layer having a thickness partially filling the gate patterns; A second spacer formed on the first contact layer in contact with the first spacer; And a second contact layer formed on the second contact layer, wherein the first and second contact layers are epitaxial layers formed by solid phase epitaxy, wherein the epitaxial layer is 1.0. × 10 19 ~ to a 1.0 × 10 22 atoms / cm characterized in that the dopant having a doping concentration range of 3 doping.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A and 2B illustrate a concept of a solid phase epitaxy process according to an exemplary embodiment of the present invention. Solid phase epitaxy (SPE) process is a process that can be applied to the existing semiconductor device manufacturing process as it is, low-temperature process and can satisfy the high concentration doping concentration.

Referring to FIGS. 2A and 2B, a solid phase epitaxy process for growing an epitaxial silicon layer is described as follows.

First, as shown in FIG. 2A, a SiH 4 gas as a silicon source and a PH 3 gas as a doping gas are simultaneously injected onto an exposed silicon substrate 11 subjected to pretreatment to form an amorphous silicon layer (at a temperature of 450 to 650 ° C.). 13) to grow. In this case, in the initial deposition state (As-deposited), the first epitaxial silicon 12 is formed on the bottom surface, and as the deposition proceeds, the amorphous silicon 13 is formed on the first epitaxial silicon 12.

For example, the solid-phase epitaxy process for growing the first epitaxial silicon 12 and the amorphous silicon 13 is performed by supplying a mixed gas of SiH 4 / PH 3 in a H 2 gas atmosphere with a pressure of 150torr to 200torr and 450 to 650 It proceeds at the temperature of ° C, but the flow rate of SiH 4 is 500sccm to 800sccm, and the flow rate of PH 3 is at least 100sccm or more (100sccm to 250sccm). As such, the amorphous silicon 13 keeps the doping concentration of phosphorus (P) in the amorphous silicon 13 at 1.0 × 10 19 to 1.0 × 10 22 atoms / cm 3 by flowing the doping gas PH 3 during growth. .

As described above, the deposition equipment for growing the amorphous silicon 13 by a solid-phase epitaxy process includes reduced pressure CVD (RPCVD), low pressure CVD (LPCVD), very low pressure CVD (VLPCVD), plasma enhanced CVD (PECVD), and UHVCVD. (Ultra High Vacuum CVD), Rapid Thermal CVD (RTCVD), Atmosphere Pressure CVD (APCVD) or Molecular Beam Epitaxy (MBE).

On the other hand, the reason why the first epitaxial silicon 12 is grown in the initial deposition state during the solid-phase epitaxy process, the vacuum is loaded on the amorphous layer deposition equipment (eg, amorphous silicon deposition equipment) without time delay after the pretreatment process Vacuum loading is the first reason. In the pretreatment process, if SPM (H 2 SO 4 : H 2 O 2 = 1:20 @ 90 ℃) and 300: 1 BOE are used for cleaning, the surface of the semiconductor substrate is hydrogen-terminated (silicon dangling on the surface of the silicon substrate). The bond (dangling bond is bonded to the hydrogen atom) is suppressed the growth of the natural oxide film for a certain time. As such, since the natural oxide film is suppressed, the first epitaxial silicon 12 is grown at the beginning of the solid phase epitaxy. The second reason is that the atmosphere gas introduced for depositing the amorphous silicon 13 is H 2 gas. That is, by using H 2 gas, the gaseous atmosphere becomes a reducing atmosphere instead of an oxidizing atmosphere in the solid phase epitaxy process, and the epitaxial silicon 12 is initially formed even in the deposition state of the amorphous silicon 13 by the reducing atmosphere. It is growing.

The amorphous silicon layer 13 grown as described above is immediately followed by a thermal process (500-700 ° C., 30 minutes to 10 hours) at a relatively low temperature as shown in FIG. 2B. Regrowth from the interface to the second epitaxial silicon layer 13A.

As a result, high quality first and second epitaxial silicon 12 and 13A are grown on the silicon substrate 11 without interfacial oxide film, and the doping concentration of phosphorus (P) in the epitaxial silicon is 1.0 × 10 19 to 1.0 ×. It is maintained at 10 22 atoms / cm 3 level.

Regrowth to the second epitaxial silicon layer 13A, paradoxically, means that almost no interfacial oxide film was formed, which is proved in FIG. 3.

FIG. 3 shows the results of quantitative analysis of oxygen elements (existence of interfacial oxide film) at each interface of epitaxial silicon by polysilicon and solid phase epitaxy. The horizontal axis is depth and the vertical axis is oxygen concentration (18O Conc.).

Referring to FIG. 3, the interfacial oxygen concentration of solid phase epitaxy (Epi-Si (SPE)) is nearly 100 times lower than that of polysilicon (LP Poly) at a depth of 2000 μs (polysilicon is 10 18 , Solid phase epitaxy is 10 16 ), and in particular, solid phase epitaxy does not show oxygen peaks at the interface. As a result, it can be seen that the solid phase epitaxy formed at a low temperature of 610 ° C is excellent in terms of the interfacial oxide film.

In addition, the solid-phase epitaxy is a non-selective epitaxial growth process unlike SEG, which can greatly increase the flow rate of PH 3 gas, which is a doping gas. For example, when injected at a flow rate of PH 3 gas of 200 sccm, the doping concentration of phosphorus has a very high concentration of 7.0 x 10 20 atoms / cm 3 .

Although the epitaxial silicon 32 used as the contact material is formed by using the above-described solid phase epitaxy (SPE) process, the contact material formed by the solid phase epitaxy process includes germanium (Ge) and silicon germanium (in addition to silicon). SiGe) is also applicable. That is, epitaxial germanium and epitaxial silicon germanium can also be formed.

The present invention is to reduce the contact resistance by increasing the contact area of the contact region, by depositing an epitaxial layer doped with a high concentration of dopant at a low temperature using a solid-phase epitaxy process as shown in FIG.

The contact resistance of the semiconductor device can be greatly reduced only by the solid phase epitaxy process having a high concentration of doping concentration, but if the contact area is increased up to this, the final contact resistance can be further reduced.

The method of increasing the contact area in the present invention relates to a spacer formed on the sidewall of the gate pattern. Detailed description will be described later.

4A through 4E are cross-sectional views illustrating a method of forming a contact of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 4A, after the gate insulating film 22 is formed on the semiconductor substrate 21, the gate electrode 23 and the gate hard mask 24 are sequentially stacked on the gate insulating film 22. Here, the gate electrode 23 can be laminated with polysilicon, polysilicon and tungsten, and the gate hard mask 24 is formed of a silicon nitride film.

Subsequently, gate patterning is performed to form a gate pattern. In this case, the gate pattern has a structure in which the gate electrode 23 and the gate hard mask 24 are stacked.

Subsequently, after depositing an insulating film used as a gate spacer, spacer etching is performed to form gate spacers 25 on both sidewalls of the gate pattern. At this time, the gate insulating film 22 is also etched to expose the surface of the semiconductor substrate 21 between the gate patterns.

As shown in FIG. 4B, a pretreatment process is performed on the exposed semiconductor substrate 21 between the gate patterns to remove etch residues.

Preferably, the pretreatment process proceeds with both dry and wet cleaning. Wet cleaning proceeds with HF-last (HF for last) cleaning, and dry cleaning may include plasma, thermal, and cleaning using reactive gases. In addition, the wet cleaning proceeds at a temperature of room temperature (27 ° C) to 150 ° C and the dry cleaning proceeds at a temperature of 100 to 850 ° C.

For example, HF-last cleaning may include RNO [R (H 2 SO 4 + H 2 O 2 ) + N (NH 4 OH + H 2 O 2 ) + O (HF series BOE)], RNF [R (H 2 SO 4 + H 2 O 2 ) + N (NH 4 OH + H 2 O 2 ) + HF], RO, NO, RF cleaning. Here, R is also called SPM.

The gas used in the dry cleaning process by the plasma process uses hydrogen, hydrogen / nitrogen mixed gas, CF series gas, NF series gas, and NH series gas. For example, hydrogen (H 2 ), hydrogen / nitrogen (H 2 / N 2 ), nitrogen fluoride (NF 3 ), ammonia (NH 3 ), and CF 4 are used.

By this pretreatment step, a clean interface is obtained in which no interface oxide film is formed at the interface between the subsequent first contact layer and the semiconductor substrate 21. Since the interfacial oxide film is disadvantageous in terms of contact resistance, its formation must be suppressed.

The above-described series of pretreatment processes proceed continuously without time delay to maintain the clean state of the exposed portion, and deposit the first contact layer 26 without time delay after the pretreatment process.

That is, the first contact layer 26 is formed on the exposed semiconductor substrate 21 so as to gap fill the gate patterns. The first contact layer 26 is formed using a solid phase epitaxy (SPE) process (completed up to the process of proceeding to the thermal process to regrow the epitaxial layer). By using a solid phase epitaxy process, not only a low temperature process but also a high phosphorus doping concentration can be obtained, and a high quality epitaxial layer having almost no interfacial oxide film can be formed.

The first contact layer 26 is selected from epitaxial silicon (Epi-Si), epitaxial germanium (Epi-Ge), or epitaxial silicon germanium (Epi-SiGe). The first contact layer 26 may include low pressure CVD (LPCVD), very low pressure CVD (VLPCVD), plasma enhanced-CVD (PE-CVD), ultrahigh vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD), and APCVD. (Atmosphere Pressure CVD) or MBE (Molecular Beam Epitaxy) in any one of the deposition equipment is deposited using a solid-phase epitaxy process.

The deposition temperature of the first contact layer 26 is low temperature of 450 to 650 ℃. In addition, the first contact layer 26 may dopant the dopant in situ using a doping gas during deposition. In this case, the doping gas uses PH 3 , and the dopant doped by the doping is phosphorous (Phosphorous). P) and the concentration of phosphorus (P) is in the range of 1.0 × 10 19 to 1.0 × 10 22 atoms / cm 3 . Unlike the SEG, the solid phase epitaxy process is a non-selective epitaxial growth process, so that the flow rate of the doping gas PH 3 gas can be greatly increased. For example, when injected at a flow rate of PH 3 gas of 200 sccm, the doping concentration of phosphorus has a very high concentration of 7.0 x 10 20 atoms / cm 3 .

As such, when the first contact layer 26 is formed before the formation of the subsequent cell spacer, the contact area of the first contact layer 26 in contact with the semiconductor substrate (source region or drain region) is reduced by the cell spacer, that is, 20 to 20. You can increase it by 50%.

Subsequently, the first contact layer 26 is etched with etchback to remain at a predetermined thickness between the gate patterns. At this time, the thickness of the first contact layer 26 remaining after the etchback is in the range of 200 to 1200 kPa.

As shown in FIG. 4C, an insulating film used as a cell spacer is deposited on the entire surface and then etched back to form a cell spacer 27 on the upper sidewall of the gate pattern on the first contact layer 26. do. For example, the cell spacers 27 are formed on the gate spacers 25 formed on both sidewalls of the gate pattern.

The cell spacer 27 serves to prevent diffusion of impurities in the interlayer insulating film, which are increased in a subsequent process, toward the gate electrode.

Preferably, the cell spacer 27 is formed by proceeding in the order of nitride film deposition and etch back. Thus, the cell spacer is also referred to as Cell Spacer Nitride (CSN).

Although not shown before forming the cell spacer 27, junction ion implantation is performed to form the source region and the drain region of the transistor in the peripheral region.

As shown in FIG. 4D, an interlayer insulating film 29 is formed on the entire surface. At this time, the interlayer insulating film 29 is formed of an oxide film such as BPSG, and is formed until a sufficient gap fill between the gate patterns.

In addition, before the interlayer insulating layer 29 is formed, an etching barrier layer 28 that serves as an etching barrier in a subsequent self-aligned contact etching process is first formed. Preferably, the etching barrier film 28 is formed of a nitride film.

Subsequently, the interlayer insulating layer 29 is etched to stop the etching in the etching barrier layer 28 through self-aligned contact etching (SAC), and the etching barrier layer 28 is subsequently etched. In the self-aligned contact etching, a contact mask 30 using a photosensitive film is used as a contact etching process for forming the contact hole 31.

Through the self-aligned contact etching as described above, a contact hole 31 for opening the surface of the first contact layer 26 is formed.

As shown in FIG. 4E, after removing the contact mask 30, a pretreatment process for removing etch residues is performed. Preferably, the pretreatment process proceeds with both dry and wet cleaning. Wet cleaning proceeds with HF-last (HF for last) cleaning, and dry cleaning may include plasma, thermal, and cleaning using reactive gases. The wet cleaning proceeds at a temperature of room temperature to 150 ° C and the dry cleaning proceeds at a temperature of 100 to 850 ° C.

By this pretreatment process, a clean interface is obtained in which no interface oxide film is formed at the interface between the first contact layer 26 and the subsequent second contact layer 32. Since the interfacial oxide film is disadvantageous in terms of contact resistance, its formation must be suppressed.

Subsequently, a second contact layer 32 is formed on the interlayer insulating film 29 to fill the contact hole 31. In this case, the second contact layer 32 is deposited by the same material and the same method as the first contact layer 26.

For example, the second contact layer 32 is selected from silicon (Si), germanium (Ge), or silicon germanium (SiGe). The second contact layer 32 may include low pressure CVD (LPCVD), very low pressure CVD (VLPCVD), plasma enhanced-CVD (PE-CVD), ultrahigh vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD), and APCVD. (Atmosphere Pressure CVD) or MBE (Molecular Beam Epitaxy) is deposited in any one of the deposition equipment.

The second contact layer 32 is deposited to a thickness of 200-2000 kPa, and the deposition temperature is in the range of 450-650 占 폚. In addition, the second contact layer 32 may dop the dopant in-situ during deposition, wherein the dopant is phosphorous (P), and the concentration of phosphorus (P) is 1.0 × 10 19 to 1.0. It is a range of x 10 22 atoms / cm 3 .

In addition, the second contact layer 32 may be formed of a tungsten film in addition to the solid phase epitaxy material. In this case, in order to improve contact resistance by forming ohmic contact between the first contact layer 26 and the second contact layer 32, a metal silicide is formed in advance and a tungsten film is deposited. . For example, the metal silicide may be titanium silicide, cobalt silicide or tungsten silicide.

In addition, the second contact layer 32 may be formed by stacking a material by solid phase epitaxy and a tungsten film.

Subsequently, the etch back and chemical mechanical polishing are sequentially performed to leave the second contact layer 32 only inside the contact hole 31. When the second contact layer 32 is a tungsten film, only the etch back process may be performed.

The semiconductor device according to the embodiment of the present invention from the results of FIG. 4E includes a contact formed by stacking the first contact layer 26 and the second contact layer 32.

When the structure of the semiconductor device is summarized in detail, a gate insulating film 22 is formed on the semiconductor substrate 21, a plurality of gate patterns formed on the gate insulating film 22 are formed, and gate spacers are formed on both sidewalls of the gate pattern. 25 is formed. Here, the gate pattern is a stack of the gate electrode 23 and the gate hard mask 24.

The first contact layer 26 is formed to partially fill the gap between the gate patterns, and the cell spacer 27 is formed on the first contact layer 26 in contact with the gate spacer 25. Here, the gate spacer 25 and the cell spacer 27 are nitride films.

The second contact layer 32 is formed on the first contact layer 26. Of course, the second contact layer 32 is formed in the contact hole 31 inside the interlayer insulating film 29.

The first and second contact layers 26 and 32 are epitaxial layers by solid phase epitaxy, or the first contact layer 26 is an epitaxial layer by solid phase epitaxy, and the second contact layer 32 is It is a metal film. Here, the epitaxial layer is any one selected from epitaxial silicon, epitaxial germanium or epitaxial silicon germanium, and has a doping concentration in the range of 1.0 × 10 19 to 1.0 × 10 22 atoms / cm 3 . Is doped.

According to the embodiment described above, the present invention has a wider contact area by forming the cell spacer 27 after the first contact layer 26 is formed, and thus the first contact layer 26 is in contact with the semiconductor substrate 21. The contact area of the one contact layer 26 can be increased.

In order to increase the concentration of dopant phosphorus in the solid phase epitaxy process, the PH 3 gas flow rate is increased to at least 100 sccm or more to fill the contact region in contact with the semiconductor substrate 21 only with an epitaxial layer having almost no interfacial oxide film. In addition, by filling the low-temperature epitaxial layer with a high concentration of phosphorus dopant in a wider contact area, it is possible to greatly improve contact resistance, device reliability, and yield in future next-generation semiconductor devices.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has the effect of not only obtaining a high dopant concentration by forming a contact using a solid phase epitaxy process but also forming a contact without an interfacial oxide film.

In addition, the present invention has the effect of reducing the contact resistance by implementing a wider contact area by the first contact layer by performing the cell spacer process after forming the first contact layer.

As a result, the present invention can not only significantly reduce contact resistance, but also improve reliability and yield.

Claims (34)

Forming a plurality of gate patterns on the semiconductor substrate; Forming a first spacer on sidewalls of the gate pattern; Forming a first contact layer having a thickness partially filling the gate patterns; Forming a second spacer on an upper sidewall of the gate pattern exposed by the first contact layer; Forming an interlayer insulating film having a contact hole exposing the first contact layer; And Forming a second contact layer embedded in the contact hole Contact forming method of a semiconductor device comprising a. The method of claim 1, The method of claim 1, wherein the first contact layer and the second contact layer are formed using a solid state epitaxy (SPE) process. The method of claim 2, The first and second contact layer, The method for forming a contact of a semiconductor device, which is an epitaxial layer selected from epitaxial silicon, epitaxial germanium, and epitaxial silicon germanium formed by the solid phase epitaxy process. The method of claim 3, Forming the epitaxial silicon, Growing first epitaxial silicon and amorphous silicon using a silicon source gas and a doping gas; And Thermally growing the amorphous silicon into second epitaxial silicon; Contact forming method of a semiconductor device comprising a. The method of claim 4, wherein The step of growing the first epitaxial silicon and amorphous silicon, A method for forming a contact for a semiconductor device which proceeds at a low temperature of 450 to 650 ° C. The method of claim 4, wherein The silicon source gas uses a SiH 4 gas, and the doping gas uses a PH 3 gas. The method of claim 6, The PH 3 gas is injected at a flow rate of 100 to 250 sccm so that the doping concentration of phosphorus (P) doped into the first and second epitaxial silicon is in a range of 1.0 × 10 19 to 1.0 × 10 22 atoms / cm 3. Method for forming a contact of a device. The method of claim 4, wherein The thermal process is a contact forming method of a semiconductor device to proceed for a time of 30 minutes to 10 hours at a temperature of 500 ~ 700 ℃. The method of claim 2, The solid-phase epitaxy process includes LPCVD (Low Pressure CVD), VLPCVD (Very Low Pressure CVD), PE-CVD (Plasma Enhanced-CVD), UHVCVD (Ultrahigh Vacuum CVD), RTCVD (Rapid Thermal CVD), APCVD (Atmosphere Pressure CVD). Method for forming a contact of a semiconductor device proceeding in any one of the deposition equipment selected from) or MBE (Molecular Beam Epitaxy). The method according to any one of claims 1 to 9, Forming the first contact layer to a thickness partially filling the gate pattern, Forming a first contact layer on the exposed semiconductor substrate to gap-fill the gate patterns; And Partially remaining between the gate patterns through an etch back; Contact forming method of a semiconductor device comprising a. The method of claim 10, And the first contact layer after the etch back is left in a thickness of 200 to 2000 micrometers. The method according to any one of claims 1 to 9, And a pretreatment step prior to forming the first contact layer and before forming the second contact layer, respectively. The method of claim 12, The pretreatment step is a contact forming method of a semiconductor device that performs both dry cleaning and wet cleaning. The method of claim 13, The wet cleaning proceeds to HF-last cleaning, and the dry cleaning uses a plasma process, a thermal process, or a cleaning process using a reactive gas. The method of claim 14, The wet cleaning proceeds at a temperature of room temperature to 150 ° C., and the dry cleaning proceeds at a temperature of 100 to 850 ° C. 16. The method according to any one of claims 1 to 9, And forming the first and second spacers as a nitride film. The method of claim 1, Forming the second contact layer, Forming the second contact layer on the interlayer insulating layer to fill the contact hole; And Sequentially performing etch back and chemical mechanical polishing on the second contact layer. Contact forming method of a semiconductor device comprising a. The method of claim 17, And wherein said second contact layer is formed by laminating a substance and a metal film by solid phase epitaxy. The method of claim 19, The second contact layer, The method for forming a contact of a semiconductor device, which is an epitaxial layer selected from epitaxial silicon, epitaxial germanium, and epitaxial silicon germanium formed by the solid phase epitaxy process. The method of claim 17, And the second contact layer is formed of a metal film. The method of claim 18 or 20, And the metal film is a tungsten film. The method of claim 20, And forming a metal silicide before forming the second contact layer. The method of claim 22, The metal silicide, Method of forming a contact of a semiconductor device, which is any one selected from titanium silicide, cobalt silicide or tungsten silicide. Semiconductor substrates; A plurality of gate patterns formed on the semiconductor substrate; First spacers formed on both sidewalls of the gate pattern; A first contact layer having a thickness partially filling the gate patterns; A second spacer formed on the first contact layer in contact with the first spacer; And A second contact layer formed on the second contact layer Semiconductor device comprising a. The method of claim 24, The first and second contact layer, A semiconductor device which is an epitaxial layer by solid phase epitaxy. The method of claim 24, And the first contact layer is an epitaxial layer by solid phase epitaxy, and the second contact layer is a metal film. The method of claim 24, And the first contact layer is an epitaxial layer by solid phase epitaxy, and the second contact layer is a stack of an epitaxial layer and a metal film by solid phase epitaxy. The method according to any one of claims 25 to 27, The epitaxial layer is, A semiconductor device which is any one selected from epitaxial silicon, epitaxial germanium or epitaxial silicon germanium. The method of claim 28, The epitaxial layer is, A semiconductor device doped with a dopant having a doping concentration in the range of 1.0 × 10 19 to 1.0 × 10 22 atoms / cm 3 . The method of claim 26 or 27, The metal film is a tungsten film. The method of claim 24, The first contact layer is a semiconductor device 200 ~ 1200Å thick. The method of claim 26, A semiconductor device in which a metal silicide is inserted between the first contact layer and the second contact layer. 33. The method of claim 32, The metal silicide, A semiconductor device which is any one selected from titanium silicide, cobalt silicide or tungsten silicide. The method of claim 24, The first and second spacers are nitride films.
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