KR20080088860A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20080088860A
KR20080088860A KR1020070031688A KR20070031688A KR20080088860A KR 20080088860 A KR20080088860 A KR 20080088860A KR 1020070031688 A KR1020070031688 A KR 1020070031688A KR 20070031688 A KR20070031688 A KR 20070031688A KR 20080088860 A KR20080088860 A KR 20080088860A
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KR
South Korea
Prior art keywords
active region
ion implantation
threshold voltage
semiconductor device
dopant
Prior art date
Application number
KR1020070031688A
Other languages
Korean (ko)
Inventor
김성연
Original Assignee
주식회사 하이닉스반도체
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070031688A priority Critical patent/KR20080088860A/en
Publication of KR20080088860A publication Critical patent/KR20080088860A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)

Abstract

A method for fabricating a semiconductor device is provided to avoid a phenomenon that a threshold voltage is decreased to a predetermined value or lower by compensating for dopants for adjusting a threshold voltage that is lost at the edge of an active region by a segregation phenomenon at the edge of an active region in contact with an isolation layer. An isolation layer(22) for defining an active region is formed in a substrate(21). An ion implantation buffer layer(26) is formed on the substrate. The ion implantation buffer layer is selectively etched at the edge of the active region in contact with the isolation layer. Dopants for adjusting a threshold voltage are ion-implanted. An annealing is performed to activate the ion-implanted dopants.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

Figure 1a is a plan view showing a semiconductor device according to the prior art.

1B is a cross-sectional view of a semiconductor device according to the prior art along the line II ′ shown in FIG. 1A;

2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

3 is a plan view showing a semiconductor device manufactured according to the semiconductor device manufacturing method of the present invention.

      *** Explanation of symbols for main parts of drawing ***

21 semiconductor substrate 22 device isolation film

23: active area 23A: active area edge

24: threshold voltage control layer 25: gate

25A: gate insulating film 25B: gate electrode

26: ion implantation buffer membrane

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method of manufacturing a semiconductor device suitable for preventing a phenomenon in which a threshold voltage decreases from an expected value by a segregation phenomenon of a threshold voltage dopant. It is about.

Recently, development of high technology for integration and miniaturization of semiconductor devices has been actively performed. With the development of such high technology, there should be no deterioration in the electrical characteristics of semiconductor devices such as threshold voltage.

1A is a plan view of a semiconductor device according to the related art, and FIG. 1B is a cross-sectional view taken along the line II ′ of FIG. 1A.

Referring to FIG. 1A, an active region 13 in which a semiconductor device is to be formed is defined by the device isolation region 12, and a plurality of gates 16 crossing the upper portion of the active region 13 are formed. .

Subsequently, referring to FIG. 1B, the active region 13 is defined by an isolation layer 12 formed by using a shallow trench isolation (STI) process in a predetermined region of the semiconductor substrate 11. A threshold voltage adjusting layer 14 including a dopant for adjusting the threshold voltage is formed under the surface of the semiconductor substrate 11 in the active region 13. Since the threshold voltage adjusting layer 14 is where the channel is formed, it is typically formed by ion implantation of boron (B). In addition, during the ion implantation process for forming the threshold voltage control layer 14, the process is generally performed to have the same doping profile throughout the active region 13. The gate insulating film 15A is formed in the selected region on the semiconductor substrate 11, and the gate electrode 15B is formed on the gate insulating film 15A.

Here, in the heat treatment process for activating the ion implanted boron to form the threshold voltage adjusting layer 14 of the semiconductor device, the threshold voltage adjusting layer (13A) at the edge 13A of the active region in contact with the device isolation film 12 14, a large amount of boron is diffused toward the device isolation film 12, and boron segregation occurs in which the diffused boron is segregated in the device isolation film. Looking at the doping profile of the threshold voltage control layer 14 of the semiconductor device in which boron segmentation occurs, the boron doping density at the active region edge 13A is lower than the boron doping density of the active region. As described above, the threshold voltage of the semiconductor device is reduced at the edge of the threshold voltage control layer 14 where the doping density of boron is reduced due to boron segmentation, that is, at the edge 13B of the active region in contact with the device isolation layer 12. Occurs. Such local threshold voltage reduction has a problem that the threshold voltage of the entire semiconductor device is reduced, resulting in deterioration of the electrical characteristics of the device.

The present invention has been proposed to solve the above problems of the prior art, and provides a method of manufacturing a semiconductor device suitable for preventing the phenomenon that the threshold voltage is lower than the expected value by the segmentation phenomenon of the threshold voltage dopant. The purpose is.

The semiconductor device manufacturing method of the present invention for achieving the above object is to form a device isolation film defining an active region on the substrate and to form an ion implantation buffer on the substrate and the edge of the active region in contact with the device isolation film In part, the method includes selectively etching the ion implantation buffer and ion implanting a dopant for adjusting the threshold voltage. In addition, the method may further include a heat treatment step for activating the dopant by the ion implantation.

In the method of manufacturing a semiconductor device, when the ion implantation buffer layer is etched, only a partial thickness of the ion implantation buffer layer may be etched.

The substrate of the active region of the present invention may include a dopant for adjusting the threshold voltage, and the substrate of the edge portion of the active region in contact with the device isolation layer may have a relatively high concentration of dopant.

As such, the doping density of the threshold voltage control dopant is made higher at the edge of the active region in contact with the device isolation layer in which the segmentation phenomenon occurs than in the active region, thereby compensating the dopant lost by the segmentation at the edge of the active region. The phenomenon that the voltage decreases can be prevented.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

As shown in FIG. 2A, an ion implantation buffer layer 26 is formed on the semiconductor substrate 21 on which the device isolation layer 22 is formed.

The ion implantation buffer layer 26 is implanted in a subsequent threshold voltage control dopant (ex. Boron) ion implantation process to form the threshold voltage control layer 24 under the surface of the semiconductor substrate 21 in the active region 23. It controls the doping density of the dopant and prevents damage to the semiconductor substrate.

The device isolation layer 22 may be formed using a shallow trench isolation (STI) process. A method of forming a device isolation film using a general STI process is performed by depositing a pad oxide film (not shown) and a pad nitride film (not shown) on a semiconductor substrate 21, and then performing a device isolation mask (not shown) process and etching process. A trench (not shown) having a depth is formed. Next, sidewall oxidation is performed in order to remove defects in the trench sidewalls generated during the etching process, and then the gap inside the trench formed after the trench etching is gap-filled with an insulating material and planarized through a CMP process. Next, the pad oxide film (not shown) and the pad nitride film (not shown) are removed. Through this series of processes, the device isolation layer 22 may be formed.

Subsequently, as shown in FIG. 2B, a hard mask pattern 27 is formed on the ion implantation buffer layer 26 so that the edge of the active region is exposed. The hard mask pattern 27 may serve as an etch barrier during the subsequent etching process of the ion implantation buffer layer 26.

The hard mask pattern 27 may be formed of a material that can be used as an etch barrier of the ion implantation buffer layer 26, for example, when the ion implantation buffer layer is an oxide film.

In the method of forming the hard mask pattern 27 using the nitride film, a nitride film is deposited on the ion implantation buffer layer 26 and a mask defining the size of the active region is smaller than the size of the set active region 23. The hard mask pattern 27 may be formed by etching the nitride layer to expose the edge portion 23A of the active region in which the segmentation phenomenon occurs.

Subsequently, as shown in FIG. 2C, the ion implantation buffer film 26 exposed by the hard mask pattern 27 is etched.

When the ion implantation buffer layer 26 is etched, the etch rate of the ion implantation buffer layer 26 is adjusted so that the edge of the active region where segmentation occurs more than the ion implantation buffer layer thickness of the active region 23 ( The thickness of the ion implantation buffer film in the portion 23A) can be made smaller. That is, only a part of the thickness of the ion implantation buffer film at the edge portion 23A of the active region may be etched. As such, by controlling the thickness of the ion implantation buffer, the doping profile in the active region may be adjusted during the ion implantation process for forming the subsequent threshold voltage control layer.

As the etching method of the ion implantation buffer film 26, the wet etching method and the dry etching method may be used alone or in combination of the two methods.

Subsequently, as shown in FIG. 2D, after removing the hard mask pattern 27, the threshold voltage adjusting layer 24 is ion-implanted with a dopant for adjusting the threshold voltage under the surface of the semiconductor substrate 21 of the active region 23. To form. In this case, the ion implantation process conditions, for example, ion implantation energy may vary depending on the thickness of the ion implantation buffer layer 26. For example, when the thickness of the ion implantation buffer film is 200 mW, the ion implantation energy can be 40 KeV.

According to the present invention, since the thickness of the ion implantation buffer layer 26 between the active region 23 and the edge portion 23A of the active region is different from each other, the amount of the dopant for adjusting the threshold voltage implanted into the semiconductor substrate 21 can be formed differently. have. That is, since the thickness of the ion implantation buffer film in the portion 23A of the active region is smaller than that of the active region 23, more threshold voltage dopants may be implanted in the portion 23A of the active region. Therefore, the doping density of the portion 23A of the active region 23 may be higher than that of the active region 23.

As such, the doping density of the edge portion 23A of the active region is formed high enough to compensate for the threshold voltage dopant lost by the segmentation phenomenon, so that the threshold voltage is adjusted even when the segmentation phenomenon occurs. The doping profile of layer 34 can be kept constant.

The threshold voltage dopant may be selected from boron (B), boron difluoride (BF 2 ), phosphorus (P) and arsenic (As).

Lastly, as shown in FIG. 2E, after the ion implantation buffer film 26 is removed, the gate insulating film 25A and the gate electrode 25B are formed. Here, before forming the gate insulating layer 25A and the gate electrode 25B, a heat treatment process for activating the ion implanted dopant may be performed to form the threshold voltage control layer 24. The gate insulating film 25A and the gate electrode 25B can be formed through a known method of manufacturing a semiconductor device.

3 is a plan view showing a semiconductor device manufactured according to the semiconductor device manufacturing method of the present invention.

As shown in FIG. 3, an active region 23 in which a semiconductor device is to be formed is defined by the device isolation layer 22, and a plurality of gates 25 crossing the upper portion of the active region are formed. Here, the threshold voltage regulating layer 24 formed below the surface of the semiconductor substrate 21 of the active region 23 has an active region 23 having a constant doping density and an active region edge 23A having a higher doping density than the active region. ) Is formed.

As such, the doping density for the threshold voltage control dopant at the active region edge 23A higher than the active region 23 is generated during the heat treatment process for activating the ion implanted threshold voltage control dopant and in the manufacturing process of other semiconductor devices. Due to the different heat treatment process, the dopant for adjusting the threshold voltage lost by the segmentation phenomenon at the edge 23A of the active region in contact with the device isolation layer 22 is compensated, resulting in the doping of the threshold voltage adjusting layer 34. You can keep the profile constant. Therefore, it is possible to prevent the phenomenon that the threshold voltage is lower than the expected value by the segmentation phenomenon.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

The present invention described above compensates the dopant for adjusting the threshold voltage lost at the edge of the active region by the segmentation phenomenon at the edge of the active region in contact with the device isolation layer, thereby preventing the phenomenon of the threshold voltage being lower than the expected value. There is.

Claims (6)

Forming an isolation layer defining an active region on the substrate; Forming an ion implantation buffer layer on the substrate; Selectively etching the ion implantation buffer layer at an edge portion of the active region in contact with the device isolation layer; And Ion implantation of dopant for threshold voltage control Method of manufacturing a semiconductor device comprising a. The method of claim 1, The method of manufacturing a semiconductor device further comprising a heat treatment step for activating the dopant by the ion implantation. The method of claim 1, The ion implantation buffer film is a semiconductor device manufacturing method, characterized in that formed by the oxide film. The method of claim 3, wherein The selective etching of the ion implantation buffer film is a semiconductor device manufacturing method, characterized in that using a nitride mask pattern. The method of claim 1, When etching the ion implantation buffer film, a method of manufacturing a semiconductor device, characterized in that for etching only a part of the thickness of the ion implantation buffer film. The method of claim 1, The substrate of the active region includes a dopant for adjusting the threshold voltage, and the substrate of the edge portion of the active region in contact with the device isolation layer has a relatively high concentration of the dopant.
KR1020070031688A 2007-03-30 2007-03-30 Method for fabricating semiconductor device KR20080088860A (en)

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Application Number Priority Date Filing Date Title
KR1020070031688A KR20080088860A (en) 2007-03-30 2007-03-30 Method for fabricating semiconductor device

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KR1020070031688A KR20080088860A (en) 2007-03-30 2007-03-30 Method for fabricating semiconductor device

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