KR20080079905A - Delayed locked loop, and method of controlling the initial delay time - Google Patents

Abstract

A delay locked loop capable of controlling initial delay time and a method for synchronizing delay are provided to control the initial delay time by using a user control signal. A phase detector(302) outputs a control signal corresponding to a phase difference by detecting the phase difference between an external clock and an internal clock. An initial delay time control part(306) outputs a delay control signal to control initial delay time determined by the number of operations of an initial delay cell, by receiving a user control signal inputted by a user. A delay circuit(308) comprises a plurality of post delay cells connected to the initial delay cell serially, and determines the initial delay time by controlling the number of operations of the initial delay cell according to the delay control signal by receiving the delay control signal and the external clock, and outputs the internal clock delayed by the initial delay cell and the post delay cells.

Description

Delayed locked loop, and method of controlling the initial delay time}

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a structure of a conventional delay lock loop.

2 is a diagram illustrating a structure of a delay cell of a conventional delay lock loop.

3 is a diagram illustrating a structure of a delay cell of a delay lock loop according to the present invention.

4 is a diagram illustrating a structure of a delay lock loop according to the present invention.

5 illustrates a structure of a delay lock loop according to an embodiment of the present invention.

6 is a diagram illustrating a structure of an internal control signal output unit according to an exemplary embodiment of the present invention.

7 is a timing diagram illustrating a signal of an internal control signal output unit according to an exemplary embodiment of the present invention.

8 is a diagram illustrating a structure of an initial delay time determining unit according to an embodiment of the present invention.

9A and 9B are views illustrating a structure of a driving voltage setting unit according to an embodiment of the present invention.

10 is a truth table of a driving voltage setting unit according to an embodiment of the present invention.

11 is a flowchart of a delay synchronization method according to an embodiment of the present invention.

The present invention relates to a delay lock loop and a delay lock method, and more particularly, to a delay lock loop and a delay lock method for adjusting an initial delay time by a user control signal.

1 is a diagram illustrating a structure of a conventional delay lock loop.

The conventional delay lock loop includes a phase detector 102, a delay control unit 104, and a delay circuit 106. The phase detector 102 receives an internal clock Int_CLK synchronized with the external clock Ex_CLK by an external clock Ex_CLK and a delay lock loop, and detects a phase difference between the external clock Ex_CLK and the internal clock Int_CLK. Then, a control signal indicating the phase difference is output to the delay control unit 104. The delay control unit 104 outputs a control signal for increasing or decreasing the delay time of the clock to the delay circuit 106 according to the control signal for the phase difference input from the phase detector 102. The delay circuit 106 receives a control signal input from the delay controller 104 and an external clock Ex_CLK as an input. The control signal input from the delay control unit 104 is input to each delay cell of the delay circuit so that the delay time is determined according to the control signal input from the delay control unit 104 when the external clock Ex_CLK passes through the delay cells. The external clock Ex_CLK is delayed to synchronize the external clock Ex_CLK with the internal clock Int_CLK. The internal clock Int_CLK becomes the output of the delay lock loop and is input back to the phase detector 102 by feedback.

2 is a diagram illustrating a structure of a delay cell of a conventional delay lock loop.

Delay circuit 106 includes a plurality of delay cells 202, 204,..., 218. An external clock Ex_CLK is delayed while passing through the plurality of delay cells 202, 204,..., 218, and the delayed external clock Ex_CLK is output as an internal clock Int_CLK. Some of the plurality of delay cells are initial delay cells, and thus the delay time is fixed and cannot be changed by the control signal. Delay cells 202, 204, ..., 216 from 0 to M in FIG. 2 are initial delay cells, and the delay time is fixed. That is, when the delay time is adjusted from the control signal output from the delay control unit 104, the delay time is changed by adjusting the delay cell after M times. The delay time of each delay cell can be adjusted by the driving voltage. For example, the clock may not be delayed when the delay cell has the first voltage level 220 as the driving voltage, and the clock may be delayed when the delay cell has the second voltage level 222 as the driving voltage. Therefore, the delay time of the external clock Ex_CLK can be changed in the delay circuit 106 by adjusting the driving voltage of each delay cell.

However, when a delay time shorter than the initial delay time is desired, the fixed initial delay time cannot be reduced by hardware, which causes a problem in that the external clock Ex_CLK is not synchronized with the internal clock Int_CLK.

In addition, there is a need for a delay synchronization loop that can adjust the initial delay time under user control.

An object of the present invention is to provide a delay lock loop and a delay lock method for changing an initial delay time fixed in hardware.

Another object of the present invention is to provide a delay lock loop and a delay lock method for adjusting an initial delay time by a user control signal.

A delay lock loop for achieving the above technical problem includes a phase detector, an initial delay time controller, and a delay circuit. The phase detector detects a phase difference between the external clock and the internal clock and outputs a control signal corresponding to the phase difference. The initial delay time controller receives a user control signal input by a user and outputs a delay control signal for controlling an initial delay time determined by the number of driving of the initial delay cells. The delay circuit includes a plurality of late delay cells connected in series with the initial delay cells, receives the delay control signal and the external clock as inputs, and adjusts the initial number of initial delay cells according to the delay control signal. A delay time is determined and the external clock outputs the internal clock delayed by the initial delay cell and the later delay cells.

The delay lock loop determines whether the user control by the user control signal is possible according to whether the number of driving of the initial delay cell can be increased, and outputs an internal control signal corresponding to the user control. The apparatus further includes a signal output unit, wherein the initial delay time controller performs the initial delay time control by the user control signal in a user controllable state corresponding to the internal control signal, and controls the user in a user control impossible state. The initial delay time control by the signal may not be performed. The user controllability is user controllable when there is an undriven initial delay cell and the number of driving of the initial delay cell can be increased, and user control when the number of driving of the initial delay cell cannot be increased. It can be judged impossible.

The internal control signal output unit may determine that user control is impossible when a pulse having the same logic state is continuously output from the phase detector more than a predetermined number of times and the number of driving of the initial delay cell cannot be increased. In addition, when the user control is impossible, the initial delay time may be set to a predetermined value.

A delay synchronization method for achieving the above technical problem includes a phase difference detection step, an initial delay time control step, and an internal clock output step. The phase difference detecting step detects a phase difference between an external clock and an internal clock and outputs a control signal corresponding to the phase difference. The initial delay time control step receives a user control signal input by a user and outputs a delay control signal for controlling an initial delay time determined by the number of driving of the initial delay cells. The internal clock output step receives the delay control signal and the external clock as inputs by using a plurality of late delay cells connected in series with the initial delay cells, and adjusts the number of driving of the initial delay cells according to the delay control signals. The initial delay time is determined, and the external clock outputs the internal clock delayed by the initial delay cell and the later delay cells.

The delay synchronization method determines whether the user can control the user by a user control signal according to whether the number of driving of the initial delay cell can be increased and outputs an internal control signal corresponding to the user control. The method may further include a signal output step, wherein the initial delay time control step may include: performing the initial delay time control by the user control signal in a user controllable state corresponding to the internal control signal; The initial delay time control by the user control signal may not be performed. The user controllability is user controllable when there is an undriven initial delay cell and the number of driving of the initial delay cell can be increased, and user control when the number of driving of the initial delay cell cannot be increased. It can be judged impossible.

The internal control signal output step may be determined to be non-user control when a pulse having the same logic state is output continuously for a predetermined number of times or more from the phase difference detection step, and the number of driving of the initial delay cell cannot be increased. . If the user control is impossible, the initial delay time may be set to a predetermined value.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects attained by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a diagram illustrating a structure of a delay cell of a delay lock loop according to the present invention.

The present invention is characterized in that the initial delay time can be controlled by controlling whether the initial delay cell, which is fixed in the related art, is driven by a control signal of a user. The initial delay cell refers to a predetermined number of delay cells on the side to which an external clock Ex_CLK is input among a plurality of delay cells connected in series. In FIG. 3, cells 0 through M (402, ..., 416) correspond to initial delay cells according to the present invention. The present invention adjusts the driving voltage of each delay cell according to a control signal input by a user, thereby controlling the number of initial delay cells to be driven. The driving voltage variable parts 420 of the initial delay cells are each adjusted by a user control signal. In addition, the Q_Fi signal is used to indicate the state of the initial delay cells. For example, if the Q_Fi signal is high, the i-th initial delay cell is not driven and no delay is caused by the i-th cell. If the Q_Fi signal is low, the i-th initial delay cell is driven and the i-th cell is driven. This may indicate that the external clock is delayed.

The initial delay time refers to a delay time controlled by the initial delay cell. In the conventional case, the initial delay time could not be changed because the initial delay cell was fixed, and a delay time shorter than the initial delay time could not be obtained. The present invention allows the initial delay time to be variable, so that a delay time shorter than the initial delay time can be obtained.

The late delay cells M + 1 (not shown) to X delay cells 418 are controlled by the control signal output from the phase detector in the same manner as the conventional delay lock loop.

4 is a diagram illustrating a structure of a delay lock loop according to the present invention.

The delay lock loop according to the present invention includes a phase detector 302, an internal control signal output 304, an initial delay time controller 306, and a delay circuit 308.

The phase detector 302 receives an external clock Ex_CLK and an internal clock Int_CLK as inputs, detects a phase difference between the two signals, and controls a signal for synchronizing the external clock Ex_CLK and the internal clock Int_CLK according to the phase difference. Output (DN) The internal clock Int_CLK is input to the phase detector 302 by feedback from the output of the delay circuit. The phase detector 302 is identical to the phase detector 302 provided in the conventional delay lock loop.

The internal control signal output unit 304 receives the DN signal output from the phase detector 302 and the Q_Fi signal output from the delay circuit 308 and receives user control signals MUP and MDN from the initial delay time controller 306. Outputs an internal control signal DN4 indicating whether initial delay time control is possible.

The initial delay time controller 306 determines whether the user control is possible according to the DN4 signal output from the internal control signal output unit 304, and when the initial delay time control is possible according to the user control signal, the driving voltage of the initial delay cells Outputs the FBi signal to determine. When the initial delay time control by the user control signal is impossible, the FBi signal for setting the initial delay time to a predetermined value is output. The FBi signal determines the driving voltage of the I-th initial delay cell. The user control signal includes an initial delay time increasing signal (MUP) and an initial delay time decreasing signal (MDN).

The delay circuit 308 determines the initial delay time according to the driving voltages of the initial delay cells determined by the FBi output from the initial delay time controller, receives the external clock Ex_CLK, and receives the initial delay time and the late delay cells M. The internal clock Int_CLK is delayed by delaying the external clock Ex_CLK by the sum of the delay times from the +1 th delay cell (not shown) to the X th delay cell 418. Late delay cells are the same in the way that they are controlled by the output of a conventional phase detector 302.

5 illustrates a structure of a delay lock loop according to an embodiment of the present invention.

The phase detector 510 receives an external clock Ex_CLK and an internal clock Int_CLK, and outputs a DN signal for controlling the delay circuit according to the phase difference.

The internal control signal output unit 520 includes a continuous determination unit 522 and a signal output unit 524.

The continuous determination unit 522 receives the DN signal as an input, and determines whether the DN signal has been input at the same logic level more than a predetermined number of times in a row. According to an embodiment of the present invention, the control signal for controlling the delay time is output from the phase detector 510 only when the DN signal is continuously input at the same logic level more than a predetermined number of times. This is to prevent the view that the DN signal is caused by noise when the phase difference does not occur.

An embodiment and a detailed structure of the continuous determiner 522 will be described with reference to FIG. 6B. The continuous determiner 522 may be realized by a predetermined number of flip-flops 642, 644, 646, and 648 connected in series and using a common clock. CLK is a clock common to the delay lock loop, and PVCCH is a driving voltage input to each flip-flop and is a drive voltage common to the delay lock loop. 6B can store up to four clocked DN signals by connecting four flip-flops in series. When the DN signal is generated for four consecutive clocks, the DN, D1, D2, D3, and D4 signals all have an activated logic level. The continuous determiner 522 outputs a predetermined number of Di signals to the signal output unit 524.

The signal output unit 524 receives a DN signal output from the phase detector 510, a Di signal output from the continuous determination unit 522, and a Q_Fi signal output from the delay circuit 540 and receives a predetermined logic operation. As a result, an internal delay signal DN4 indicating whether the initial delay cell can be controlled by the user control signal is output.

The operation and detailed structure of the signal output unit 524 will be described with reference to FIG. 6A. The signal output unit 524 performs an AND operation (618, 620) on the CNT signal indicating whether the DN signal is continuous and the SEL1 signal indicating whether the initial delay cell of the delay circuit 540 is driven to the first delay cell. Outputs a DN4 signal indicating whether the initial delay time can be controlled by the user control signal.

The CNT signal receives D1, D2, D3, and D4 from the continuous determination unit 522 of FIG. 6B, receives a DN signal from the phase detector 510, and performs a NAND operation 612 for D1 and D2. After performing NAND operations 614 on D4, D4, and DN, the outputs of the two NAND operations 612, 614 are NOR operations 616 and output.

For example, the case where the level at which the DN signal is activated is high will be described. When the DN signal outputs a high level pulse four consecutive times, D1, D2, D3, D4, and DN are all high level, and the outputs of the two NAND gates 612 and 614 are all low level. Since the inputs of the NOR gate 616 are all low level, the output of the NOR gate 616 goes high. That is, when the DN is output four times in succession, the CNT has a high level. On the other hand, when the DN signal does not output the high level pulse four times in succession, the low level signal among the D1, D2, D3, D4, or DN signals exists, and at least one of the two NAND gates 612 and 614. One has a high level output. Therefore, the CNT signal has a low level when the DN signal does not have a high level for four clocks in a row.

7A and 7B show the values of CNTs according to D1, D2, D3, D4, and DN. Fig. 7A shows a case where a DN pulse of high level is generated four consecutive clocks. If the DN has a pulse of high level four consecutive clocks, in the fourth pulse of DN, D1, D2, D3, and D4 all have a high level, and a high level appears in the CNT. FIG. 7B shows the case where DN does not have four clock continuous high level pulses. If DN does not have a high level pulse four consecutive times, there is no point in time when DN, D1, D2, D3, and D4 have a high level at the same time, so the CNT continues to have a low level.

The SEL1 signal is obtained by AND operation (624, 626) of the inverting signals of Q_F0 and Q_F1. If the i-th initial delay cell is driven to generate a delay, Q_Fi is low level. If the i-th initial delay cell is not driven and does not cause a delay, Q_Fi is high level. It is assumed that the state is fixed. When the initial delay time by the initial delay cell is driven to the maximum initial delay cell as much as possible, the initial delay time can no longer be increased, in which case the initial delay time control by the user control signal is limited. When driven to one initial delay cell, Q_F1 has a low level and Q_F0 has a high level. Accordingly, the inverting 622 signal of Q_F1 and the output SEL1 of the AND operations 624 and 626 of Q_F0 become high level. When the first delay cell is not driven, both Q_F1 and Q_F0 have a high level. Therefore, the output SEL1 of the AND operations 624 and 626 is at the low level.

The DN4 signal is output by performing an AND operation (618, 620) on the CNT signal and the SEL1 signal. When both SEL1 and CNT are high level, DN4 becomes high level, which corresponds to the case where the initial delay time cannot be adjusted by the user control signal. When the CNT signal or SEL1 is low level, DN4 becomes low level, which corresponds to the case where the initial delay time can be adjusted according to the user control signal.

The initial delay time controller 530 includes an initial delay time determiner 532 and a driving voltage setting unit 534.

The initial delay time determining unit 532 receives the MUP and MDN signals, which are user control signals input by the user, and the DN4 signal output from the internal control signal output unit 520, and controls the driving voltage of the initial delay cell. The control signals DU12 and DU3M are output.

The operation and detailed structure of the initial delay time determiner 532 will be described with reference to FIG. 8. The initial delay time determiner 532 outputs n control signals DU12 and DU3M for controlling driving voltages of the n initial delay cell groups having a predetermined number of initial delay cells. An embodiment of the initial delay time determiner 532 illustrated in FIG. 8 divides and adjusts the plurality of initial delay cells into two groups. The DU12 signal controls the driving voltages of the first and second initial delay cells, and the DU3M signal controls the driving voltages from the third delay cell to the M delay cells. The MDN signal input by the user is an initial delay time increasing signal, and the MUP signal is an initial delay time decreasing signal. DU12 is a signal obtained by performing an NAND operation 804 on the inverting 802 signals of the MDN and MUP, and an OR operation 806 and 808 on the DN4 signal. The DU3M signal is a signal obtained by performing an NOR operation 812 on the inverting 802 signals of the MDN and the MUP, and an OR operation 814 and 816 on the DN4 signal.

In one embodiment of the present invention, the user control signal may be a Test Mode Register Set (TMRS) signal or a fuse signal.

10 is a truth table showing DU12, DU3M, and FBi signals according to DN4, MDN, and MUP. The initial state is that DU12 is high level and DU3M is low level. An operation of the circuit of FIG. 8 illustrating an embodiment of the initial delay time determiner 532 will be described with reference to FIG. 10. If DN4 is high level, the outputs of the two OR operations 806, 808 and 814, 816 are high level so that both the DU12 and DU3M signals are high level. This means that all of the initial delay cells are not driven so that no delay occurs due to the initial delay cells, which will be described later. When DN4 is low level, DU12 and DU3M signals are determined according to MDN and MUP. When both MDN and MUP are low level or high level, DU12 and DU3M have the same value as the previous state. If MDN is low level and MUP is high level, DU12 and DU3M have high level and FBi both have low level, reducing the initial delay time than the initial state. If MDN is high level and MUP is low level, the initial delay is longer than the initial state because DU12 and DU3M are low level and FBi are both high level. The relationship between DU12, DU3M, and FBi will be described later.

The driving voltage setting unit 534 receives the DU12 and DU3M signals output from the initial delay time determining unit 532 and receives an FBi signal, which is a control signal for determining driving voltages of initial delay cells of the delay circuit 540, from the delay circuit. Output to 540. The operation and detailed structure of the driving voltage setting unit 534 will be described with reference to FIGS. 9A and 9B.

9A illustrates a structure in which an FBi output output from the driving voltage setting unit 920 is input to an initial delay cell. The driving voltage setting unit 920 receives the DU12 and DU3M signals output from the initial delay time determining unit 532 and outputs FB1 to FBM which are control signals for determining driving voltages of the initial delay cells.

9B illustrates a detailed structure of an embodiment of the driving voltage setting unit 920. The initial delay cells are controlled by using the first and second initial delay cells as the first group and the 3 to M initial delay cells as the second group. DU12 controls the initial delay cells of the first group, and FB1 to FB2 are determined by DU12. According to the embodiment of FIG. 9B, when DU12 is high level, FB1 to FB2 are inverted three times from DU12, respectively (942, 944, and 946; 942, 944, and 948, respectively) and have a low level of 1 The first to second initial delay cells are not driven so that no delay occurs. When DU12 is at the low level, FB1 to FB2 have a high level, and the first to second initial delay cells are driven to cause a delay by the first to second cells. DU3M works with the same logic as DU12.

In the case where DN4 is high level in FIG. 10, since the FBi is all low level, no delay caused by the initial delay cell occurs. Therefore, if DN4 is high level, the delay lock loop delay is set to the state starting from the M + 1th cell.

The delay circuit 540 outputs the internal clock Int_CLK by delaying the external clock Ex_CLK by the initial delay cells and the late delay cells as shown in FIG. 3.

11 is a flowchart illustrating a delay synchronization method according to an embodiment of the present invention.

In the phase difference detecting step, a phase difference between the external clock Ex_CLK and the internal clock Int_CLK is detected using a conventional phase detector (S1002), and a control signal corresponding to the phase difference is output (S1004).

The internal control signal output step determines whether the initial delay time can be increased according to the current state of the delay circuit 540 (S1006). That is, when the initial delay cells controlled by the user control signal are not all driven and the initial delay time can be increased by the user control signal, the initial delay time is regarded as a user controllable state capable of increasing the initial delay time.

If all of the initial delay cells controlled by the user control signal are driven and thus the initial delay time is not increased (S1006), and a DN pulse having a constant logic state for a predetermined number of consecutive times is output (S1008), the user cannot control the state. In step S1010, the initial delay time is set to a predetermined value. Whether or not a DN pulse having a constant logic state is output continuously for a predetermined number or more is determined using the D1 to D4 signals and the DN signal. Setting the initial delay time to a predetermined value is set by the DN4 signal and the FBi signal.

The internal control signal output step outputs an internal control signal corresponding to a user controllable state or a user controllable state.

In the initial delay time control step, when an internal control signal corresponding to a user controllable state is input, the initial delay time control step receives the user control signal to determine an initial delay time (S1012), and drive voltages of the initial delay cells. Set (S1014) to output a delay control signal for adjusting the initial delay time. When the internal control signal corresponding to the user control impossible state is input, the delay control signal for setting the driving voltage of the initial delay cells is output so that the initial delay time is set to a predetermined value (S1014).

The internal clock output step receives a delay control signal from the initial delay time control step, and determines an initial delay time corresponding to the delay control signal, and according to the output of the phase difference detection step, the delay time of late delay cells is increased according to a conventional method. The external clock Ex_CLK is delayed by the initial delay cells and the late delay cells to output the internal clock Int_CLK synchronized with the external clock Ex_CLK (S1016).

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, in the delay lock loop and the delay lock method according to the present invention, a delay time shorter than a conventional initial delay time can be obtained by changing an initial delay time fixed in hardware. In addition, a delay time longer than the sum of the conventional initial delay time and the delay times of the delay cells after the initial delay cell can be obtained.

Claims (18)

A phase detector for detecting a phase difference between an external clock and an internal clock and outputting a control signal corresponding to the phase difference; An initial delay time controller receiving a user control signal input by a user and outputting a delay control signal for controlling an initial delay time determined by the number of driving of the initial delay cells; And The initial delay time is provided by having a plurality of late delay cells connected in series with the initial delay cells, receiving the delay control signal and the external clock as inputs, and adjusting the number of driving of the initial delay cells according to the delay control signal. And a delay circuit that is determined and wherein the external clock outputs the internal clock delayed by the initial delay cell and the late delay cells. The method of claim 1, The delay synchronization loop may determine whether the user control is possible by the user control signal according to whether the number of driving of the initial delay cell can be increased, and output an internal control signal corresponding to the user control. Further comprising a control signal output unit, The initial delay time controller performs the initial delay time control by the user control signal when the user control is possible in response to the internal control signal, and the initial delay by the user control signal when the user control is impossible. No time control, Whether the user can control the User controllable when there is an undriven initial delay cell to increase the number of drives of the initial delay cell; And when it is impossible to increase the number of driving of the initial delay cell, determining that user control is impossible. The method of claim 2, The internal control signal output unit may determine that user control is impossible when a pulse having the same logic state is continuously output from the phase detector for a predetermined number of times or more and the number of driving of the initial delay cell cannot be increased. Delayed synchronous loop. The method of claim 3, The internal control signal output unit includes a flip-flop connected in series and sequentially transmits a control signal output from a phase detector through the flip-flop, and determines whether the flip-flops output the same logic state. Delayed synchronous loop. The method of claim 2, And, if the user control is impossible, set the initial delay time to a predetermined value. The method of claim 1, The initial delay cells may be a predetermined number of consecutive delay cells located on the side to which the external clock is input, not controlled by a control signal output from the phase detector among the plurality of delay cells connected in series. Delayed synchronous loop. The method of claim 1, The user control signal includes an initial delay time increasing signal and an initial delay time decreasing signal, The initial delay increasing signal increases the number of driving of the initial delay cells, and the initial delay decreasing signal reduces the number of driving of the initial delay cells. The method of claim 1, The user control signal is a delay lock loop, characterized in that the Test Mode Register Set (TMRS) signal. The method of claim 1, And the user control signal is a fuse signal. Detecting a phase difference between an external clock and an internal clock and outputting a control signal corresponding to the phase difference; An initial delay time control step of receiving a user control signal input by a user and outputting a delay control signal for controlling an initial delay time determined by a driving number of an initial delay cell; And By using the plurality of late delay cells connected in series with the initial delay cells, the delay control signal and the external clock are received as inputs, and the initial delay time is adjusted by adjusting the number of driving of the initial delay cells according to the delay control signal. And an internal clock output step of outputting the internal clock, wherein the external clock is delayed by the initial delay cell and the late delay cells. The method of claim 10, The delay synchronization method may determine whether the user can control the user by the user control signal according to whether the number of driving of the initial delay cell can be increased, and output an internal control signal corresponding to the user control. Further comprising a control signal output step, The initial delay time control step may include performing the initial delay time control by the user control signal in a user controllable state corresponding to the internal control signal, and performing the initial delay time control by the user control signal in a user control impossible state. Does not perform latency control, Whether the user can control the User controllable when there is an undriven initial delay cell to increase the number of drives of the initial delay cell; And when it is impossible to increase the number of driving of the initial delay cell, determining that user control is impossible. The method of claim 11, The internal control signal output step may determine that user control is impossible when a pulse having the same logic state is outputted a predetermined number of times consecutively from the phase difference detection step, and the number of driving of the initial delay cell cannot be increased. Delay synchronization method. The method of claim 12, The internal control signal output step may include using flip-flops connected in series, sequentially transmitting control signals output from a phase detector through the flip-flops, and determining whether the flip-flops output the same logic state. Delay synchronous method. The method of claim 11, And in case of no user control, set the initial delay time to a predetermined value. The method of claim 10, The initial delay cells may be a predetermined number of consecutive delay cells located on the side to which the external clock is input, not controlled by a control signal output from the phase detector among the plurality of delay cells connected in series. Delay synchronization method. The method of claim 10, The user control signal includes an initial delay time increasing signal and an initial delay time decreasing signal, And the initial delay increasing signal increases the number of driving of the initial delay cells, and the initial delay decreasing signal reduces the number of driving of the initial delay cells. The method of claim 10, The user control signal is a delay synchronization method, characterized in that the TMS (Test Mode Register Set) signal. The method of claim 10, And the user control signal is a fuse signal.

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