KR20080079492A - Method of forming semiconductor device having bi-layer gate electrode - Google Patents

Abstract

A method for forming a semiconductor device having a bi-layer gate electrode is provided to implement a flash memory device having high erase efficiency and excellent data retention by increasing a work function of a control gate electrode. A tunnel dielectric(15) is formed on a semiconductor substrate(11). A charge trap layer(17) is formed on the tunnel dielectric. A shield dielectric(19) is formed on the charge trap layer. A first conductive layer is formed on the shield dielectric. Chlorine treatment is performed on the first conductive layer to form a Cl doped conductive layer(21'). A second conductive layer(25) is formed on the Cl doped conductive layer. The chlorine treatment is performed by exposing the semiconductor substrate having the first conductive layer to a Cl plasma atmosphere. The charge trap layer is formed with a nitride layer. A thickness of the first conductive layer is 1 nm to 10 nm. The second conductive layer is formed with a material layer having a work function of 4.5 eV to 6.0 eV.

Description

Method of forming a semiconductor device having a double gate electrode {Method of forming semiconductor device having bi-layer gate electrode}

1 to 5 are cross-sectional views illustrating a method of forming a semiconductor device having a double gate electrode according to an exemplary embodiment of the present invention.

** Description of the symbols for the main parts of the drawings **

11 semiconductor substrate 12 active region

13: device isolation film

15: tunnel dielectric film 15P: tunnel dielectric pattern

17: charge trap film 17P: charge trap pattern

19: shielding dielectric film 19P: shielding dielectric pattern

21: first conductive film

21 ': Cl doped conductive film

21P: first conductive pattern

25: second conductive film

25P: Second Conductive Pattern

26G: control gate electrode

27: mask pattern

29: source / drain area

The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a control gate electrode of a flash memory device.

Semiconductor memory devices that store data may be classified into volatile memory devices and nonvolatile memory devices. The volatile memory device loses stored data when the power supply is cut off, while the nonvolatile memory device retains stored data even when the power supply is cut off. Accordingly, the nonvolatile memory device, for example, a flash memory device, is widely used in a mobile storage device or a mobile telecommunication system.

Techniques for implementing the flash memory device are classified into a floating gate type and a charge trap type according to the type of memory storage layer constituting the unit cell. In the conventional flash memory device market, the floating gate type has been mainstream. However, since the floating gate type memory device is stored in a conductive pattern such as polysilicon, the floating gate type memory device is also affected by a small defect in the tunnel dielectric layer, thereby causing a problem in data retention.

On the other hand, a silicon-oxide-nitride-oxide-silicon (SONOS) device, which is a charge trap type memory device using a nitride film such as a silicon nitride film as a memory storage layer, has recently been published.

The SONS device includes tunnel dielectrics, charge trap layers, and blocking dielectrics that are sequentially stacked on a semiconductor substrate. A control gate electrode is disposed on the shield dielectric layer. The charge trap film uses a non-conductive material film such as a silicon nitride film.

The write operation of the sonos device may include injecting electrons from the semiconductor substrate into the charge trap layer by applying a positive write voltage to the control gate electrode. Since the charge trap layer is a non-conductive material layer, movement of the injected electrons is not free. Therefore, since the sonos device is less susceptible to defects in the tunnel dielectric layer, the sonos device exhibits excellent data retention.

An erase operation of the SONOS device may include grounding the control gate electrode and applying a positive erase voltage to the semiconductor substrate. The shielding dielectric layer may serve to block electrons from flowing into the charge trap layer from the control gate electrode during the erase operation.

In the method for efficiently blocking the inflow of electrons from the control gate electrode to the charge trap layer, a method of adopting a material film having a low leakage current characteristic as the shielding dielectric film and a material having a high work function at the control gate electrode may be employed. There is a way to adopt the membrane.

Accordingly, research into using high-K dielectrics as the shielding dielectric film is actively underway. The high-k dielectric has a thicker physical thickness than the silicon oxide layer, but has an effect equivalent to using a thinner dielectric layer. In other words, the high-k dielectric has relatively better leakage current blocking characteristics than the silicon oxide layer.

However, the high dielectric film reacts with the control gate electrode to form a reaction film between the shielding dielectric film and the control gate electrode. The reaction film increases an equivalent oxide thickness (EOT) of the shielding dielectric film. In addition, the reaction film reduces the work function of the control gate electrode. The decrease in the work function means a decrease in the electron barrier. That is, the reduction of the work function provides a condition in which electrons are easily introduced into the charge trap layer from the control gate electrode. In this case, the SONOS device may malfunction.

In conclusion, it is advantageous to form the control gate electrode to have a high work function.

SUMMARY OF THE INVENTION The present invention has been made in an effort to improve the above-described problems of the related art, and to provide a method of forming a semiconductor device capable of increasing a work function of a control gate electrode.

In order to achieve the above technical problem, the present invention provides a method of forming a semiconductor device having a double control gate electrode. The method includes forming a tunnel dielectric film on a semiconductor substrate. A charge trap layer is formed on the tunnel dielectric layer. A shielding dielectric film is formed on the charge trap film. A first conductive film is formed on the shielding dielectric film. The first conductive film is chlorine treated to form a Cl doped conductive film. A second conductive film is formed on the Cl doped conductive film.

In some embodiments of the present disclosure, the chlorine treatment may include exposing the semiconductor substrate having the first conductive layer to a Cl plasma atmosphere.

In another embodiment, the charge trap layer may be formed of a nitride layer such as a silicon nitride layer.

In another embodiment, the shielding dielectric layer may include HfO, HfSiO, HfAlO, AlO, AlSiO, TiO, BeAlO, CeO, CeHfO, CoTiO, LaO, LaAlO, LaSiO, MgAlO, NdAlO, PrAlO, SrTiO, TaO, YO, YSiO , ZrO, ZrAlO, ZrSiO, SiO and SiON may be formed to include one selected from the group consisting of.

In another embodiment, the first conductive film may be formed to a thickness of 1nm to 10nm. In this case, the first conductive film is made of polysilicon, Ti, TiN, Ta, TaN, W, WN, Hf, Nb, Mo, RuO, MoN, Ir, Pt, Co, Cr, RuO, TiAl, TiAlN, Pd, It may be formed to include one selected from the group consisting of WSi and NiSi.

In another embodiment, the second conductive film may be formed of a material film having a work function of 4.5 eV to 6.0 eV. The second conductive film may be formed thicker than the first conductive film. The second conductive film may be formed of a metal film, a metal silicide film, a metal nitride film, or a combination thereof.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed contents are thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

1 to 5 are cross-sectional views illustrating a method of forming a semiconductor device having a double control gate electrode according to an exemplary embodiment of the present invention.

Referring to FIG. 1, an isolation layer 13 may be formed in a predetermined region of the semiconductor substrate 11 to define an active region 12. The semiconductor substrate 11 may be formed of a silicon wafer or a silicon on insulator (SOI) wafer. The device isolation layer 13 may be formed using a shallow trench isolation (STI) technique. The device isolation layer 13 may be formed of an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

Tunnel dielectrics 15 may be formed on the active region 12. The tunnel dielectric layer 15 may be formed of a silicon oxide layer, a high-k dielectric layer, or a combination thereof. A charge trap layer 17 may be formed on the tunnel dielectric layer 15. The charge trap layer 17 may be formed of a nitride layer such as a silicon nitride layer. Blocking dielectric layers 19 may be formed on the charge trap layer 17.

The shield dielectric layer 19 may be formed relatively thicker than the tunnel dielectric layer 15. In addition, the shield dielectric layer 19 may be formed to have an equivalent oxide thickness (EOT) that is relatively larger than that of the tunnel dielectric layer 15. In addition, the shielding dielectric layer 19 may be formed of a material layer having a low leakage current characteristic. For example, the shield dielectric layer 19 may be formed of HfO, HfSiO, HfAlO, AlO, AlSiO, TiO, BeAlO, CeO, CeHfO, CoTiO, LaO, LaAlO, LaSiO, MgAlO, NdAlO, PrAlO, SrTiO, TaO, YO, YSiO , ZrO, ZrAlO, ZrSiO, SiO and SiON may be formed to include one selected from the group consisting of.

Referring to FIG. 2, a first conductive layer 21 may be formed on the shielding dielectric layer 19. The first conductive layer 21 may be formed to a thickness of 1nm to 10nm. The first conductive film 21 is made of polysilicon, Ti, TiN, Ta, TaN, W, WN, Hf, Nb, Mo, RuO, MoN, Ir, Pt, Co, Cr, RuO, TiAl, TiAlN, Pd, It may be formed to include one selected from the group consisting of WSi and NiSi.

Referring to FIG. 3, a Cl doped conductive film 21 ′ may be formed by chlorine treatment on the first conductive film 21. The chlorine treatment may include exposing the semiconductor substrate 11 having the first conductive layer 21 to a Cl plasma atmosphere.

As a result, the first conductive layer 21 may be divided into a Cl doped region 21B and an undoped region 21A. That is, the Cl doped conductive layer 21 ′ may be formed to include the Cl doped region 21B and the undoped region 21A. In this case, the undoped region 21A may remain between the Cl doped region 21B and the shielding dielectric layer 19.

Alternatively, the Cl doped conductive layer 21 ′ may be formed only with the Cl doped region 21B. In this case, the Cl doped region 21B may contact the shield dielectric layer 19.

As confirmed by the inventors, the Cl doped conductive film 21 ′ was found to have a significantly increased work function compared to the first conductive film 21. That is, the Cl-doped conductive film 21 ′ may be formed to have a higher work function than the first conductive film 21.

Referring to FIG. 4, a second conductive layer 25 may be formed on the Cl doped conductive layer 21 ′. The second conductive layer 25 may be formed relatively thicker than the first conductive layer 21. The second conductive layer 25 may be formed of a material layer having a high work function. For example, the second conductive layer 25 may be formed of a material layer having a work function of 4.5 eV to 6.0 eV. The second conductive layer 25 may be formed of a metal layer, a metal silicide layer, a metal nitride layer, or a combination thereof.

Referring to FIG. 5, a mask pattern 27 may be formed on the second conductive layer 25. The mask pattern 27 may be formed as a photoresist pattern or a hard mask pattern. The mask pattern 27 may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

The second conductive layer 25, the Cl-doped conductive layer 21 ′, the shielding dielectric layer 19, the charge trap layer 17, and the tunnel using the mask pattern 27 as an etching mask. The dielectric layer 15 may be patterned in sequence. The patterning may be performed using an anisotropic etching process.

As a result, the tunnel dielectric pattern 15P, the charge trap pattern 17P, the shielding dielectric pattern 19P, the first conductive pattern 21P, and the second conductive pattern 25P are sequentially stacked on the active region 12. This can be formed. The active region 12 adjacent to both sides of the control gate electrode 26G may be exposed. The first conductive pattern 21P and the second conductive pattern 25P may constitute a control gate electrode 26G.

Subsequently, impurity ions may be implanted into the active region 12 adjacent to both sides of the control gate electrode 26G to form a pair of source / drain regions 29 spaced apart from each other.

The active region 12, the source / drain regions 29, the tunnel dielectric pattern 15P, the charge trap pattern 17P, the shield dielectric pattern 19P, and the control gate electrode 26G may be flashed. The memory device can be configured.

The write operation of the flash memory device is performed by applying a positive write voltage to the control gate electrode 26G to inject electrons from the active region 12 into the charge trap pattern 17P. can do.

The charge trap pattern 17P may be formed of a non-conductive material film such as a silicon nitride film. Therefore, the movement of the electrons injected into the charge trap pattern 17P is not free. Since the flash memory device is less susceptible to defects in the tunnel dielectric pattern 15P, the flash memory device can exhibit excellent data retention.

An erase operation of the flash memory device may be performed by grounding the control gate electrode 26G and applying a positive erase voltage to the active region 12. The shielding dielectric pattern 19P may serve to block electrons from flowing into the charge trap pattern 17P from the control gate electrode 26G during the erase operation.

The control gate electrode 26G may include the first conductive pattern 21P and the second conductive pattern 25P. The first conductive pattern 21P may be interposed between the shielding dielectric pattern 19P and the second conductive pattern 25P. The first conductive pattern 21P may include the Cl doped region 21B. Under the influence of the Cl doped region 21B, the first conductive pattern 21P may have a high work function.

As a result, the control gate electrode 26G may also have a high work function under the influence of the Cl doped region 21B. The fact that the control gate electrode 26G has the high work function means that it is difficult for electrons to flow into the charge trap pattern 17P from the control gate electrode 26G. That is, since the erase efficiency of the flash memory device can be increased, the time required for the erase operation can be shortened.

As described above, according to the present invention, a tunnel dielectric film, a charge trap film, and a shielding dielectric film are sequentially stacked on a semiconductor substrate. The charge trap layer may be formed of a nitride layer. A first conductive film is formed on the shielding dielectric film. The first conductive film is chlorine treated to form a Cl doped conductive film. A second conductive film is formed on the Cl doped conductive film. The Cl doped conductive layer and the second conductive layer may constitute a control gate electrode. The control gate electrode may have a high work function under the influence of the Cl doped conductive film.

As a result, it is possible to implement a flash memory device having high erase efficiency and excellent data retention.

Claims (9)

Forming a tunnel dielectric film on the semiconductor substrate, Forming a charge trap layer on the tunnel dielectric layer, Forming a shielding dielectric layer on the charge trap layer, Forming a first conductive film on the shielding dielectric film, Chlorine treatment of the first conductive film to form a Cl-doped conductive film, And forming a second conductive film on the Cl-doped conductive film. The method of claim 1, The chlorine treatment A method of forming a semiconductor device comprising exposing the semiconductor substrate having the first conductive film to a Cl plasma atmosphere. The method of claim 1, And the charge trap film is formed of a nitride film. The method of claim 1, The shielding dielectric film is HfO, HfSiO, HfAlO, AlO, AlSiO, TiO, BeAlO, CeO, CeHfO, CoTiO, LaO, LaAlO, LaSiO, MgAlO, NdAlO, PrAlO, SrTiO, TaO, YO, YSiO, ZrO, ZrAlO, ZrAlO, ZrOO Forming a semiconductor device, characterized in that formed to include one selected from the group consisting of SiO and SiON. The method of claim 1, The first conductive film is a method of forming a semiconductor device, characterized in that formed in a thickness of 1nm to 10nm. The method of claim 1, The first conductive film is polysilicon, Ti, TiN, Ta, TaN, W, WN, Hf, Nb, Mo, RuO, MoN, Ir, Pt, Co, Cr, RuO, TiAl, TiAlN, Pd, WSi and NiSi Forming a semiconductor device, characterized in that formed to include one selected from the group consisting of. The method of claim 1, And the second conductive layer is formed of a material layer having a work function of 4.5 eV to 6.0 eV. The method of claim 1, And the second conductive film is formed thicker than the first conductive film. The method of claim 1, And the second conductive film is formed of a metal film, a metal silicide film, a metal nitride film, or a combination film thereof.

Images