KR20080076466A - Array substrate and display panel having the same - Google Patents

Abstract

An array substrate and a display panel having the same are provided to maximize the area of a pixel electrode by forming a high sub-electrode and a low sub-electrode of the pixel electrode, of which facing ends are parallel with each other in a line, without application of notch patterns, thereby improving the brightness of a display panel. A pixel electrode(500) has a high sub-electrode(510) and a low sub-electrode(520) distanced from the high sub-electrode and surrounding the high sub-electrode. Facing ends of the high sub-electrode and the low sub-electrode are formed in parallel with each other in a line. First and second data lines(310,320) are distanced from each other in a first direction, and disposed outside the pixel electrode. A gate line(100) is formed outside the pixel electrode in a second direction crossing the first direction. A first transistor is electrically connected to the gate line and the first data line, and electrically connected to one of the high sub-electrode and the low sub-electrode. A second transistor is electrically connected to the gate line and the second data line, and electrically connected to the other of the high sub-electrode and the lower sub-electrode.

Description

Array board and display panel having same {ARRAY SUBSTRATE AND DISPLAY PANEL HAVING THE SAME}

1 is a plan view illustrating unit pixels of a display panel according to an exemplary embodiment of the present invention.

2 is a cross-sectional view taken along the line II ′.

3 is a plan view illustrating the pixel electrode of FIG. 1.

4 is a diagram illustrating a state in which voltages are applied to the unit pixels of FIG. 1.

<Description of the symbols for the main parts of the drawings>

100: gate wiring 300: data wiring

310: first data wire 320: second data wire

400: thin film transistor 410: first transistor

420: second transistor 500: pixel electrode

510: high sub-electrode 520: low sub-electrode

521: first row electrode 522: second row electrode

523: pixel notch pattern 600: opening

610: main opening 620: sub opening

The present invention relates to an array substrate and a display panel having the same, and more particularly, to an array substrate for improving brightness and a display panel having the same.

In general, a liquid crystal display includes a liquid crystal display panel displaying an image using a light transmittance of liquid crystal and a backlight assembly disposed under the liquid crystal display panel to provide light.

The liquid crystal display panel includes an array substrate having thin film transistors and pixel electrodes formed in the unit pixels that are electrically connected to the signal lines, the signal lines defining the plurality of unit pixels that cross each other, and the color filter and the common electrode. And a counter substrate having a liquid crystal layer interposed between the array substrate and the counter substrate. As the liquid crystal array is changed by an electric field formed between the pixel electrode and the common electrode, the liquid crystal display panel may display an image by changing light transmittance.

On the other hand, in the liquid crystal display panel in the vertical alignment mode, the long axis of the liquid crystal molecules is vertically arranged with respect to the substrate while no electric field is applied, and the contrast ratio and the wide viewing angle are excellent.

Recently, in order to further improve the side viewing angle of the liquid crystal display panel in the vertical alignment mode, a method of separating the pixel electrode into two sub-electrodes and applying different voltages to the sub-electrodes is used. That is, the pixel electrode may include a low sub electrode to which a low level voltage is applied and a high sub electrode to which a high level voltage is applied. Accordingly, the wide viewing angle can be realized by dispersing the inclination directions of the liquid crystal molecules in various directions.

On the other hand, the liquid crystal molecules are laid down by an electric field to form a plurality of domains, wherein the liquid crystals lie in different directions to form a singular point that looks like a node between the domains. A pixel open portion is formed in the unit pixel area to separate the high sub electrode and the low sub electrode. Therefore, it is difficult to control the singular point in the pixel open portion. That is, since singular points are irregularly generated, instantaneous afterimages occur in the liquid crystal display panel.

Accordingly, when the vertical alignment mode is applied, a notch structure is applied to the pixel open part to improve the instantaneous afterimage since there is no factor for determining the lying direction of the liquid crystal molecules. As the groove-shaped notch pattern is formed at the edge of the sub-electrode facing the pixel open part, the area of the pixel electrode is reduced. As such, as the area of the pixel electrode is sacrificed in the unit pixel, the luminance of the liquid crystal display panel is lowered.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide an array substrate capable of improving luminance by changing a notch structure of a pixel electrode.

Another object of the present invention is to provide a display panel having the above-described array substrate.

In order to achieve the above object of the present invention, an array substrate according to an embodiment has a high sub electrode and a low sub electrode spaced apart from the high sub electrode to surround the high sub electrode, and the high sub electrode and the low sub electrode face each other. One end of the pixel electrode is formed to be parallel to each other in a straight line, the first and second data wires formed on the outside of the pixel electrode spaced apart from each other in a first direction, and the outside of the pixel electrode in a second direction crossing the first direction. A gate transistor electrically connected to the gate line, the gate line, and the first data line, and a first transistor electrically connected to any one of the high and low sub-electrodes, and electrically connected to the gate line and the second data line. And a second transistor electrically connected to the other of the high and low sub-electrodes. .

In accordance with another aspect of the present invention, a display panel includes an array substrate having a plurality of unit pixels, an opposite substrate facing the array substrate, and a liquid crystal layer interposed between the array substrate and the opposite substrate. It includes. The array substrate has a high sub electrode and a row sub electrode spaced apart from the high sub electrode to surround the high sub electrode, and one end of the high sub electrode and the row sub electrode facing each other is formed in a straight line in a first direction. First and second data wires spaced apart from each other, the first and second data wires spaced apart from each other, a gate wire formed outside the pixel electrode in a second direction crossing the first direction, and electrically connected to the gate wires and the first data wires. A first transistor connected to the one of the high and low sub-electrodes, and electrically connected to the gate line and the second data line, and electrically connected to the other of the high and low sub-electrodes. 2 transistors.

According to such an array substrate and a display panel having the same, the notch structure is removed at opposite ends between sub-electrodes driven with different polarities, thereby maximizing the area of the pixel electrode to further improve the brightness of the display panel.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view illustrating unit pixels of a display panel according to an exemplary embodiment of the present invention. 2 is a cross-sectional view taken along the line II ′.

1 and 2, a display panel according to an exemplary embodiment includes an array substrate, an opposing substrate facing the array substrate, and a liquid crystal layer interposed between the array substrate and the opposing substrate.

The array substrate may include a first base substrate 110, a gate wiring 100, a storage wiring 200, a gate insulating film 120, a data wiring 300, a thin film transistor 400, a protective insulating film 130, and a pixel electrode. 500.

The first base substrate 110 has a flat plate shape and is made of a transparent insulating material.

The gate wiring 100 and the storage wiring 200 are formed on the first base substrate 110 to form the same layer. The gate insulating layer 120 is formed on the first base substrate 110 to cover the gate wiring 100 and the storage wiring 200. The data line 300 is formed on the gate insulating layer 120.

In detail, the gate lines 100 extend in a row direction that is a first direction, and a plurality of gate lines 100 are formed in parallel along a second direction that is perpendicular to the first direction. The data line 300 extends long in the column direction, which is the second direction, to cross the gate line 100, and a plurality of data lines 300 are formed in parallel along the first direction.

As such, as the gate line 100 and the data line 300 are formed to cross each other, a plurality of unit pixels are defined on the first base substrate 110. The thin film transistor 400 and the pixel electrode 500 are formed in each unit pixel. Here, each of the unit pixels preferably has a rectangular shape long in the second direction.

As in the present exemplary embodiment, the data line 300 includes a first data line 310 formed on the left side of the pixel electrode 500 and a second data line 320 formed on the right side of the pixel electrode 500. The first and second data lines 310 and 320 are formed to overlap the left and right portions of the pixel electrode 500, respectively.

The storage wiring 200 extends along the first direction in which the gate wiring 100 extends, and is formed to be disposed between neighboring gate wirings 100. The storage line 200 may be formed to cross the center of each unit pixel. The storage line 200 maintains the voltage applied to the pixel electrode 500 for one frame. For example, a constant voltage, which is a reference voltage, may be applied to the storage wire 200.

For example, the storage wiring 200 may extend from the electrode body portion 210 and the electrode body portion 210 crossing the center of the pixel electrode 500 in the first direction, and extend up and down along the second direction. Leg portion 220 is included. The electrode leg 220 is formed adjacent to the first and second data lines 310 and 320, and is influenced by electrical coupling between the first and second data lines 310 and 320 and the pixel electrode 500. Can be blocked.

The thin film transistor 400 is formed in each unit pixel, and is electrically connected to the gate line 100, the data line 300, and the pixel electrode 500. The thin film transistor 400 serves as a switching element for controlling a voltage charged in the pixel electrode 500.

The thin film transistor 400 is a gate electrode extending from the gate wiring 100, an active pattern formed on the gate insulating layer 120 to overlap the gate electrode, and forming a channel layer, and extending from the data wiring 300. A source electrode overlapping the pattern, and a drain electrode spaced apart from the source electrode to overlap the active pattern. The drain electrode is electrically connected to the pixel electrode 500 through the contact hole 700.

The thin film transistor 400 may include a first transistor 410 electrically connected to the gate line 100 and the first data line 310, and a second electrode electrically connected to the gate line 100 and the second data line 320. Transistor 420.

The protective insulating layer 130 is formed on the gate insulating layer 120 to cover the data line 300 and the thin film transistor 400. The protective insulating layer 130 protects the thin film transistor 400 and flattens the surface. The protective insulating layer 130 may be formed of, for example, an organic film material.

The pixel electrode 500 is formed in each unit pixel, and is formed on the protective insulating layer 130. The pixel electrode 500 may be made of a transparent conductive material. For example, the pixel electrode 500 may be made of indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 500 includes a high sub electrode 510 and a row sub electrode 520 spaced apart from the high sub electrode 510 and surrounding the outer portion. Details thereof will be described later.

The opposing substrate is coupled to face the array substrate, and includes a second base substrate 810, a light blocking film, a color filter, and a common electrode 820.

The second base substrate 810 has the same flat plate shape as the first base substrate 110 and is made of a transparent insulating material.

The light blocking film is formed on a portion of the second base substrate 810 to face the first base substrate 110 to block the movement of light. The light blocking film is formed at a position corresponding to the gate wiring 100, the data wiring 300, and the thin film transistor 400. For example, the light blocking film may have a matrix shape.

The color filter is formed on the second base substrate 810 so as to overlap a predetermined area with the light blocking film. The color filter includes, for example, a red, green, and blue color filter, and each color filter is formed at a position corresponding to the pixel electrode 500 formed in the unit pixel.

The common electrode 820 is formed on the light blocking film and the color filter. The common electrode 800 is made of the same transparent conductive material as the pixel electrode 500.

In addition, the counter substrate further includes a domain divider 830. The domain dividing unit 830 may be an opening pattern formed by etching a part of the common electrode 820. Unlike this, the domain divider 830 may be, for example, a protrusion pattern formed on a part of the common electrode 820. The domain divider 830 may be formed to correspond to the centers of the high and low sub electrodes 510 and 520 forming the pixel electrode 500. Accordingly, the direction of the electric field formed between the common electrode 820 and the pixel electrode 500 is staggered, and the unit pixel area is divided into a plurality of domains.

Meanwhile, the liquid crystal molecules of the liquid crystal layer may not be uniformly arranged at the point divided by the domain dividing unit 830, that is, the point where the domain meets the domain. As such, when the arrangement of the liquid crystal molecules is not uniform at the boundary points of the domains, an afterimage may occur and display quality may deteriorate.

Accordingly, as in the present exemplary embodiment, a plurality of groove or protrusion-shaped common notch patterns 822 may be formed at the edge of the common electrode 820 facing the domain dividing unit 830. The common notch patterns 822 may be spaced apart from each other at uniform intervals. The domain dividing unit 830 is divided into a plurality of regions having the same area by the common notch patterns 822 formed at uniform intervals. The liquid crystal molecules disposed in each domain dividing unit 830 may be uniformly arranged in a left-right symmetry with respect to a region divided by the common notch patterns 822. Accordingly, the image displayed on the display panel does not cause a difference in terms of visibility depending on the direction of viewing the screen.

For the same reason, the common notch patterns 822 may be applied to a part of the opening 600 formed between the sub-electrodes of the array substrate.

The liquid crystal layer is composed of liquid crystals interposed between the array substrate and the counter substrate. The liquid crystals of the liquid crystal layer are rearranged by an electric field formed between the pixel electrode 500 and the common electrode 800. For example, the liquid crystal layer may be formed in a vertical alignment (VA) mode. Due to the liquid crystal layer rearranged by the electric field as described above, the display panel displays an image by adjusting the transmittance of light applied from the outside.

In addition, the display panel may further include a polarizing film for polarizing light supplied from the outside. Specifically, the polarizing film may include a first polarizing film 910 disposed on the outside of the array substrate and a second polarizing film 920 disposed on the outside of the opposing substrate. For example, the first polarization axis of the first polarization film 910 and the second polarization axis of the second polarization film 920 may cross each other perpendicularly.

Hereinafter, the arrangement relationship between the pixel electrode 500 and the opening 600 dividing the pixel electrode 500 will be described in detail.

The pixel electrode 500 includes a high sub-electrode 510 disposed at the center of the unit pixel area and a row sub-electrode 520 that surrounds the outer portion of the high sub-electrode 510. The high and low sub electrodes 510 and 520 may have a symmetrical shape with respect to the virtual center line crossing the center of the unit pixel. For example, the high and low sub electrodes 510 and 520 may have a symmetrical shape with respect to the storage wire 200.

The high sub-electrode 510 may have a V-shaped symmetry with respect to the center line. The row sub-electrode 520 is spaced apart from the high sub-electrode 510 and is formed outside the high sub-electrode 510. The row sub-electrode 520 intersects the gate line 100 and the data line 300 so as to be adjacent to the first row electrode 521 and the first row electrode 521 formed adjacent to the high sub electrode 510. It is divided into a second row electrode 522 formed in the. The first row electrode 521 and the second row electrode 522 are formed to be spaced apart from each other.

The high and low sub electrodes 510 and 520 are formed to be inclined at an angle of about 45 degrees with respect to the first and second directions. The high and low sub electrodes 510 and 520 are connected to one end of the drain electrode of the thin film transistor 400 through the first and second contact holes 710 and 720, respectively.

As in the present exemplary embodiment, each of the sub-electrodes constituting the pixel electrode 500 may be spaced apart from each other, and an opening 600 may be formed between the sub-electrodes in the unit pixel region. In detail, the opening 600 may include a main opening 610 formed between the high sub electrode 510 and the low sub electrode 520 and a sub opening 620 formed at the center of the low sub electrode 520. . That is, the row sub electrode 520 is divided into first and second row electrodes 521 and 522 by the sub opening 620.

The main opening 610 is formed to be inclined at an angle of about 45 degrees with respect to the first and second directions along the extending directions of the high and low sub electrodes 510 and 520. The sub opening 620 may be formed at the center of the row sub electrode 520 along the extending direction of the row sub electrode 520, and may be formed to be inclined at an angle of about 45 degrees with respect to the first and second directions.

Meanwhile, as in the exemplary embodiment of the present invention, the display panel has a 120 120 1G2D structure, that is, a structure in which unit pixels are defined by one gate line 100 and two data lines 300. The display panel as described above may be driven by column inversion. The polarity of the odd-numbered data line 300 and the polarity of the even-numbered data line 300 are opposite to each other based on the data line 300 of the array substrate. That is, data signals having different polarities are applied to the first data line 310 and the second data line 320 that divide the unit pixels.

The data line 300 is electrically connected to the pixel electrode 500 through the thin film transistor 400. As in the present exemplary embodiment, the first transistor 410 electrically connected to the first data line 310 is electrically connected to any one of the high and low sub-electrodes 510 and 520, and is connected to the second data line 320. The second transistor 420 may be electrically connected to the other of the high and low sub electrodes 510 and 520.

Accordingly, the high and low sub electrodes 510 and 520 receive voltages having different polarities through the first and second data lines 310 and 320. For example, a high voltage having a high polarity having a positive polarity is applied to the high sub-electrode 510, and a voltage lower than the first voltage having a negative polarity is applied to the low sub-electrode 520. A low voltage second voltage may be applied.

3 is a plan view illustrating the pixel electrode of FIG. 1.

1 and 3, a detailed shape of the pixel electrode 500 as in the exemplary embodiment of the present invention will be described in detail.

The high sub electrode 510 is surrounded by the main opening 610 so as to be spaced apart from the low sub electrode 520. One end of the high sub-electrode 510 and the low sub-electrode 520 facing each other are formed in parallel and in a straight line. Specifically, one end of the high sub-electrode 510 facing the low sub-electrode 520 extends in a straight line. That is, the outer periphery of the high sub-electrode 510 in contact with the main opening 610 is formed in a straight line. As such, groove-shaped patterns such as the common notch patterns 822 are not formed at the edge of the high sub-electrode 510, and extend in a straight line.

The row sub electrode 520 is divided into the first and second row electrodes 521 and 522 by the sub opening 620.

The first row electrode 521 is formed to be in contact with the main opening 610 so as to be spaced apart from the high sub electrode 510. In detail, one end 521a of the first row electrode 521 facing the high sub-electrode 510 through the main opening 610 is formed in a straight line. The pixel notch patterns 523 are formed on the other end 521b of the first row electrode 521 facing the second row electrode 522 between the sub openings 620. That is, at least one groove is formed in the other end 521b of the first row electrode 521 facing the second row electrode 522 along the length direction.

The second row electrode 522 is formed to contact the sub opening 620 so as to be spaced apart from the first row electrode. In detail, pixel notch patterns 523 are formed on one end 522a of the second row electrode 522 facing the first row electrode 521 through the sub opening 620. That is, at least one groove is formed in the other end 522a of the second row electrode 522 facing the first row electrode 521 along the length direction.

2 and 3, the arrangement of the liquid crystal molecules constituting the liquid crystal layer will be described later for each domain region.

The liquid crystal molecules of the liquid crystal layer are disposed in the vertical alignment mode when no electric field is formed between the pixel electrode 500 and the common electrode 820. In addition, the polarization axes of the first and second polarizing films 920 disposed on the outside of the display panel are perpendicular to each other. At this time, the light polarized in the first direction through the first polarizing film 910 is blocked by the second polarizing film 920 without changing the polarization state by the vertically aligned liquid crystal molecules. Accordingly, the display panel does not transmit light.

On the other hand, when an electric field is formed between the pixel electrode 500 and the common electrode 820, the electric field is formed in the diagonal direction in the domain dividing unit 830. In this case, the liquid crystal molecules arranged around the domain dividing unit 830 are rearranged according to the electric field direction, and the rearranged liquid crystal molecules change the polarization state of the light polarized in the first direction. Accordingly, the second direction component of the light polarized in the first direction passes through the second polarizing film 920, and the display panel transmits the light.

Meanwhile, as described above, the high sub electrode 510 and the low sub electrode 520 on the array substrate are driven with different polarities. Accordingly, an electric field is formed in a vertical direction in the main opening 610 formed between the high sub electrode 510 and the low sub electrode 520, and the liquid crystal molecules disposed around the main opening 610 are vertically aligned. As a result, light polarized in the first direction through the first polarizing film 910 is blocked by the second polarizing film 920 in the main opening 610, and thus cannot pass through the display panel.

In summary, when the vertical electric field is applied to the display panel, the liquid crystal molecules disposed in the main opening 610 formed between the high sub electrode 510 and the low sub electrode 520 do not react, and the first row electrode 521 does not react. ) And the liquid crystal molecules disposed in the sub opening 620 formed between the second row electrode 522 react.

Accordingly, as in the exemplary embodiment of the present invention, the outer edge of the high sub electrode 510 and the one end 521a of the low sub electrode 520 contacting the main opening 610 may be applied without applying the pixel notch patterns 523. It may be formed in a straight line in parallel. This is because the liquid crystal molecules disposed in the main opening 610 do not respond to the electric field, and thus the pixel notch patterns 523 for uniform arrangement of the liquid crystal molecules are not necessary. As such, as the pixel notch patterns 523 are formed only on a portion of the pixel electrode 500, the area of the pixel electrode 500 may be maximized to further improve the luminance of the display image.

4 is a diagram illustrating a state in which voltages are applied to the unit pixels of FIG. 1.

Referring to FIG. 4, as in one embodiment of the present invention, the high sub electrode 510 and the low sub electrode 520 are driven with different polarities. Accordingly, the liquid crystal molecules disposed in the main opening 610 formed between the high sub electrode 510 and the low sub electrode 520 do not react.

The connection relationship between the pixel electrode 500 and the thin film transistor 400 in each unit pixel will be described. The first transistor 410 connected to the first data line 310 is electrically connected to any one of the high and low sub electrodes 510 and 520, and the second transistor 420 connected to the second data line 320 is high. And the other of the row sub electrodes 510 and 520.

Here, the high and low pixel electrodes 510 and 520 disposed in each row and column are driven with polarities that are regularly inverted.

Specifically, the high and low sub-electrodes 510 and 520 in the unit pixels are driven by column inversion, and have different polarities. For example, when the high sub electrode 510 is electrically connected to the first transistor 410 to have a positive polarity voltage, the low sub electrode 520 is electrically connected to the second transistor 420. Can have a voltage of negative polarity. In contrast, when the high sub electrode 510 is electrically connected to the second transistor 420 to have a negative polarity voltage, the low sub electrode 520 is electrically connected to the first transistor 410. It may have a voltage of positive polarity.

As such, when the driving voltage of the high sub electrode 510 has a positive polarity, the driving voltage of the low sub electrode 520 has a negative polarity, and the driving voltage of the high sub electrode 510 is increased. In the case of having a negative polarity, the driving voltage of the row sub-electrode 520 has a positive polarity.

In addition, the high and low sub-electrodes 510 and 520 disposed in each row and column are driven in a dot inversion method, and have different polarities. That is, the high sub electrodes 510 repeatedly have voltages of positive and negative polarities along each column and row. Similarly, the row sub electrodes 520 repeatedly have voltages of negative polarity and positive polarity along each column and row.

As described above, in order for the pixel electrode 500 to be driven in the column or dot inversion method according to the above rule while having the arrangement relationship as shown in FIG. 4, a data signal for driving the column or dot inversion is applied to each data line 300. It is desirable to be. That is, each data line 300 transmits data signals having different polarities for each column. For example, a voltage of positive polarity is applied to the first data wire 310 and a voltage of negative polarity is applied to the second data wire 320.

As described above, the ends of the high sub electrode and the low sub electrode facing each other are formed in parallel in a straight line without applying a notch pattern. As a result, the area of the pixel electrode defining the unit pixel may be maximized to further improve the brightness of the display panel.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (6)

A pixel electrode having a high sub-electrode and a row sub-electrode spaced apart from the high sub-electrode to surround the outer sub-electrode, and one end of the high sub-electrode and the row sub-electrode facing each other in a straight line; First and second data lines spaced apart from each other in a first direction and formed outside the pixel electrode; A gate wiring formed outside the pixel electrode in a second direction crossing the first direction; A first transistor electrically connected to the gate line and the first data line and electrically connected to any one of the high and low sub-electrodes; And And a second transistor electrically connected to the gate line and the second data line and electrically connected to the other of the high and low sub-electrodes. The method of claim 1, wherein the row sub-electrode A first row electrode formed adjacent to the high sub electrode; And And a second row electrode formed to be spaced apart from the first row electrode. The method of claim 2, wherein one end of the first row electrode facing the high sub electrode is formed in a straight line. At least one groove is formed in the other end of the first row electrode facing the second row electrode along a longitudinal direction. The array substrate of claim 2, wherein at least one groove is formed at one end of the second row electrode facing the first row electrode along a length direction. The array substrate of claim 1, wherein the high sub electrode and the low sub electrode are supplied with voltages having different polarities. An array substrate on which a plurality of unit pixels are formed; An opposing substrate facing the array substrate; And A liquid crystal layer interposed between the array substrate and the counter substrate, The array substrate A pixel electrode having a high sub-electrode and a row sub-electrode spaced apart from the high sub-electrode to surround the outer sub-electrode, and one end of the high sub-electrode and the row sub-electrode facing each other in a straight line; First and second data lines spaced apart from each other in a first direction and formed outside the pixel electrode; A gate wiring formed outside the pixel electrode in a second direction crossing the first direction; A first transistor electrically connected to the gate line and the first data line and electrically connected to any one of the high and low sub-electrodes; And And a second transistor electrically connected to the gate line and the second data line and electrically connected to the other of the high and low sub-electrodes.

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