KR20080073308A - Method and apparatus for determining frequency offset in a receiver - Google Patents

Abstract

The disclosed embodiments relate to a method and apparatus for determining the frequency offset in a receiver. The apparatus includes a link circuit (200). The link circuit includes a frequency translator (204, 206) for translating the input signal, a detector (210) for measuring the magnitude of the translated signal, and a controller (220) for determining a maximum value of magnitude of a plurality of magnitudes measured by the detector (210) as a result of controlling the frequency translator (204, 206). The method (400) includes receiving an input signal, mixing the signal with a plurality of frequencies (402), processing the plurality of second signals to generate a plurality of magnitudes and a plurality of associated frequency values, (408) and determining a maximum magnitude from the plurality of magnitudes (416).

Description

METHOD AND APPARATUS FOR DETERMINING FREQUENCY OFFSET IN A RECEIVER}

The present invention generally relates to a communication receiver. More specifically, the invention relates to determining a frequency offset that may exist in a received signal at a receiver.

This section is intended to introduce the reader to various technical aspects that may relate to various aspects of the invention described and / or claimed below. This description is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Thus, it should be understood that these descriptions are to be read in this respect and should not be taken as an acceptance of the prior art.

As most people know, satellite television systems have become more prevalent in the last few years. In fact, since the introduction of digital satellite television in 1994, more than 12 million US homes have become satellite TV subscribers. Most of these subscribers live in single-family homes where satellite dishes are installed and connected relatively easily. For example, this satellite dish can be installed on the roof of a house. To continue this growth, customers often expect more from service each year. As a result, service providers are constantly considering new features such as recording, multi-room operations, bulk high quality content, and so forth, and upgrade accordingly. In recent years, high quality video and audio signals have attracted attention.

High definition signals require greater capacity or bandwidth than the services currently provided in satellite systems. In addition, many high definition services are provided in addition to (but not replacing) the current service. To provide these new services, some service providers are increasing the total capacity of their systems. The capacity can be increased in a number of ways, including increasing the number of available transponders or satellite channels or increasing the number of satellites used. The biggest change for satellite systems is related to changes in the actual communication system specifications.

Recent technological advances allow satellite system service providers to consider increasing capacity by changing system specifications in a number of ways, including using new decoding algorithms such as those produced by MPEG, commonly known as MPEG-4. It became. It is also possible to use more advanced modulation formats, such as eight level phase shift keying (8PSK), which can be found in the specifications generated for digital video broadcast (DVB-S2). The DVB-S2 specification also provides a new error correction system known as low density parity check (LDPC) coding, which allows further system total capacity. Although these changes can increase the capacity in a communication system, they can also change the operating margin and change the receiver design in receiving a signal.

In order to meet the growing expectations of customers, it is still important that these advances do not interfere with the currently expected service behavior. Even in this new and advanced service, one of the parameters that a user may consider important is the time it takes to acquire and change program channels. Channel change time can be significantly affected by changes made to the communication system (ie, lowering the signal to noise ratio (SNR) of the incoming signal and / or increasing the complexity of the modulation format and decoding function). One of the important factors for channel acquisition time is related to determining and correcting the frequency offset. The frequency offset is an offset that exists between the expected reception frequency and the actual reception frequency.

Receiving systems, such as those employed in satellite receivers, typically suffer from frequency offsets caused by system components such as low noise block (LNB) converters, tuners in the satellite receiver, and clock reference errors. . This offset may remain fixed, or may change over time or as the temperature changes. Most of the channel acquisition time is spent determining the frequency offset of the received signal and then providing a means to correct it so that proper signal demodulation can be done.

One current solution to the problem of determining and correcting a frequency offset at a receiver involves the use of a control loop, such as a digital carrier tracking loop, within the digital demodulator. This control loop is adjusted to allow determining the frequency offset at which the loop may exist and in some cases correcting it. However, the efficiency of the carrier tracking loop depends not only on the received signal quality but also on the type of signal being operated. Current systems used in products such as satellite receivers operate in an environment where the SNR is higher than 3 dB and the modulation format is quadrature phase shift keying (QPSK). The frequency offset to be recovered is usually specified to be +/- 5 MHz. Under these circumstances, a typical phase locked loop (PLL) used as a carrier recovery loop cannot find and lock the signal for a full +/- 5 MHz possible frequency offset. The loop in this case will step or tune through several pull-in ranges to cover the entire range of frequency offsets. If the pull-in range for the PLL is +/- 1 MHz, to recover the frequency offset of +/- 5 MHz, the PLL is forcibly retuned in steps of nearly 2 MHz, so that any number of steps are required. It covers the frequency search space. Using the currently available hardware, this procedure can be done relatively quickly, because only five steps are needed to cover the entire range and the signal state allows the PLL to use a relatively large pull-in range. Because it is.

However, the newer satellite transmission specification previously described (eg DVB-S2) has modes that operate at a signal-to-noise ratio of less than 1 dB. The DVB-S2 specification also includes modulation formats with more signal points than in a typical QPSK system. For example, the DVB-S2 specification includes 8-PSK like others. For modes with very low SNR and / or higher type of constellation, the pull-in range of a typical PLL carrier recovery system is a pull-in range of a conventional system to ensure that the loop is locked to a signal rather than background noise. It should be reduced to the range of -in. If the pull-in range is not reduced, the loop can be locked to background noise, resulting in an undesirable no-lock state or a false lock state. In an exemplary case, the pull-in range that needs to be properly locked in a system using the newer satellite transmission specification may be only +/- 50 KHz. Using this small pull-in range, a stepped approach to frequency recovery would require nearly 100 steps. The time it takes to obtain a signal containing a large offset can be significantly increased and the user is likely to think that this time increase is unacceptable.

Accordingly, new methods for determining frequency offsets are desired. In addition, the apparatus for determining the frequency offset preferably includes the ability to correct the frequency offset.

Summary of the Invention

The present invention is directed to determining a frequency offset associated with various processing elements within a communication system. More specifically, the present invention relates to systems and methods for determining frequency offset under various situations, including low signal to noise ratio when using various modulation schemes.

The apparatus of the present invention includes a frequency translator for translating an input signal into a plurality of second signals having different frequencies. The apparatus also includes a detector for measuring the magnitude of the plurality of second signals. The apparatus also includes a controller capable of determining a maximum value of the plurality of magnitudes measured by the detector.

The method of the present invention comprises the steps of receiving an input signal, mixing the signal with a plurality of frequencies to generate a plurality of second signals having different carrier frequencies, the plurality of magnitudes, and the plurality of magnitudes and Processing the second plurality of signals to produce an associated plurality of frequency values. The method also includes determining a maximum size among the plurality of sizes.

Advantages of the present invention will become apparent from the following detailed description and the accompanying drawings.

1 is a block diagram of an exemplary link circuit for a demodulation signal.

2 is a block diagram of a link circuit of the present invention.

3 is a flowchart illustrating a method for determining a frequency offset of the present invention.

The features and advantages of the invention may become more apparent from the following description given by way of example.

One or more specific embodiments of the present invention are described below. To provide a concise description of these embodiments, not all features of an actual implementation are described in this specification. In the deployment of any such practical implementation, as in any engineering or design project, for example, in order to achieve the specific goals of the developer in accordance with system-related constraints and business-related constraints that may differ from one implementation to another. It should be understood that numerous implementation-specific decisions should be made. In addition, while such development efforts may be complex and time consuming, it should nevertheless be appreciated that this may be routine for those skilled in the art to be responsible for the design, manufacture and manufacture of the advantages of the present disclosure.

The following describes a circuit used to receive satellite signals. Other systems used to receive other types of signals (in these systems, signal input may be provided by some other means) may include very similar structures. Those skilled in the art will appreciate that the embodiments of the circuits described herein are only one promising embodiment. As such, in other embodiments the components of this circuit may be rearranged or deleted, or additional components may be added. For example, the disclosed circuits may be configured for use with non-satellite video and audio services as delivered from a cable network with some modifications.

Referring now to FIG. 1, an exemplary link circuit 100 used for digital demodulation is shown. At the input of the circuit, an A / D converter 102 is connected to the frequency translator 104. A numerically controlled oscillator (NCO) 106 is also coupled to the frequency translator 104. The output of the frequency translator 104 is connected to an anti-alias filter 108 and the anti-alias filter 108 is connected to an automatic gain control amplifier block 110. . The output of the AGC amplifier block 110 is connected to a decimator block 112, which is connected to a symbol timing recovery block 114. Finally, the symbol timing recovery block 114 is connected to the carrier tracking loop 116. The link processor 120 is coupled to the NCO 106, the carrier tracking loop 116, and the link memory 122. For clarity, some connections and blocks may be omitted, but those skilled in the art should be able to recognize these omissions. The operation of each of these blocks will be described in more detail below.

The link circuit 100 includes an A / D converter 102 for converting one or more baseband signals transmitted from a tuner (not shown) into digital signals. The digital signal from A / D converter 102 represents a series of samples of one or more baseband signals, where each sample comprises a data word of 10 bits, for example. A clock signal (not shown) is also coupled to the A / D converter to produce the series of samples. This clock signal can come from another source, such as a crystal.

The digital signal from A / D converter 102 is then provided to frequency translator 104. The frequency translator 104 also receives an input signal provided from the NCO 106. The NCO 106 and the frequency translator 104 can shift the input digital signal in accordance with the carrier frequency of the input signal, thereby generating a frequency shifted digital signal. NCO 106 is generally a programmable frequency digital signal source. Control for programming the digital frequency of the NCO 106 may be done by the link processor 120. The frequency translator block 104 and the NCO 106 allow the frequency offset determined by the carrier tracking loop 116 to be removed directly from the circuit located in the link circuit 100. The frequency shifted digital signal output from the frequency translator 104 is provided to the anti-alias filter 108. The anti-alias filter 108 is typically a digital filter used to remove signal energy that is not associated with the desired input signal while essentially passing the desired input signal unaltered.

The filtered digital signal is passed to the AGC block 110. AGC block 110 includes a gain controllable digital signal amplifier and a signal detector. The signal detector is used to measure the magnitude of the signal present in the AGC block 110. Detectors in the AGC block 110 typically detect the total power of the signal over a period of time. The output of the detector in AGC block 110 is connected in a loop as a control signal for the gain controllable digital signal amplifier in a manner that allows the output of the amplifier to be maintained at a constant level.

The AGC block 110 outputs the gain compensated signal from its controllable digital signal amplifier and provides the gain compensated signal to the decimator 112. The decimator 112 effectively determines the sampling rate by removing samples of the gain compensated signal based on the comparison of the sampling rate of the incoming signal with the sample rate required for the symbol timing recovery block 114. Decrease.

The symbol timing recovery block 114 includes a control loop that adjusts the phase of the input decimated signal to optimize the sampling position and optimally detect data symbols transmitted in the input signal. The output of the symbol timing recovery block 114 is then connected to the block containing the carrier tracking loop 116. The carrier tracking loop includes a control loop that can determine and / or correct the phase and / or frequency of the input signal relative to the expected carrier frequency or the correct carrier frequency. The carrier tracking loop 116 can typically determine and correct the carrier frequency without considering the actual values of the symbols.

The output of the carrier tracking loop 116, i.e., the demodulated signal, is passed to a downstream processing block, such as an error correction block (not shown), for further processing.

In operation, the carrier tracking loop 116 determines the frequency offset of the incoming signal. The link processor 120 controls operating parameters of the carrier tracking loop 116, such as loop bandwidth, lock in range, and nominal frequency of the lock in range, as known to those skilled in the art. The carrier tracking loop 116 outputs values, such as a frequency offset and a lock state, determined by the carrier tracking loop 116 to the link processor 120. These values can then be used to also program carrier tracking, for example to step on a nominal frequency in the lock-in range. The link processor 120 may also use values to adjust the frequency programmed in the NCO 106. As noted above, the time it takes for the carrier tracking loop 116 to determine the frequency offset and lock to the carrier frequency of the input signal for the signal as used in newer satellite systems may not be acceptable.

Referring now to FIG. 2, an exemplary link circuit 200 of the present invention is shown. At the input of the circuit, an A / D converter 202 is connected to the frequency translator 204. An oscillator, such as NCO 206, is also coupled to frequency translator 204. The output of the frequency translator 204 is connected to an anti-alias filter 208, and the anti-alias filter 208 is connected to an AGC amplifier block 210. The output of the AGC amplifier block 210 is connected to the decimator block 212, which is connected to the symbol timing recovery block 214. The symbol timing recovery block 214 is connected to the carrier tracking loop 216, and finally the carrier tracking loop block 216 is connected to the error correction block 218. Link processor 220 is coupled to NCO 206, AGC amplifier block 210, carrier tracking loop 216, and link memory 222. For clarity, some connections and blocks may be omitted, but those skilled in the art should be able to recognize these omissions. The operation of each of these blocks will be described in more detail below.

The link circuit 200 includes an A / D converter 202 for converting one or more baseband signals transmitted from a tuner (not shown) into digital signals. The digital signal from the A / D converter 202 represents a series of samples of one or more baseband signals, where each sample contains a 10-bit data word, for example. It is important to note that in this preferred embodiment one or more baseband signals are used as input to the A / D converter 202. However, in other embodiments, the signal (s) provided by the tuner as input to the A / D converter 202 may be located at a frequency near the baseband or at some other intermediate frequency (IF). have.

A clock signal (not shown) is also coupled to the A / D converter to produce the series of samples. This clock signal may be from another source, such as crystal, and / or may also be controlled by the link processor 220. In one embodiment, the link processor 220 may determine the clock rate required for proper processing of the incoming received signal. In another embodiment, sampling at A / D converter 202 may be done at a fixed rate, and processing such as decimating the sampled signal at an appropriate sampling rate may be done in later blocks.

The digital signal from A / D converter 202 is then provided to frequency translator 204. The frequency translator 204 also receives an input signal provided from the NCO 206. The NCO 206 and the frequency translator 204 can shift the input digital signal according to the carrier frequency of the input signal, thereby generating a frequency shifted digital signal. NCO 206 is generally a programmable frequency digital signal source. Control for programming the digital frequency of the NCO 206 may be done by the link processor 220. In some embodiments, control may also be determined in conjunction with or separately from the link processor 220 by the carrier tracking loop 216 (described below). The operating range of the NCO 206 may be specified by its frequency offset adjustment range. This range can be determined using a number of factors, such as the symbol rate of the input digital signal and / or the sampling rate used by the A / D converter 202 to process the input baseband signal. In one embodiment, the frequency translator block 204 and the NCO 206 allow the frequency offset determined by the carrier tracking loop 216 to be removed directly within the circuit located in the link circuit 200. . By correcting the offset in the link circuit 200, it eliminates possible re-tuning of the tuner, which may cause additional undesirable time delays for the user.

The frequency shifted digital signal output from the frequency translator 204 is provided to the anti-alias filter 208. The anti-alias filter 208 is typically a digital filter used to remove signal energy that is not associated with the desired input signal while essentially passing the desired input signal unaltered. Depending on the range of symbol rates of the input signal possible for demodulation in the link circuit 200, the anti-alias filter 208 may be one or more fixed filters or a set of programmable filters. In a preferred embodiment, anti-alias filter 208 may be programmed to change its passband frequency response and / or other characteristics. In another embodiment, this filter may be programmed to match the bandpass characteristics of the frequency shifted input digital signal. One of these passband characteristics may be the signal bandwidth.

The filtered digital signal is passed to the AGC amplifier block 210. The AGC amplifier block 210 includes a gain controllable digital signal amplifier and a signal detector. The detector in AGC amplifier block 210 is used to measure the magnitude of the signal present. The detector detects the total power of the signal over a period of time, for example, as the root mean square (RMS) power. The detector in AGC block 210 may be connected in a loop as a control signal for the gain controllable digital signal amplifier in a manner that allows the output of the amplifier to be maintained at a constant level. In addition, the detector in AGC block 210 may be used to provide an indication of the level of the incoming signal. One output of the detector, i.e. the level indicator signal, may then be sent to the link processor 220 for subsequent processing.

The AGC block 210 outputs the gain compensated signal from its controllable digital signal amplifier and provides the gain compensated signal to the decimator 212. The decimator 212 effectively reduces the sampling rate by removing the samples of the gain compensated signal based on comparing the sampling rate of the input signal with the sample rate required for the symbol timing recovery block 214. Let's do it.

The symbol timing recovery block 214 includes a control loop that adjusts the phase of the input decimated signal to optimize the sampling position and allow selection detection of data symbols transmitted in the input signal. The output of the symbol timing recovery block 214 is coupled to the carrier tracking loop 216. The carrier tracking loop 216 includes a control loop that can determine and / or correct the phase and / or frequency of the input signal relative to the expected carrier frequency or the correct carrier frequency. The carrier tracking loop 216 can make the determination and correction without considering the actual values of the symbols.

Note that the symbol timing recovery block 214 and the carrier tracking loop 216 can be operatively coupled to each other and / or to other blocks within the link circuit 200, as known to those skilled in the art. It is important. In addition, the carrier tracking loop 216 described herein generally includes the foregoing limitations that are unique based on input signal attributes for frequency offsets.

The output of the carrier tracking loop 216, i.e., the de-rotated signal, is input to the error correction block 218. In general, error correction block 218 may include a symbol slicer module for determining actual symbol values. The error correction block 218 can also include a symbol to bit mapper module that is used to generate bits that include data and error correction bits. The error correction block 218 also includes a module for utilizing error correction information transmitted with the data in the input signal. As is known to those skilled in the art, many types of error correction methods may be used in communication systems, such as the systems disclosed herein. Some error correction methods may include Reed-Solomon error correction, trellis error correction, or interleaving. In addition, new types known as turbo code error correction and LDPC error correction may also be used. As is known to those skilled in the art, any of these error correction methods can be used individually or combined to cooperate with each other.

Referring now to FIG. 3, a flowchart 400 for completing the method of the present invention is shown. This flowchart includes steps representing a complete process based on a particular embodiment of the method. Those skilled in the art should appreciate that some steps for accommodating other embodiments may be omitted or exchanged. First, in step 402, the tuner is tuned to receive a channel (e.g., satellite transponder) transmitted from the L-band signal. Further, at step 402, the link circuit 200 may be initialized under the control of the link processor 220. This initialization may include any initialization of registers for use in the NCO 206, the AGC block 210, and the link memory 222. In step 404, anti-alias filter 208 may be programmed to a predetermined bandwidth. If the anti-alias filter 208 does not allow programming of the filter bandwidth, step 404 may be omitted. This bandwidth may be selected based on several criteria, including the input channel, signal quality and / or operating parameters of the input channel, or a possible bandwidth range in the anti-alias filter 208. In one embodiment, the anti-alias filter 208 may be programmed to the smallest possible value, for example 500 KHz. In another embodiment, anti-alias filter 208 may be programmed to a value that is approximately half of the bandwidth of the input channel.

At step 406, the NCO 206 is programmed to a first frequency or starting frequency. This frequency may be selected as the frequency at one end of the possible tuning range of the NCO 206. For example, NCO 206 can be initially tuned to its lowest frequency. The tuning range of the NCO 206 is often chosen to cover a particular frequency range where the input signal may be known to exist when considering the frequency offset. In a preferred embodiment, the tuning range of the NCO 206 is chosen to be in the same frequency range as the Nyquist frequency of the largest bandwidth signal to be received. In other embodiments, the NCO range may be selected to be in a frequency range equal to or greater than the total frequency offset that may occur in the system.

In addition, it will be important that a pattern for tuning the NCO 206 be generated and followed, as this process will need to be stepped through a series of frequencies. For example, in one embodiment, tuning will begin using the lowest frequency as the first frequency, complete tuning using the highest frequency as the final frequency, and step through the set of frequencies between them. In most cases, this pattern may be stored in memory or derived as an algorithm within the link processor 220 before tuning the NCO 206.

After the NCO 206 is initiated at its starting frequency, a measurement of signal strength is performed using the AGC block 210 at step 408. In one embodiment, this measurement may be made using the level indicator output from the aforementioned AGC block 210 coupled to the link controller. In one embodiment, the link controller may use this level indicator output directly as the measured value, while in other embodiments, the link controller performs additional processing, such as averaging two or more samples at different time instances. The measured value can be derived.

In step 410, the measured value from the link processor 220 is stored in a specific place in the memory, such as link memory 222. In addition, the link processor 220 may store an indication of the frequency of the NCO 206 in an individual specific location in the memory. The frequency value can be stored in any useful manner, for example, this frequency value can be stored as an absolute frequency value, as a scaled relative value, or as a median value or an offset from a desired value. The stored value can be used later, and the necessary information can be recovered based on the recognition of the format of this stored value.

Step 412 is to initiate the iteration branch. If the final frequency value for NCO 206 has not yet been reached in step 412, the process proceeds to step 414 where the NCO 206 is changed to the next tuning frequency step value. In a preferred embodiment, this step value can be increased from the previous value. The increase value can vary depending on several factors. For example, this increase value may be a value of the bandwidth selected for use in the anti-alias filter 208. In any case, the magnitude and total frequency range of the increment value for the NCO 206 will determine the number of times the iteration branch is returned. The iteration branch returns to step 408 to measure the power in the AGC block 210 based on the new tuning frequency of the NCO 206. The process then proceeds to step 410 as before, writing both this newly measured power and this new frequency step value into memory. Finally, the process returns to step 412 to determine whether the final frequency value for the NCO 206 has been reached.

In step 412, if the final frequency value is reached at the NCO 206 (eg, the highest frequency value within the tuning range of the NCO 206), the iteration process ends and the decision branch at step 412 is now Proceed to step 416. In step 416, the process for determining the largest measurement value is started. The largest value for the measured power may be determined by the link processor 220 retrieving and processing previously stored values in the link memory 222. The link processor may directly compare by value or apply a “windowing” function to a contiguous set of values. In a windowing function, a contiguous set of data from memory is processed to produce a windowed value. In one embodiment, this window is selected to correspond to the bandwidth of the incoming signal, and the number of data points used in this window is multiplied by the signal bandwidth and the bandwidth previously selected for the anti-alias filter 208. It is a number. The selection of the window function may be made based on a number of parameters and may be selected in a manner that ensures proper signal detection by attempting to ensure that the signal appears within the window function. For example, if the signal bandwidth is 10 MHz and the selected anti-alias filter bandwidth is 1 MHz, the "window" is 10 MHz and the number of data points taken for each window may be 10. To facilitate a window near the first and last values stored, the window function starts at the point where the window function is filled, the endpoint values are repeated to fill the window, or the reduced window near the endpoints in memory. This window function may include a split step that causes the size. The same windowing function can then be applied to the frequency values associated with each of the magnitude values stored in the link memory 222. After the windowed values are generated, these windowed values are compared to determine the largest windowed value.

Finally, in step 418, the largest individual value measured or the largest windowed value measured is reported, and also the value of the frequency corresponding to the largest individual value measured or the largest windowed value measured is also reported. Is reported. These values can then be used for subsequent adjustment of other blocks in the link circuit 200. In one embodiment, the reported frequency value corresponding to the largest measured value may be processed by the link controller 218 to generate a new value used to program the nominal frequency of operation of the NCO 206. . In another embodiment, the frequency value corresponding to the largest measured value may be processed by the link processor 220 to generate a loop frequency offset value used to program the carrier tracking loop 216. In another embodiment, link processor 220 corresponds to the largest value measured along with the largest value measured to determine how much adjustment should be made to NCO 206 or carrier tracking loop 216. The value of the frequency can be used. Once the process described herein is complete, the link circuit 200 can begin processing the input signal under normal operation.

In other embodiments where the memory of the link memory 222 needs to be minimal, step 416 may be omitted, and step 410 may be modified to store only the largest measurement measured for that point and its associated frequency. Can be. In this embodiment, when each step including steps 408, 410, 412, and 414 is executed, the most recently measured magnitude value is compared with the currently stored maximum value. If the most recent magnitude value is greater than the currently stored value, then the currently stored value and its associated frequency value are replaced with the most recent magnitude value and its associated frequency. Otherwise, this memory location is left unchanged until the next size value is determined. Once the loop in the decision branch of step 412 is complete, the values in the memory are the values to report in step 418.

Using the methods and apparatus described above, the time spent determining the frequency offset during channel acquisition can be significantly reduced. This frequency offset can generally be determined within a relatively small error, such as +/- 1 MHz, even for signals with very low SNR, such as 1 dB SNR. Using this method, carrier tracking loop 216 can operate within the narrow pull-in range required for low SNR signals and the carrier tracking loop 216 does not have to step through multiple large pull-in ranges. will be. This method also applies equally well to any modulation format.

In addition, this method can function as a kind of "coarse tuning" for the frequency offset, allowing more accurate fine tuning to be maintained within other blocks, such as the carrier recovery loop 216, as described above. For example, the present invention described above can be used to reduce the frequency search space as much as possible to shorten the time required to obtain a signal. The present invention can be used to reduce the acquisition search space during the fine tuning step for about +/- 1 MHz or less. With this amount, then, typical acquisition schemes as described above can be used to complete the acquisition of the signal in the reduced search space due to the removal of part of the frequency offset.

In addition, the invention described herein is not limited to the processes associated with initial tuning of a communication system. The process described in the present invention can also be used at any time, such as when the system has previously found the correct frequency offset, or when the frequency offset can be changed in the system and must now be determined and corrected. .

While the present invention may accommodate many modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the invention is not limited to the specific forms disclosed. Rather, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the following claims.

Claims (26)

Receiving a signal having a first carrier frequency (402); Mixing (402) the received signal with a signal having a plurality of frequencies to produce a plurality of second signals, each having a different carrier frequency; Processing (408) the plurality of second signals to produce a plurality of magnitudes and a plurality of frequency values associated with the plurality of magnitudes; And Determining a maximum size among the plurality of sizes (416) Method 400 comprising a. The method of claim 1, Identifying (418) a selected frequency value, wherein the selected frequency value is a frequency value associated with the maximum magnitude. The method of claim 2, Using the selected frequency value to correct a frequency offset. The method of claim 1, Storing (410) the plurality of magnitudes and the plurality of frequency values associated with the plurality of magnitudes in a memory in the order in which the plurality of magnitudes and the plurality of frequency values are generated (410). . The method of claim 1, The processing further includes filtering (404) the plurality of second signals to improve resolution of the magnitude values. The method of claim 5, And the filtered second signal has a bandwidth not equal to the bandwidth of the second signal. The method of claim 1, The processing further comprises measuring (408) the magnitude of the plurality of filtered second signals. The method of claim 7, wherein The measuring step further comprises determining a root mean square power of the filtered second signal. The method of claim 1, The mixing step further comprises mixing the received signal with a plurality of discrete frequencies stepping from a start frequency to an end frequency. The method of claim 9, And wherein the starting frequency is lower than the stepping frequency. The method of claim 1, The determining step, Storing the plurality of magnitudes and the plurality of frequency values; Windowing the stored plurality of magnitudes and the stored plurality of frequency values to produce a plurality of windowed magnitudes and a plurality of windowed frequency values; And Determining a maximum windowed size among the plurality of windowed sizes Method 400 further comprises. The method of claim 11, Further comprising identifying a selected windowed frequency value, And wherein the selected windowed frequency value is a windowed frequency value associated with the maximum windowed magnitude. The method of claim 12, Using the selected windowed frequency value to correct a frequency offset. Frequency translators 204 and 206 for translating a first signal having a first carrier frequency into a plurality of second signals, each having a different carrier frequency; A detector 210 coupled to the frequency translator to measure a plurality of magnitudes of the plurality of second signals; And A processor 220 coupled to the frequency translator and the detector to determine a maximum magnitude among a plurality of magnitudes measured by the detector 210 Apparatus 200 comprising a. The method of claim 14, The processor (220) also determines a selected frequency value, wherein the selected frequency value is a frequency value associated with the maximum magnitude. The method of claim 15, The processor (220) also uses the selected frequency value to correct a frequency offset. The method of claim 15, The apparatus 200 further includes a memory 222 for storing the plurality of magnitudes, the plurality of frequency values associated with the plurality of magnitudes, in a memory in the order in which the plurality of magnitudes and the plurality of frequency values are generated. . The method of claim 14, And a filter (208) coupled between the frequency translator and the detector to filter the plurality of second signals to improve resolution of the magnitude values from the detector. The method of claim 18, The filter (208) has a bandwidth different from that of the signal having a second carrier frequency. The method of claim 14, The processor 220 also stores the plurality of sizes, windowes the stored plurality of sizes, generates a plurality of windowed sizes and a plurality of windowed frequency values, and stores the plurality of windowed sizes. Apparatus 200 for determining the maximum windowed size among the sizes. The method of claim 20, The processor also determines 200 the selected windowed frequency value associated with the maximum windowed magnitude. The method of claim 14, The frequency translator (204, 206) comprises a mixer (204) and an oscillator (206). The method of claim 22, The oscillator 206 is a numerically controlled oscillator. The method of claim 14, And the processor (220) determines a maximum size among a plurality of sizes measured by the detector (210) as a result of repeatedly controlling the frequency translator. The method of claim 14, Each of the plurality of second signals is generated at different times. Means (402) for receiving a signal having a first carrier frequency; Means (402) for mixing the received signal with a signal having a plurality of frequencies to produce a plurality of second signals, each having a different carrier frequency; Means (408) for processing the plurality of second signals to produce a plurality of magnitudes and a plurality of frequency values associated with the plurality of magnitudes; And Means (416) for determining a maximum size among the plurality of sizes Device comprising a.

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