KR20080071822A - Firefet and fabricating method of the same - Google Patents

Abstract

A FIREFET(Fin and Recess channel MOSFET) and a manufacturing method thereof are provided to improve a current driving performance of the FIREFET by reducing source and drain resistances. An active region is surrounded by a field oxide film on a semiconductor substrate. Source/drain(14,16) are formed on the active region with a fin-type channel between them. A recess hole is formed under the source/drain and the fin channel. A recess channel is formed under the fin channel at one side of the recess hole. Gate oxide films(80) are formed on a surface of the recess hole including the recess channel, side surfaces of the source/drain, and the fin channel. A gate(90a) surrounds the recess channel and the fin channel on the gate oxide film and is formed between the recess hole and the source/drain.

Description

Field Effect Transistor with Mixed Fin and Recess Channels and Manufacturing Method Thereof {FIREFET AND FABRICATING METHOD OF THE SAME}

1 is a perspective view showing the structure of a FinFET having a conventional multi-gate.

2A and 2B are a perspective view and a cross-sectional view taken along line AA ′ of an embodiment of the structure of a FIREFET device according to the present invention.

3A to 3R are process perspective views showing one embodiment of a method of manufacturing a FIREFET device according to the present invention.

4 is a cross-sectional view taken along line BB ′ of FIG. 3H.

5 is a cross-sectional view taken along line CC ′ of FIG. 3I.

FIG. 6 is a cross-sectional view taken along the line DD ′ of FIG. 3L.

FIG. 7 is a cross-sectional view taken along the line EE ′ of FIG. 3R.

8 is a sectional view taken along the line FF 'of FIG. 3R.

FIG. 9 is a cross-sectional view taken along the line GG ′ of FIG. 3R.

<Description of the symbols for the main parts of the drawings>

10 semiconductor substrate 12 pin channel

14 source 16 drain

18: recess channel 20a: first dummy layer mask

30a: second dummy layer mask 40a: first oxide film sidewall

50: second oxide film 60a: photosensitive film mask

70 groove: 70a recessed hole

80 third oxide film (gate oxide film) 90a gate

The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly to a field effect transistor having a self-aligned fin and recessed mixed channel region formed on a bulk silicon substrate and a method of manufacturing the same.

As the semiconductor industry develops, both memory and logic circuits require high integration and high speed operation of circuits. Thus, although the field size transistor (MOSFET) device, which is the most basic element of a semiconductor circuit, is being miniaturized in size, the MOSFET device having a channel length of 30 nm or less obtains good operating characteristics due to the extreme short channel effect. There is a hard problem.

One way to overcome this short channel effect is to implement a device with a multi-gate MOSFET structure. In multi-gate MOSFETs, the channel effect is controlled by multiple gate electrodes, which significantly reduces the short channel effect than conventional devices. As a result, as the device scale becomes smaller, the gate oxide film thickness reduction phenomenon, which is inevitably accompanied, can be flexibly handled, and the current driving capability of the device can be improved.

Recently manufactured multi-gate MOSFET devices are the most commonly used fin-type MOSFET (FinFET) type due to their process suitability.

However, in implementing FinFET devices, there are also problems such as the selection of gate materials, channel doping, source and drain resistance. In particular, in order to properly overcome the short channel effect, the fin width should be less than 2/3 of the gate length, which leads to a phenomenon that results in a faster scaling limit of the device in the region below 30 nm. If the thickness is very thin, there is a problem in that the resistance of the source and the drain becomes large, thereby reducing the current.

A typical FinFET structure having a conventional multi-gate, as shown in Figure 1, the source 110 and the drain 120 is implemented in the form of a thin fin, the gate 300 in the middle portion controls the channel In the form of a double gate or triple gate depending on the presence of the upper gate. By using the bulk silicon substrate 100, there are improvements in manufacturing cost and heat dissipation of the wafer than in the case of the SOI substrate. It has the following fundamental problems.

First, since the driving force of the current varies according to the height of the fin, the fin driving device generally improves the driving power as the height of the fin increases. In the case of the conventional FinFET device as shown in FIG. There is a problem that it is difficult to take high. This is because when the fin height is very high, the gate material may not overcome the step height due to the fin height during gate patterning, and thus the gate may not be formed properly.

Second, in the case of a fin-type MOSFET, the width of the fin should be made smaller than the gate length in order to suppress the short channel effect. When a device having a gate length of 50 nm or less is implemented, the fin width becomes very thin, resulting in the source and drain There is a problem in that the overall current driving ability is reduced due to the increase in resistance as the area decreases.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a new FIREFET device structure which fundamentally improves current driving capability by coupling a recess channel to a fin channel of a conventional FinFET on a bulk silicon substrate.

In addition, the source / drain and the gate are self-aligned, and by forming a gate material into a recess hole in forming a gate, unlike the conventional FinFET, the FIREFET capable of forming a gate regardless of the height of the fin Another object is to provide a method for manufacturing the device.

In order to achieve the above object, a field effect transistor (FIREFET) having a fin and recess mixed channel according to the present invention comprises an active region surrounded by a field oxide film on a predetermined semiconductor substrate; Source / drain formed between the fin-shaped channel in the active region; A recess hole formed under the source / drain and the fin channel; A recess channel formed under the fin channel to one side of the recess hole; A gate oxide layer formed on the surface of the recess hole including the recess channel and on each side of the source / drain connected to the recess hole and the fin channel; And a gate formed on the gate oxide layer to surround the recess channel and the fin channel and between the recess hole and the source / drain.

In addition, a method of manufacturing a field effect transistor (FIREFET) having a fin and recess mixed channel according to the present invention includes a first step of depositing a first dummy layer having a high silicon and etch selectivity on a predetermined silicon substrate; Depositing a second dummy layer having a high etching selectivity with an oxide film on the first dummy layer; A third step of patterning the second dummy layer and sequentially etching the second dummy layer and the first dummy layer according to the pattern to form a channel hard mask using a second dummy layer mask and a first dummy layer mask; ; Depositing and etching a first oxide film over the entire surface of the substrate to form sidewalls on a side surface of the channel hard mask; A fifth step of etching the silicon substrate using the formed sidewalls as a mask to define an active region; A sixth step of depositing a second oxide film on the entire surface of the substrate and planarization by a CMP process; A seventh step of applying and patterning a photoresist film to form a groove on the planarized substrate; An eighth step of etching the first oxide film and the second oxide film with the patterned photoresist mask to form a groove; A ninth step of forming a recess hole by etching the silicon substrate exposed by the groove formation; A tenth step of removing the first dummy layer mask exposed by the photoresist mask and the recess hole formation; An eleventh step of forming a third oxide film on the silicon substrate surface and the recess hole surface exposed by removing the first dummy layer mask; Depositing and etching a gate material over the entire surface of the substrate to fill the groove and the recess hole with the gate material; A thirteenth step of exposing the silicon substrate to be used as a source / drain by etching the first oxide film and the second oxide film; And a fourteenth step of forming a source / drain by implanting predetermined ions into the entire surface of the substrate.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

[Structure Example ]

The structure according to the present invention basically includes an active region surrounded by a field oxide film (not shown) on a predetermined semiconductor substrate 10, as shown in Figs. 2A and 2B; Source / drain (14) (16) formed in the active region with a pin-shaped channel (12) interposed therebetween; A recess hole 70a formed below the source / drain and the fin channel; A recess channel 18 formed below the fin channel to one side of the recess hole; A gate oxide layer formed on the surface of the recess hole 70a including the recess channel 18 and on each side of the source / drain 14 and 16 connected to the recess hole 70a and on the fin channel 12. 80; A gate 90a formed on the gate oxide layer 80 and surrounding the recess channel 18 and the fin channel 12 and between the recess hole 70a and the source / drain 14 and 16. It is configured to include.

In the present embodiment, as shown in FIG. 2B, a recess channel 18 is further formed below the fin channel 12, so that an additional current path is formed through the recess channel 18. It is further formed to improve the current driving capability.

Here, it is preferable to use a bulk silicon substrate as the semiconductor substrate 10. By doing so, the manufacturing cost can be lowered and the heat dissipation characteristics of the substrate can be improved than in the case of using the SOI substrate.

In addition, the width of the fin channel 12 is preferably 2/3 or less than the length of the gate 90a in order to adequately overcome the short channel effect of shortening the gate length.

In addition, the source / drain 14 and 16 are preferably formed in the entire active region except for the fin channel 12. As a result, an increase in resistance caused by a reduction in the source / drain area of the conventional FinFET is achieved. Can be solved. However, the problem of increased leakage current caused by an increase in the junction area due to an increase in the source / drain area can be solved by making the depth of the recess hole 70a deeper.

Accordingly, the height of the recess channel 18 is preferably 1 to 2 times the height of the fin channel 12, but is not necessarily limited thereto, and may be higher or lower depending on the area of the active region, that is, the source / drain. Of course it can.

[Production method Example ]

One embodiment of a method for manufacturing a FIREFET device according to the present invention is as follows.

First, as shown in FIG. 3A, a first dummy layer 20 having a high silicon and etch selectivity is deposited on a predetermined silicon substrate 10 (first step), and a high oxide film and a high etch selectivity are disposed on the first dummy layer. The second dummy layer 30 is deposited (second step).

Here, the first and second dummy layers 20 and 30 are used for temporary channel hard masks for subsequently etching the silicon substrate or the field oxide layer to form the fin channel 12 and the recess channel 18. Since the first dummy layer 20 is a material layer, the etching selectivity of the second dummy layer 30 is higher than that of the oxide film.

Therefore, more preferably, a nitride film or an oxide film may be used as the first dummy layer 20, and an amorphous silicon layer or a germanium silicon layer may be used as the second dummy layer 30, but is not limited thereto.

Next, as shown in FIG. 3B, the second dummy layer 30 is patterned, and the second dummy layer 30 and the first dummy layer 20 are sequentially etched according to the pattern to form each dummy layer mask 20a. (30a) to form a channel hard mask.

Subsequently, as shown in FIG. 3C, a sidewall 40 is formed on the side surface of the channel hard mask by etching and depositing a first oxide layer on the entire surface of the substrate using TEOS. The sidewall 40 thus formed is used as a mask to define the active region by etching the silicon substrate 10 later, so that the first and second dummy layers 20 and 30 of the first and second dummy layers 20 and 30 are formed according to the size of the active region to be formed. It is necessary to adjust the deposition thickness as well as the etching time of the first oxide film.

Next, as illustrated in FIG. 3D, the silicon substrate 10 is etched using the formed sidewall 40 as a mask to define the active region 10a.

Subsequently, the second oxide film 50 for the field is deposited on the entire surface of the substrate using a silicon oxide film (SiO ₂ ) or the like, and planarized by a CMP process until the second dummy layer mask 30a is exposed, as shown in FIG. 3E.

Next, the photoresist film 60 is coated on the planarized substrate (FIG. 3F) and patterned (FIG. 3G), and the planarization process is performed using the patterned photoresist mask 60a and the second dummy layer mask 30a. The first oxide film 40b and the second oxide film 50a exposed by etching are etched to form a groove 70 (FIG. 3H). In FIG. 3H, a cross-sectional view as shown in FIG. 4 is obtained by cutting in the direction BB ′.

Subsequently, when the active region 10a of the silicon substrate exposed by the groove 70 is etched, the recess hole 70a is formed, as shown in FIGS. 3I and 5. 5 is a cross-sectional view taken along line CC ′ of FIG. 3I. As can be seen in FIG. 5, the silicon fins made in the formation of the recess holes 70a are subsequently used as the channel 12 and the recess channel 18. When the recess hole 70a is formed, the second dummy layer mask 30a having an etch selectivity similar to that of silicon disappears and only the first dummy layer mask 20a having an etch selectivity different from that of silicon remains, so that only the latter is used as a channel hard mask. Done. Therefore, the depth of the recess hole 70a, that is, the height of the recess channel 18 may be adjusted by the silicon etching time.

Next, as shown in FIG. 3K, the first dummy layer mask 20a exposed by the photoresist mask 60a and the recess hole 70a is removed, and as shown in FIG. 3L, the first dummy layer mask 20a is removed. A third oxide film 80 is formed on the surface of the silicon substrate 10a and the recess hole 70a exposed by removing the silicon oxide film SiO ₂ . Here, the third oxide film 80 formed on the surface of the silicon substrate 10a and the recess hole 70a adjacent thereto exposed by removing the first dummy layer mask 20a serves as a gate oxide film (see FIG. 6). ). Therefore, in order to improve the quality of the gate oxide film, it is preferable to first form the third oxide film 80 after the sacrificial oxide film formation process. A third oxide film 80 is also formed on the second dummy layer 30b exposed during the gate oxide film forming process.

Subsequently, a gate material 90 is deposited on the entire surface of the substrate (FIG. 3m), and the same thickness is etched (FIG. 3n) to fill the groove 70 and the recess hole 70a with the gate material 90a. Here, the gate material is preferably metal or polysilicon, and when polysilicon is used as the gate material, it is preferable to further proceed with the step of doping the gate during the deposition of the gate material or after the deposition of the gate material.

Next, the first oxide film 40b and the second oxide film 50a are etched to expose the active region 10a of the silicon substrate to be used as a source / drain. To this end, the second dummy layer residue 30b and the first dummy layer residue 20b may be exposed and etched sequentially, as shown in FIGS. 3O to 3Q, but the first and the second dummy layer 20b may be exposed. After the second oxide film is etched, the second dummy layer residue 30b and the first dummy layer residue 20b may be removed at a time.

Finally, as shown in FIG. 3q, the source / drain 14, 16 is formed by implanting predetermined ions into the active region 10a that is particularly exposed on the entire surface of the substrate through a known ion implantation process.

After the formation of the source / drain 14 and 16, an annealing process of activating ions implanted into the ion implantation process may be further performed. However, in this case, the annealing process is sufficient to activate the implanted ions, so it is preferable to anneal shortly at about 1000 ° C. for 5 to 10 seconds. If too much, the diffusion of the implanted ions shortens the length of the fin channel.

3R is a progression to the annealing process, and FIGS. 7 to 9 are cross-sectional views illustrating cross sections of lines EE ′, FF ′, and GG ′ of FIG. 3R.

Referring to FIG. 7, a gate oxide film (third oxide film 80) is formed below the gate 90A to surround the fin, and the upper fin is the fin channel 12 and the lower fin is the recess channel 18. Here, the fin channel 12 refers to an active region between the source / drain partitioned up to the junction portion formed under the source / drain 14 and 16 as shown in FIG. 8.

Thereafter, the back-end process, such as the formation of metal lines, should follow a conventional MOSFET process, and further description thereof will be omitted.

As described above, preferred embodiments of the present invention have been described in detail, but the present invention is not limited thereto, and various modifications can be made by those skilled in the art. Accordingly, descriptions of various embodiments that can be modified under the technical spirit of the present invention will be omitted herein.

According to the present invention described above, by having a large source / drain area and a self-aligned fin and recess mixed channel MOSFET (FIREFET) structure on the bulk substrate, the resistance of the source and drain is lower than before, and the recess channel As a result, there is an effect of fundamentally improving the current driving capability.

In addition, since the source / drain and the gate can be manufactured in a self-aligned structure, it can be manufactured by a relatively simple process method, and manufacturing on a bulk silicon substrate also reduces the manufacturing cost.

Claims (11)

An active region surrounded by a field oxide film on a predetermined semiconductor substrate; Source / drain formed between the fin-shaped channel in the active region; A recess hole formed under the source / drain and the fin channel; A recess channel formed under the fin channel to one side of the recess hole; A gate oxide layer formed on the surface of the recess hole including the recess channel and on each side of the source / drain connected to the recess hole and the fin channel; A field effect transistor (FIREFET) having a fin and recess mixed channel, comprising a gate formed on the gate oxide layer to cover the recess channel and the fin channel and between the recess hole and the source / drain. . The method of claim 1, The semiconductor substrate is a bulk silicon substrate, characterized in that the field effect transistor (FIREFET) having a fin and recess mixed channel. The method according to claim 1 or 2, The width of the fin channel is less than two thirds of the gate length field effect transistor (FIREFET) having a mixed pin and recess channel. The method of claim 3, wherein And the source / drain is formed over the entire active region excluding the fin channel. The method of claim 4, wherein The height of the recess channel is a field effect transistor (FIREFET) having a fin and recess mixed channel, characterized in that 1 to 2 times the height of the pin channel. Depositing a first dummy layer having a high etching selectivity with silicon on a predetermined silicon substrate; Depositing a second dummy layer having a high etching selectivity with an oxide film on the first dummy layer; A third step of patterning the second dummy layer and sequentially etching the second dummy layer and the first dummy layer according to the pattern to form a channel hard mask using a second dummy layer mask and a first dummy layer mask; ; Depositing and etching a first oxide film over the entire surface of the substrate to form sidewalls on a side surface of the channel hard mask; A fifth step of etching the silicon substrate using the formed sidewalls as a mask to define an active region; A sixth step of depositing a second oxide film on the entire surface of the substrate and planarization by a CMP process; A seventh step of applying and patterning a photoresist film to form a groove on the planarized substrate; An eighth step of etching the first oxide film and the second oxide film with the patterned photoresist mask to form a groove; A ninth step of etching the silicon substrate exposed by the groove formation to form a recess hole; A tenth step of removing the first dummy layer mask exposed by the photoresist mask and the recess hole formation; An eleventh step of forming a third oxide film on the silicon substrate surface and the recess hole surface exposed by removing the first dummy layer mask; Depositing and etching a gate material over the entire surface of the substrate to fill the groove and the recess hole with the gate material; A thirteenth step of exposing the silicon substrate to be used as a source / drain by etching the first oxide film and the second oxide film; And a fourteenth step of forming a source / drain by implanting predetermined ions into the entire surface of the substrate, wherein the field effect transistor has a fin and recess mixed channel. The method of claim 6, In the twelfth step, the gate material is metal or polysilicon, When the gate material is polysilicon, the method further comprises doping the gate material upon depositing the gate material or depositing the gate material, and then manufacturing a field effect transistor (FIREFET) having a fin and recess mixed channel. Way. The method of claim 7, wherein And an annealing process for activating the ions implanted into the ion implantation process after the fourteenth step is further added to the field effect transistor (FIREFET) having a fin and recess mixing channel. The method according to any one of claims 6 to 8, The method of manufacturing a field effect transistor (FIREFET) having a pin and a recess mixed channel characterized in that the depth of the recess hole in the ninth step is adjusted by the etching time. The method of claim 9, The first dummy layer is a nitride film or an oxide film, The second dummy layer is an amorphous silicon layer or a germanium silicon layer, characterized in that the field effect transistor (FIREFET) having a fin and recess mixed channel. The method of claim 10, The first oxide film is a TEOS film, The second oxide film is a silicon oxide film (SiO ₂ ), And the third oxide layer is a silicon oxide layer (SiO ₂ ) as a gate oxide layer. _{2. A} method of manufacturing a field effect transistor having a fin and recess mixed channel.

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