KR20080070400A - Display apparatus - Google Patents

Abstract

A display apparatus is provided to reduce the number of components to be mounted in a flexible printed circuit board by forming a capacitor for driving voltage stabilization in a display panel, and improve the driving reliability by reducing discharge time of the capacitor. A display apparatus includes a display panel(100), a driving unit(200), a first gate driving circuit(310), a second gate driving circuit(320), plural layered capacitors(410~450) and a discharge circuit(500). The display panel is comprised of a first display area(DA1) which displays a main image, a second display area(DA2) which displays a sub image and peripheral areas(PA1~PA7) which surrounds the first display area and the second display area. The first gate driving circuit outputs a gate signal which activates a first gate lines(GL1_1~GL1_n). The second gate driving circuit outputs a gate signal which activates a second gate lines(GL2_1~GL2_n). The driving unit provides a gate control signal and a gate voltage which control the first gate driving circuit and the second gate driving circuit. The plural layered capacitors are formed in the peripheral area to stabilize the first gate voltage. And the discharge circuit discharges the plural layered capacitors in response to the second gate voltage converted into a grounded voltage level after power cutoff.

Description

Display device {DISPLAY APPARATUS}

1 is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the first multilayer capacitor and the first thin film transistor illustrated in FIG. 1.

FIG. 3 is a block diagram illustrating the driving unit, the multilayer capacitors, and the discharge circuit shown in FIG. 1.

4 is a schematic structural block diagram of an embodiment of the first gate driving circuit illustrated in FIG. 1.

FIG. 5 is an equivalent diagram showing an embodiment of each stage shown in FIG. 4.

<Description of the symbols for the main parts of the drawings>

100: display panel 110: array substrate

120: opposing substrate 130: flexible circuit board

200; Driver 310: first gate driving circuit

320; Second gate driving circuits 410 to 450: multilayer capacitors

DA1: first display area DA2: second display area

PA1 to PA7: Peripheral region TFT1: First thin film transistor

TFT2: second thin film transistor CLC1: first liquid crystal capacitor

CLC2: second liquid crystal capacitor GL1_1 to GL1_n: first gate wirings

GL2_1 to GL2_i: second gate lines DL1_1 to DL1_m: first data lines

DL2_1 to DL2_j: second data wires

The present invention relates to a display device, and more particularly, to a display device capable of reducing costs by reducing the number of mounting parts.

2. Description of the Related Art Generally, a liquid crystal display device includes a display panel including an array substrate and an opposite substrate facing each other with a liquid crystal having an anisotropic dielectric constant therebetween, and a driving circuit unit for driving the display panel. Gate lines extend in one direction, data lines extend in a direction crossing the gate lines, and a plurality of pixel parts defined in the gate lines and the data lines are formed in the display panel.

The driving circuit may include a gate driver for sequentially supplying gate signals to the gate lines, a data driver for supplying image data signals to the data lines, a timing controller for controlling the gate driver and the data driver, and a driving voltage required for each unit. It includes a voltage generator for generating.

The driving circuit unit receives and displays image data through a flexible circuit board attached to the display panel, and various components for driving the display panel are mounted on the flexible circuit board. As a representative example, a plurality of capacitors for stabilizing the driving voltage generated by the voltage generator is mounted on the flexible circuit board, and the larger the number of mounting components, the higher the production cost.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display device capable of reducing the cost by reducing the number of mounting components.

A display device according to an exemplary embodiment for realizing the object of the present invention includes a display panel, a voltage generator, a first stacked capacitor, and a discharge circuit. The display panel includes a first display area in which a plurality of pixel parts including switching elements are formed, a second display area in which a main image is displayed, and a second display area in which a sub image is displayed, and a periphery surrounding the first display area and the second display area. It consists of an area. The voltage generator receives a power supply voltage to generate a first gate voltage of a high level and a second gate voltage of a low level. The first stacked capacitor is formed in the peripheral region and stabilizes the first gate voltage. The discharge circuit discharges the first multilayer capacitor in response to the second gate voltage switched to the ground voltage level after the power supply voltage is cut off.

According to such a display device, the number of parts to be mounted can be reduced, thereby reducing the cost.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view illustrating a display device according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the first multilayer capacitor and the first thin film transistor illustrated in FIG. 1.

1 and 2, a display device according to an exemplary embodiment of the present invention includes a display panel 100 for displaying an image, a driver 200, a first gate driver circuit 310, and a second gate driver circuit 320. ), A plurality of stacked capacitors 410 to 450, and a discharge circuit 500.

The display panel 100 includes an array substrate 110 and an opposing substrate 120, and a liquid crystal layer (not shown) interposed between the array substrate 110 and the opposing substrate 120, and displays a main image. A first display area DA1 and a second display area DA2 on which a sub-image is displayed, and a peripheral area surrounding the first display area DA1 and the second display area DA2. The peripheral area is divided into first to seventh peripheral areas PA1 to PA7 according to positions.

The first display area DA1 includes a plurality of first gate lines GL1_1 to GL1_n extending in one direction and a plurality of first data extending in a direction crossing the first gate lines GL1_1 to GL1_n. A plurality of pixel parts is defined by the wirings DL1_1 to DL1_m. In each pixel part defined in the first display area DA1, a first thin film transistor TFT1 connected to a first gate line and a first data line is formed as a switching element, and the first thin film transistor TFT1 is connected to the first thin film transistor TFT1. The first liquid crystal capacitor CLC1 and the first storage capacitor CST1 that are electrically connected to each other are formed.

The first thin film transistor TFT1 may include a gate electrode GE, a first insulating layer 112, an active layer 116a, an ohmic contact layer 116, and a source electrode stacked on the array substrate 110 in order. SE, a drain electrode DE, and a second insulating layer 114. The pixel electrode PE, which is one side electrode of the first liquid crystal capacitor CLC1, is connected to the drain electrode DE.

In the second display area DA2, a plurality of second gate lines GL2_1 to GL2_i extending in one direction and a plurality of second data extending in a direction crossing the second gate lines GL2_1 to GL2_i. A plurality of pixel parts is defined by the wirings DL2_1 to DL2_j. In each pixel portion defined in the second display area DA2, a second thin film transistor TFT2 connected to the second gate line and the second data line is formed as a switching element, and the second thin film transistor TFT2 is formed. The second liquid crystal capacitor CLC2 and the second storage capacitor CST2 are electrically connected to each other. The second thin film transistor TFT2 is formed in the same manner as the first thin film transistor TFT1.

The second data lines DL2_1 to DL2_j may be connected to the first data line through connection lines formed in a seventh peripheral area PA7 positioned between the first display area DA1 and the second display area DA2. The other ends of the data lines DL1_1 to DL1_m are electrically connected to the other ends of the data lines DL1_1 to DL1_j. In addition, the second gate lines GL2_1 to GL2_i are smaller than the first gate lines GL1_1 to GL1_n.

One end of the flexible circuit board 130 is attached to a first peripheral area PA1 positioned at one end of the first data lines DL1_1 to DL1_m, and electrically connects an external system to the driving unit 200. do.

The driver 200 has a chip shape and is mounted in the first peripheral area PA1 and has a data signal on the first data lines DL1_1 to DL1_m and the second data lines DL2_1 to DL2_j. And a gate control signal and a gate voltage for controlling the driving of the first gate driving circuit 310 and the second gate driving circuit 320.

The first gate driving circuit 310 is formed in the second peripheral area PA2 positioned at one end of the first gate lines GL1_1 to GL1_n in an integrated circuit form, and the first gate lines GL1_1. Gate signals for activating ˜GL1_n) are sequentially output.

The second gate driving circuit 320 is formed in the fourth peripheral area PA4 positioned at one end of the second gate lines GL2_1 to GL2_i in an integrated circuit form, and the second gate lines GL2_1. ~ G2_i) to sequentially output the gate signal.

The plurality of multilayer capacitors 400 are formed in the peripheral region, and are generated by a voltage generator to be described later to stabilize driving voltages provided to each unit. For example, the plurality of multilayer capacitors 410 to 450 are formed in the third to sixth peripheral regions PA3 to PA6, and are divided into first to fifth multilayer capacitors 410 to 450. Here, the division of the first to fifth stacked capacitors (410 to 450), the area and the formation position of each of them is an example for convenience of description, and the formation of the stacked capacitors (410 to 450) is required according to characteristics. It can be freely changed and applied in consideration of the number of capacitors, capacity, connection wiring, etc. In some cases, the multilayer capacitors 410 to 450 may also be formed in the first, second and fourth peripheral regions PA1, PA2, and PA4.

The multilayer capacitors 410 to 450 are formed together when the pixel portion is formed, and as an example, a schematic configuration of the first multilayer capacitor 410 will be described.

The first multilayer capacitor 410 is interposed between the first electrode 410a and the second electrode 410b and the first electrode 410a and the second electrode 410b to function as a dielectric. Is defined by 112. The first electrode 410a is formed together when the gate electrode GE is formed, and the second electrode 410b is formed together when the source electrode and the drain electrodes SE and DE are formed.

The first multilayer capacitor 410 further includes a third electrode (not shown) and a second insulating layer 114 interposed between the second electrode 410b and the third electrode (not shown). The third electrode may be formed together when the pixel electrode PE is formed. In some cases, the first electrode 410a may be omitted, and only the second electrode 410b and the third electrode (not shown) may be defined.

The discharge circuit 500 is formed in the third peripheral area PA3, and is electrically connected to the first multilayer capacitor 410 and the driving unit 200, and is similarly formed when the first thin film transistor TFT1 is formed. Is formed

FIG. 3 is a block diagram illustrating the driving unit, the multilayer capacitors, and the discharge circuit shown in FIG. 1.

1 and 3, the driver 200 includes a controller 210, a data driver 220, a voltage generator 230, a first gate controller 240, a second gate controller 250, and a gamma. The generation unit 260 is included.

The controller 210 controls the raw image data DATA from the external device, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the main clock signal MCLK to control the display thereof. Receiving the synchronization signals CONT, and the first gate voltage VGH having a high level and the second gate voltage VGL having a low level from the voltage generator 230. A gate driving voltage is provided.

The controller 210 receives the first gate control signal 210c, the second gate control signal 210d, the data control signal 210b, and the voltage control signal 210e based on the received synchronization signals CONT. And the first gate controller 240, the second gate controller 250, the data driver 220, and the voltage controller 230, respectively.

Here, the first gate control signal 210c includes a first clock signal CLK1, a second clock signal CLK2, and a first vertical start signal STV1, and the second gate control signal 210d is And a third clock signal CLK3, a fourth clock signal CLK4, and a second vertical start signal STV2, wherein the clock signals CLK1 to CLK4 and the vertical start signals STV1 and STV2 are formed of the first clock signal CLK3. It consists of one gate voltage VGL and a second gate voltage VGL. The second clock signal CLK2 is out of phase with the first clock signal CLK1 and the fourth clock signal CLK4 is out of phase with the third clock signal CLK3.

Meanwhile, the controller 210 transmits the data signal 210a processed to apply the received raw image data DATA to the display panel 100 to the data driver 220 together with the data control signal 210b. The data signal 210a may include a first data signal DATA1 for the first display area DA1 and a second data signal DATA2 for the second display area DA2.

The voltage generator 230 receives an external power supply voltage according to the voltage control signal 210e provided by the controller 210 to receive an analog driving voltage AVDD, the first gate voltage VGH, and the second voltage. The gate voltage VGL, the common voltage Vcom, and the gamma driving voltage GVDD are generated. The generated first and second gate voltages VGH and VGL are provided to the controller 210, and the second gate voltage VGL is also provided to the first and second gate controllers 240 and 250. The analog driving voltage AVDD is provided to the data driver 220, the gamma driving voltage GVDD is provided to the gamma generator 260, and the common voltage Vcom is the display panel 100. Is provided.

The data driver 220 may correspond to the data signal 210a provided according to the data control signal 210b based on the gamma reference voltage VREF and the analog drive voltage AVDD (eg, an analog data signal). The data voltage is converted into a data voltage and output to the first data lines DL1_1 to DL1_m. In other words, the first data signal DATA1 is converted and output to the first data lines DL1_1 to DL1_m, and the second data signal DATA2 is converted to the first data lines DL1_1 to DL1_m. It is output to some of the wires DL1_1 to DL1_j and provided to the second data wires DL2_1 to DL2_j.

The first gate controller 240 provides the received first gate control signal 210c and the second gate voltage VGL to the first gate driving circuit 310 and the second gate controller 250. The second gate control signal 210d and the second gate voltage VGL are provided to the second gate driving circuit 320.

The gamma generator 260 receives the gamma driving voltage GVDD from the voltage generator 230, generates a plurality of gamma reference voltages VREF, and provides the gamma driving voltages VREF to the data driver 220.

Meanwhile, the stacked capacitors 410 to 450 formed in the peripheral area of the display panel 100 stabilize the driving voltages output from the voltage generator 230.

That is, the first multilayer capacitor 410 is connected to the output of the first gate voltage VGH to stabilize the first gate voltage VGH, and the second multilayer capacitor 420 is connected to the second gate voltage. The second gate voltage VGL is stabilized by being connected to an output of the VGL. In this manner, the third to fifth stacked capacitors 430 to 450 stabilize the common voltage Vcom, the analog driving voltage AVDD, and the gamma driving voltage GVDD, respectively.

The discharge circuit 500 is connected to the first multilayer capacitor 410 in parallel and includes a switching element to which a control electrode is applied the second gate voltage VGL.

The discharge circuit 500 is turned on by the second gate voltage VGL which is switched to the ground voltage level after the power supply voltage supplied to the voltage generator 230 is cut off when the power is turned off. 1 The discharge time of the multilayer capacitor 410 is shortened. In general, since the second gate voltage VGL has a level lower than the ground voltage, the discharge circuit 500 is maintained at the turn-off level at power on, and at the power off, the second gate voltage VGL is maintained. As a result of switching to the ground voltage level, it is turned on to shorten the discharge time of the first stacked capacitor 410.

As described above, the discharge circuit 500 shortens the discharge time of the first multilayer capacitor 410 that stabilizes the first gate voltage VGH after the power is turned off, that is, when the power supply voltage is cut off, thereby driving the display device. Reliability can be improved.

4 is a schematic structural block diagram of an embodiment of the first gate driving circuit illustrated in FIG. 1.

1 and 4, the first gate driving circuit 310 includes a shift register including a plurality of stages SRC1 to SRCn + 1 that are connected to each other dependently, and the stages SRC1 to SRCn. +1) is divided into n driving stages SRC1 to SRCn and one dummy stage SRCn + 1.

Each stage includes a first clock terminal CK1, a second clock terminal CK2, a first input terminal IN1, a second input terminal IN2, a voltage terminal VSS, and an output terminal OUT.

The first clock signal CK1 and the second clock terminal CK2 of the k-th stage SRCk and k are natural numbers are provided with the first clock signal CLK1 and the second clock signal CLK2 that are out of phase with each other. do. That is, the first and second clock signals CLK1 and CLK2 are provided to odd-numbered stages, and the second and first clock signals CLK2 and CLK1 are provided to even-numbered stages, respectively. do.

Output signals of the k-1st stage SRCk-1 and the k + 1st stage SRCk + 1 are respectively provided to the first input terminal IN1 and the second input terminal IN2 of the kth stage SRCk. The first vertical start signal STV1 is provided to the first input terminal IN1 of the first stage SRC1 and the second input terminal IN2 of the last stage SRCn + 1.

The second gate voltage VGL is provided to the voltage terminal VSS of the k-th stage SRCk, and a high section of the clock signal input to the first clock terminal CK1 is output. .

As such, the first gate driving circuit 310 includes a plurality of stages SRC1 to SRCn + 1, and includes the first clock signal CLK1, the second clock signal CLK2, and the first vertical start signal The first gate lines GL1_1 to GL1_n are driven based on the STV1 and the second gate voltage VGL.

FIG. 5 is an equivalent diagram showing an embodiment of each stage shown in FIG. 4.

For convenience of description, the first clock signal CLK1 and the second clock signal CLK2 are provided to the first clock terminal CK1 and the second clock terminal CK2, respectively.

4 and 5, the k-th stage SRCk includes a pull-up unit 311, a pull-down unit 312, a pull-up driving unit 313, a ripple prevention unit 314, and a pull-down control unit 315. , Include.

The pull-up unit 311 includes a first transistor TR1 and outputs a high section of the first clock signal CLK1, which is the first clock terminal CK1, to the output terminal OUT to pull the gate signal. Pull-up The pull-up unit 311 further includes a charging capacitor C1 formed between the control electrode and the output electrode of the first transistor TR1.

The pull-down unit 312 converts the gate signal output to the output terminal OUT into the second gate voltage VGL in response to the second clock signal CLK2 which is the second clock terminal CK2 signal. A second transistor TR2 that pulls down and pulls down, and a third transistor that pulls down the gate signal in response to the first clock signal CLK1 that is the first clock terminal CK1 signal. (TR3). The third transistor TR3 is driven in response to the first clock signal CLK1 charged in the switching capacitor C2.

The pull-up driving unit 313 turns on the pull-up unit 311 in response to a high value of an output signal of the k-1 stage SRCk-1 applied to the first input terminal IN1. And a fifth transistor TR5 which turns off the pull-up unit 311 in response to a high value of the output signal of the k + 1th stage SRCk + 1 applied to the second input terminal IN2. ).

The ripple prevention unit 314 maintains the first node T1 at the second gate voltage VGL, so that the ripple of the first node T1 generated by the coupling of the first clock signal CLK1 is generated. The sixth transistor TR6 prevents ripple.

The pull-down control unit 315 includes a seventh transistor TR7 that turns off the ripple prevention unit 314 in response to the signal of the first node T1.

As described above, according to the present invention, the capacitor for stabilizing the driving voltage is formed on the display panel, thereby reducing the number of components to be mounted on the flexible circuit board, thereby reducing the cost. In addition, it is possible to improve the driving reliability by shortening the discharge time of the multilayer capacitor for stabilization of the first gate voltage at the high level when the power is turned off by the discharge circuit.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (7)

A display including a first display area in which a main image is displayed, a second display area in which a sub image is displayed, and a peripheral area surrounding the first display area and the second display area, the plurality of pixel parts including a switching element being formed. panel; A voltage generator configured to receive a power supply voltage and generate a first gate voltage having a high level and a second gate voltage having a low level; A first multilayer capacitor formed in the peripheral region and stabilizing the first gate voltage; And And a discharge circuit configured to discharge the first multilayer capacitor in response to the second gate voltage switched to the ground voltage level after the power supply voltage is cut off. The display device of claim 1, wherein the discharge circuit comprises a switching element and is formed in the peripheral area. The display device of claim 2, further comprising a second stacked capacitor formed in the peripheral region and stabilizing the second gate voltage. 4. The pixel portion of the first display area is defined by a plurality of first gate lines and a plurality of first data lines, and the pixel portion of the second display area is a plurality of second gate lines. And a plurality of second data wires, A first gate driving circuit formed in the peripheral area positioned at one end of the first gate lines and driving the first gate lines; And And a second gate driving circuit formed in the peripheral area positioned at one end of the second gate wires and driving the second gate wires. The display device of claim 4, wherein the voltage generator further generates an analog driving voltage provided to the data driver, a gamma driving voltage based on the analog driving voltage, and a common voltage applied to the display panel. 6. The display device of claim 5, further comprising stacked capacitors formed in the peripheral region and stabilizing the analog driving voltage, the gamma driving voltage, and the common voltage, respectively. The gamma generator of claim 6, further comprising: a gamma generator configured to receive the gamma driving voltage to generate a plurality of gamma reference voltages; A data driver configured to receive the plurality of gamma reference voltages and analog driving voltages to drive the first data wires and the second data wires; And And a controller for controlling driving of the first gate driver circuit, the second gate driver circuit, the data driver, and the voltage generator to display externally supplied image data.

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