KR20080066250A - Pulse amplitude modulation driving circuit - Google Patents

Abstract

A pulse amplitude modulation driving circuit is provided to be operated at a low power by using one current source. A pulse amplitude modulation driving circuit includes a first variable resistor circuit(Rvar1), a second variable resistor circuit(Rvar2), a first transistor(D1), and a second transistor(D2). The first and the second variable resistor circuits are coupled to a power voltage, and have a resistance value which is variable according to 2-bit data. The first transistor is coupled between a current source and the first variable resistance circuit, and is controlled by a second data bit of the 2-bit data. The second transistor is coupled between the second variable resistance circuit and the current source, and is controlled by a complementary value of the second data bit of the 2-bit data.

Description

Pulse amplitude modulation driving circuit {PULSE AMPLITUDE MODULATION DRIVING CIRCUIT}

1 is a circuit diagram illustrating a 2-PAM driver of a general data transmission circuit.

FIG. 2 is a table showing output voltages of the 2-PAM driver shown in FIG. 1.

3 is a circuit diagram illustrating a 4-PAM driver of a general data transmission circuit.

FIG. 4 is a table showing output voltages of the 4-PAM driver shown in FIG. 3.

5 is a block diagram schematically showing a transmission circuit according to the present invention.

FIG. 6 is a circuit diagram illustrating the 4-PAM driver shown in FIG. 5.

FIG. 7 is a circuit diagram illustrating in detail the variable resistor of the 4-PAM driver shown in FIG. 6.

8 is a table illustrating values of the variable resistors according to the first bit voltage and the second bit voltage.

FIG. 9 is a table showing output voltages of the 4-PAM driver shown in FIG. 6.

* Description of symbols on the main parts of the drawings *

10 digital circuit 20 4-PAM driver

30: transmitter 40: antenna

The present invention relates to a data transmission circuit, and more particularly, to a data transmission circuit using pulse amplitude modulation.

The concept of multilevel transmission has emerged as a way to send and receive larger amounts of information without increasing the data rate. Among them, a pulse amplitude modulation (hereinafter referred to as PAM) method has been proposed. According to this PAM method, only the amplitude of the pulse is changed and transmitted while leaving the width and period of the pulse as it is to be transmitted. In the PAM scheme, only the amplitude of the pulse changes, which simplifies the configuration of the modulator and demodulator.

1 is a circuit diagram illustrating a 2-PAM driver of a general data transmission circuit.

Referring to FIG. 1, a 2-PAM driver of a typical data transmission circuit includes two resistors R1 and R2, two NMOS transistors A1 and A2, and one current source I1 through which current I flows. do.

The first bit voltage Bit1 is connected to the gate of the NMOS transistor A1 and the first complementary bit voltage / Bit1 is connected to the gate of the NMOS transistor A2. Thus, when one NMOS transistor is on, the other NMOS transistor is off. One ends of the two resistors R1 and R2 are respectively connected to the drains of the NMOS transistors A1 and A2, and the other ends thereof are respectively connected to the external power supply VDD. In this embodiment, it is assumed that the magnitudes of the two resistors R1 and R2 are both R [Ω]. The sources of the two NMOS transistors A1 and A2 are connected to the current source I1. Current I flows through one of the two NMOS transistors A1 and A2. Therefore, the voltages of the output terminal Out + and the output terminal Out- connected to the drains of the NMOS transistors A1 and A2 are changed, and the difference between the voltage of the output terminal Out + and the voltage of the output terminal Out-. To distinguish the data you are sending.

FIG. 2 is a table showing output voltages of the 2-PAM driver shown in FIG. 1.

Referring to FIG. 2, when the first bit voltage Bit1 is low, the NMOS transistor A1 is turned off and the NMOS transistor A2 is turned on. Thus, current I flows through the NMOS transistor A2. The voltage at the output terminal Out + is (VDD-R * I) [V] by Kirchhoff's Voltage Law (KVL). The voltage at the output terminal Out- becomes VDD [V] because no current flows through the resistor R1. Therefore, the output voltage becomes the output terminal (Out +) voltage-the output terminal (Out-) voltage = -R * I [V]. In this case, power consumption is VDD * I [W].

When the first bit voltage Bit1 is high, the NMOS transistor A1 is turned on and the NMOS transistor A2 is turned off. Thus, current I flows through the NMOS transistor A1. The voltage at the output terminal (Out-) becomes (VDD-RI) [V] by KVL. The voltage at the output terminal Out + becomes VDD [V] because no current flows through the resistor R2. Therefore, the output voltage becomes the output terminal (Out +) voltage-the output terminal (Out-) voltage = R * I [V]. In this case, power consumption is VDD * I [W].

In this manner, one bit can be transmitted at a time. However, the 4-PAM driver to be described later may send twice as much information as the 2-PAM driver at the same data rate.

3 is a circuit diagram illustrating a 4-PAM driver of a general data transmission circuit.

Referring to FIG. 3, a typical 4-PAM driver includes two resistors R3 and R4, four NMOS transistors B1, B2, C1 and C2, and two current sources I2 and I3. .

The 4-PAM driver can transmit two bits at a time. The first bit voltage Bit1 is connected to the gate of the NMOS transistor B1 and the first complementary bit voltage / Bit1 is connected to the gate of the NMOS transistor B2. Therefore, only one NMOS transistor of the NMOS transistors B1 and B2 is turned on. The sources of the NMOS transistors B1 and B2 are connected to a current source I2 through which a current I [A] flows. The second bit voltage Bit2 is connected to the gate of the NMOS transistor C1, and the second complementary bit voltage / Bit2 is connected to the gate of the NMOS transistor C2. Therefore, only one NMOS transistor of the NMOS transistors C1 and C2 is turned on. The sources of the NMOS transistors C1 and C2 are connected to a current source I3 through which a current 2I [A] flows. One end of the resistor is connected to the drains of the NMOS transistors B1, B2, C1, and C2, respectively, and the other end thereof is connected to an external power supply VDD. Current I [A] flows through the NMOS transistor of one of the two NMOS transistors B1 and B2 and current 2I [A] flows through the NMOS transistor of one of the two NMOS transistors C1 and C2. Therefore, the voltages of the output terminal Out + and the output terminal Out- connected to the drains of the NMOS transistors B1, B2, C1, and C2 are changed, and the voltages of the output terminal Out + and the output terminal Out- Different data can be distinguished by the difference in voltage.

FIG. 4 is a table showing output voltages of the 4-PAM driver shown in FIG. 3.

Referring to FIG. 4, when the first bit voltage Bit1 and the second bit voltage Bit2 are low, the NMOS transistor B1 is turned off and the NMOS transistor B2 is turned on. The NMOS transistor C1 is turned off and the NMOS transistor C2 is turned on. Thus, current I [A] flows through NMOS transistor B2 and current 2I [A] flows through NMOS transistor C2. The voltage at the output terminal Out + becomes (VDD-3RI) [V] by KVL. The voltage at the output terminal (Out-) becomes VDD [V] because no current flows through the resistor R. Therefore, the output voltage becomes the output terminal (Out +) voltage-the output terminal (Out-) voltage = -3R * I [V].

When the first bit voltage Bit1 is low and the second bit voltage Bit2 is high, the NMOS transistor B1 is turned off and the NMOS transistor B2 is turned on. The NMOS transistor C1 is turned on and the NMOS transistor C2 is turned off. Thus, current I [A] flows through NMOS transistor B2 and current 2I [A] flows through NMOS transistor C1. The voltage at the output terminal Out + becomes (VDD-R * I) [V] by KVL. The voltage at the output terminal (Out-) becomes (VDD-2R * I) [V] by KVL. Therefore, the output voltage becomes the output terminal (Out +) voltage-the output terminal (Out-) voltage = R * I [V].

When the first bit voltage Bit1 is high and the second bit voltage Bit2 is low, the NMOS transistor B1 is turned on and the NMOS transistor B2 is turned off. The NMOS transistor C1 is turned off and the NMOS transistor C2 is turned on. Thus, current I [A] flows through NMOS transistor B1 and current 2I [A] flows through NMOS transistor C2. The voltage at the output terminal (Out +) is (VDD-2R * I) [V] by KVL. The voltage at the output terminal (Out-) becomes (VDD-R * I) [V] by KVL. Therefore, the output voltage becomes the output terminal (Out +) voltage-the output terminal (Out-) voltage = -R * I [V].

When the first bit voltage Bit1 and the second bit voltage Bit2 are high, the NMOS transistor B1 is turned on and the NMOS transistor B2 is turned off. The NMOS transistor C1 is turned on and the NMOS transistor C2 is turned off. Thus, current I [A] flows through NMOS transistor B1 and current 2I [A] flows through NMOS transistor C1. The voltage at the output terminal (Out-) becomes (VDD-3R * I) [V] by KVL. The voltage at the output terminal Out + is VDD [V] because no current flows through the resistor R. Therefore, the output voltage becomes the output terminal (Out +) voltage-the output terminal (Out-) voltage = 3R * I [V].

By changing the size of the pulse in the above manner, it is possible to transmit a 2-bit signal in one transmission. However, the 4-PAM driver consumes the power of VDD * 3I [W] because both the current source I2 through I [A] and the current source I3 through 2I [A] are always in operation. This is three times the power consumed by the 2-PAM driver. Therefore, there is a need for a transmission method that reduces power consumption while enabling transmission of a 2-bit signal in one transmission.

It is an object of the present invention to provide a data transmission circuit that operates at low power.

Exemplary embodiments of the invention include first and second variable resistance circuits connected to a power supply voltage, each having a resistance value that varies with the 2-bit data; A first transistor coupled between the first variable resistance circuit and a current source and controlled by a second data bit of the 2-bit data; And a second transistor connected between the second variable resistance circuit and the current source and controlled by a complementary value of a second data bit of the 2-bit data. .

In an exemplary embodiment, each of the first and second variable resistor circuits comprises: first to third resistors connected in series between the power supply voltage and a corresponding transistor; An XNOR gate coupled to receive the first and second data bits; And a third transistor coupled between the supply voltage and a connection node between the second and third resistors and controlled by the output of the XNOR gate.

In an exemplary embodiment, the first and second transistors are configured as NMOS transistors, and the third transistor is configured as PMOS transistors.

Other exemplary embodiments of the present invention include digital circuitry for converting information to be transmitted into digital data; A pulse amplitude modulation driving circuit for converting N-bit digital data output from the digital circuit into an analog signal; And a transmitter configured to transmit the analog signal, wherein the pulse amplitude modulation driving circuit is connected to a power supply voltage, each of the first and second variable resistance circuits having a resistance value that is variable according to the N-bit digital data. With; A first transistor coupled between the first variable resistance circuit and a current source and controlled by a second data bit of the N-bit digital data; And a second transistor connected between the second variable resistance circuit and the current source and controlled by a complementary value of a second data bit of the N-bit digital data.

In an exemplary embodiment, each of the first and second variable resistor circuits comprises: first to third resistors connected in series between the power supply voltage and a corresponding transistor; An XNOR gate coupled to receive the first and second data bits; And a third transistor coupled between the supply voltage and a connection node between the second and third resistors and controlled by the output of the XNOR gate.

In an exemplary embodiment, the first and second transistors are composed of NMOS transistors, and the third transistor is composed of PMOS transistors.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and that additional explanations of the claimed invention are provided.

Reference numerals are shown in detail in preferred embodiments of the invention, examples of which are shown in the reference figures. In any case, like reference numerals are used in the description and the drawings to refer to the same or like parts.

In the following, a data transmission circuit is used as an example for explaining the features and functions of the present invention. However, one of ordinary skill in the art will readily appreciate the other advantages and performances of the present invention in accordance with the teachings herein, and the present invention may also be implemented or applied through other embodiments. In addition, the detailed description may be modified or changed according to the viewpoint and the application without departing from the scope, technical spirit and other objects of the present invention.

5 is a block diagram schematically showing a transmission circuit according to the present invention.

Referring to FIG. 5, the transmission circuit includes a digital circuit 10, a 4-PAM driver 20, a transmitter 30, and an antenna 40.

Briefly referring to the operation of the transmission circuit configured as described above, the information to be transmitted is converted into digital information, that is, binary data through the digital circuit 10 and output. The binary data output from the digital circuit 10 is converted into an analog signal according to the PAM modulation method by the 4-PAM driver 20 and sent to the transmitter 30. The transmitter 30 transmits the analog signal to the receiver (not shown in the figure) via the antenna 40.

FIG. 6 is a circuit diagram illustrating the 4-PAM driver 20 shown in FIG. 5.

Referring to FIG. 6, the 4-PAM driver 20 of the transmission circuit according to the present invention includes two variable resistors Rvar1 and Rvar2, two NMOS transistors D1 and D2, and one current source I4. It includes.

The second bit voltage Bit2 is connected to the gate of the NMOS transistor D1 and the second complementary bit voltage / Bit2 is connected to the gate of the NMOS transistor D2. Therefore, only one NMOS transistor of the NMOS transistors D1 and D2 is turned on. The sources of the NMOS transistors D1 and D2 are connected to a current source I4 through which a current I [A] flows. One ends of the variable resistors Rvar1 and Rvar2 are connected to the drains of the NMOS transistors D1 and D2, respectively, and the other ends thereof are connected to the external power supply VDD, respectively. Current I [A] flows through the NMOS transistor of one of the two NMOS transistors D1 and D2. Therefore, the voltages of the output terminal Out + and the output terminal Out- connected to the drains of the NMOS transistors D1 and D2 are changed, and are transmitted by the difference between the voltage of the output terminal Out + and the voltage of the output terminal Out-. Can distinguish data.

FIG. 7 is a circuit diagram illustrating in detail the variable resistors Rvar1 and Rvar2 of the 4-PAM driver shown in FIG. 6.

Referring to FIG. 7, the variable resistors Rvar1 and Rvar2 of the transmission circuit according to the present invention include three resistors R5, R6, and R7 connected in series. In this embodiment, the structures of the variable resistor Rvar1 and the variable resistor Rvar2 are the same. Also in this embodiment the three resistors R5, R6, R7 have the same resistance value. It is assumed that the resistance value is R [Ω]. Two resistors R5 and R6 are connected in series between the drain and the source of the PMOS transistor P1. The gate of the PMOS transistor P1 receives a value obtained by performing an XNOR operation on the first bit voltage Bit1 and the second bit voltage Bit2. The PMOS transistor P1 is turned on or off depending on the result of the XNOR operation (indicated by terminal A). Accordingly, the variable resistors Rvar1 and Rvar2 have a value of R [Ω] or 3R [Ω] depending on whether the PMOS transistor P1 is on or off. The XNOR operation is well known, so the detailed description of the XNOR operation is omitted for brevity.

FIG. 8 is a table illustrating values of the variable resistors Rvar1 and Rvar2 according to the first bit voltage Bit1 and the second bit voltage Bit2.

Referring to FIG. 8, when both the first bit voltage Bit1 and the second bit voltage Bit2 are low, a high magnitude voltage is output by the XNOR operation, and thus the PMOS transistor P1 is turned off. Therefore, since three resistors are connected in series, the size of the variable resistors Rvar1 and Rvar2 becomes 3R [Ω].

When the first bit voltage Bit1 is low and the second bit voltage Bit2 is high, a low magnitude voltage is output by the XNOR operation, and thus the PMOS transistor P1 is turned on. Therefore, the sizes of the variable resistors Rvar1 and Rvar2 become R [Ω].

When the first bit voltage Bit1 is high and the second bit voltage Bit2 is low, a low magnitude voltage is output by the XNOR operation, and thus the PMOS transistor P1 is turned on. Therefore, the sizes of the variable resistors Rvar1 and Rvar2 become R [Ω].

When both the first bit voltage Bit1 and the second bit voltage Bit2 are high, a high magnitude voltage is output by the XNOR operation, and thus the PMOS transistor P1 is turned off. Therefore, since three resistors are connected in series, the size of the variable resistors Rvar1 and Rvar2 becomes 3R [Ω].

9 is a table showing the output voltage of the 4-PAM driver 20 shown in FIG.

Referring to FIG. 9, when the first bit voltage Bit1 and the second bit voltage Bit2 are low, the NMOS transistor D1 is turned off and the NMOS transistor D2 is turned on. The size of the variable resistors Rvar1 and Rvar2 is 3R [Ω]. Current I [A] flows through NMOS transistor D2. The voltage at the output terminal Out + becomes (VDD-3R * I) [V] by KVL. The voltage at the output terminal Out- becomes VDD because no current flows through the variable resistor Rvar1. Therefore, the output voltage becomes output terminal (Out +) voltage-output terminal (Out-) voltage = -3R * I [V].

When the first bit voltage Bit1 is low and the second bit voltage Bit2 is high, the NMOS transistor D1 is turned on and the NMOS transistor D2 is turned off. The size of the variable resistors Rvar1 and Rvar2 is R [Ω]. Current I [A] flows through NMOS transistor D1. The voltage at the output terminal (Out-) becomes (VDD-RI) [V] by KVL. The voltage at the output terminal Out + becomes VDD [V] because no current flows through the variable resistor Rvar2. Therefore, the output voltage becomes the output terminal (Out +) voltage-the output terminal (Out-) voltage = R * I [V].

When the first bit voltage Bit1 is high and the second bit voltage Bit2 is low, the NMOS transistor D1 is turned off and the NMOS transistor D2 is turned on. The size of the variable resistors Rvar1 and Rvar2 is R [Ω]. Current I [A] flows through NMOS transistor D2. The voltage at the output terminal Out + becomes (VDD-RI) [V] by KVL. The voltage at the output terminal Out- becomes VDD [V] because no current flows through the variable resistor Rvar1. Therefore, the output voltage becomes the output terminal (Out +) voltage-the output terminal (Out-) voltage = -R * I [V].

When both the first bit voltage Bit1 and the second bit voltage Bit2 are high, the NMOS transistor D1 is turned on and the NMOS transistor D2 is turned off. The size of the variable resistors Rvar1 and Rvar2 is 3R [Ω]. Current I [A] flows through NMOS transistor D1. The voltage at the output terminal (Out-) becomes (VDD-3R * I) [V] by KVL. The voltage at the output terminal Out + becomes VDD [V] because no current flows through the variable resistor Rvar2. Therefore, the output voltage becomes the output terminal (Out +) voltage-the output terminal (Out-) voltage = 3R * I [V].

By changing the size of the pulse in the above manner, it is possible to transmit a 2-bit signal in one transmission. In addition, the 4-PAM driver 20 consumes the power of VDD * I [W] because only the current source I4 flowing the I [A] current operates. Therefore, it can reduce power consumption than general 4-PAM transmission circuit while transmitting 2bit signal at once.

It will be apparent to those skilled in the art that the structure of the present invention may be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is believed that the present invention includes modifications and variations of this invention provided they come within the scope of the following claims and their equivalents.

As described above, the pulse amplitude modulation driving circuit according to the present invention can operate at low power by using only one current source.

Claims (6)

In the pulse amplitude modulation driving circuit for converting 2-bit data into an analog signal by the pulse amplitude modulation method: First and second variable resistance circuits connected to a power supply voltage, each of the first and second variable resistance circuits having a resistance value varied according to the 2-bit data; A first transistor coupled between the first variable resistance circuit and a current source and controlled by a second data bit of the 2-bit data; And And a second transistor coupled between the second variable resistance circuit and the current source and controlled by a complementary value of a second data bit of the 2-bit data. The method of claim 1, Each of the first and second variable resistor circuits First to third resistors connected in series between the power supply voltage and a corresponding transistor; An XNOR gate coupled to receive the first and second data bits; And And a third transistor coupled between the power supply voltage and a connection node between the second and third resistors, the third transistor being controlled by an output of the XNOR gate. The method of claim 2, And the first and second transistors are configured as NMOS transistors, and the third transistor is configured as PMOS transistors. Digital circuitry for converting information to be transmitted into digital data; A pulse amplitude modulation driving circuit for converting N-bit digital data output from the digital circuit into an analog signal; And A transmitter configured to transmit the analog signal, The pulse amplitude modulation driving circuit First and second variable resistance circuits connected to a power supply voltage, each of the first and second variable resistance circuits having a resistance value varied according to the N-bit digital data; A first transistor coupled between the first variable resistance circuit and a current source and controlled by a second data bit of the N-bit digital data; And A second transistor coupled between the second variable resistance circuit and the current source, the second transistor being controlled by a complementary value of a second data bit of the N-bit digital data. The method of claim 4, wherein Each of the first and second variable resistor circuits First to third resistors connected in series between the power supply voltage and a corresponding transistor; An XNOR gate coupled to receive the first and second data bits; And And a third transistor coupled between the power supply voltage and a connection node between the second and third resistors, the third transistor being controlled by an output of the XNOR gate. The method of claim 5, wherein Wherein said first and second transistors are comprised of NMOS transistors, and said third transistor is comprised of PMOS transistors.

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