KR20080062788A - Multi-modulus frequency divider - Google Patents

Abstract

A multi-modulus frequency divider is provided to reduce the size of circuit by omitting capacitors, resistors, and inductors therein. A multi-modulus frequency divider includes an input delay cell(110), a ring voltage control oscillator(100), a bias circuit(180), and a control signal generator(190). The input delay cell delays input frequency signals. The ring voltage control oscillator, which includes plural first and second type delay cells and plural switches, receives the delayed input frequency signals and supplies output frequency signals whose frequency division ratio is determined by operations of the switches. The bias circuit generates bias voltages for controlling currents, which are supplied to the input delay cell and the first and second type delay cells. The control signal generator generates switch control signals for controlling the switches and current control signals for controlling currents flowing in the second type delay cells.

Description

 Multi-modulus frequency divider

1 illustrates a configuration of a frequency divider circuit of a conventional conventional current mode logic (CML) type.

FIG. 2 is a block diagram illustrating a configuration of the flip flop of FIG. 1.

3 is a conventional dual modulus frequency divider capable of adjusting the frequency division ratio to 2 or 3. FIG.

4 is a block diagram illustrating a configuration of a multi-modulus frequency divider according to an embodiment of the present invention.

5 shows a configuration of an input delay cell and a delay cell of a first type.

6 shows a configuration of delay cells of a second type.

7 shows the structure of a delay cell that can replace the first type of delay cell in the differential structure.

8 shows the structure of a delay cell that can replace the second type of delay cell in the differential structure.

<Description of Signs of Major Parts of Drawings>

100: ring type voltage controlled oscillator

110, 120, 130, 140, 150, 160, 170, 180: Delay cell

180: bias circuit

190: control signal generator

The present invention relates to a frequency divider, and more particularly, to a frequency divider capable of varying the division ratio.

Recently, with the development of communication systems and the diversification of digital systems using clocks, frequency synthesizers or clock generators that generate local or clock signals with a wide range of frequencies Required. In this frequency synthesizer or clock generator, a frequency divider for frequency division is used. The frequency divider used to divide a high frequency signal can be classified into various types. Among them, the most commonly used types can be divided into two types. The first type is a frequency divider using CML (Current Mode Logic).

Figure 1 shows the configuration of a conventional conventional CML type frequency divider circuit.

Referring to FIG. 1, a frequency divider circuit is implemented by connecting two flip-flops FF1 and FF2.

FIG. 2 is a block diagram illustrating a configuration of the flip flop of FIG. 1.

Referring to FIG. 2, each flip-flop FF1 and FF2 includes a plurality of transistors M21 to M26 and a current source. In order to operate at a high frequency, the frequency divider uses a CML circuit that implements a logic circuit using a current source as shown in FIG. The biggest drawback of such CML circuits is their high current consumption. In particular, the higher the frequency, the more power is consumed in order to stably divide the frequency.

In addition, a resistor is used to increase the size of the output waveform at the output stage, and the size of the resistor is increased to obtain a large waveform with a small bias current. However, as the resistance increases, the frequency divider becomes difficult to operate at high frequencies. The reason for this is as follows. The parasitic capacitance of the wires and the parasitic capacitance of the wires and the resistance at the output stages show the characteristics of the low pass filter. Larger resistors or larger capacitors limit the operating frequency because the 3dB bandwidth frequency is smaller. To solve this problem, inductors are used instead of resistors at high frequencies. When using an inductor on a silicon wafer, the area of the inductor is so large that the overall area of the frequency synthesizer or clock generator can increase.

Another disadvantage is that it is difficult to vary the frequency division ratio when designing a Modulus frequency divider to vary the frequency division ratio.

3 is a conventional dual modulus frequency divider capable of adjusting the frequency division ratio to 2 or 3. FIG.

Referring to FIG. 3, in the conventional CML Dual Modulus frequency divider, since the logic gates 10 and 20 are additionally used in addition to the CML type flip-flops FF1 and FF2, the operating frequency is limited by the gate delay. Therefore, the CML type modulus frequency divider is not easy to design with three or more division ratios. In order to design a frequency divider requiring various division ratios, an additional CML type frequency divider is required in addition to the dual modulus frequency divider. As a result, it is very difficult to design a frequency divider with a high frequency division ratio while operating at a high frequency with the CML type.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a multi-modulus frequency divider with varying division ratios while operating at high frequencies.

A multi-modulus frequency divider according to an embodiment of the present invention for achieving the above object includes an input delay cell, a ring voltage controlled oscillator, a bias circuit and a control signal generator.

The input delay cell delays the input frequency signal. The ring voltage controlled oscillator includes a plurality of first type delay cells, a plurality of second type delay cells, and a plurality of switches, and receives an input frequency signal delayed by the input delay cell, thereby opening or closing the switches. Provides an output frequency signal whose frequency division ratio is determined. The bias circuit generates a bias voltage for adjusting a current supplied to the input delay cell, the plurality of first type delay cells, and the plurality of second type delay cells. The control signal generator generates a switch control signal for determining opening and closing of the plurality of switches and a current control signal for determining on / off of current flowing in the plurality of second type delay cells.

According to an embodiment, the ring voltage controlled oscillator further includes a locking transistor for synchronizing the input frequency signal with the output frequency signal.

According to an embodiment, the plurality of first type delay cells, the plurality of second type delay cells, and the plurality of switches may form a variable loop by the switch control signal. The frequency division ratio may be determined by the variable loop.

According to an embodiment, the delay degree of the delay cells may be determined by the amount of current supplied to the delay cells.

According to an embodiment, the plurality of first types of delay cells are configured of second and third delay cells of the same type as the first delay cell, and the plurality of second types of delay cells are fourth to seventh. Composed of delay cells, the plurality of switches may include first to fifth switches.

According to an embodiment, the locking transistor may include an NMOS transistor having a drain connected to an input of the third delay cell, a source connected to an output of the third delay cell, and a gate applied to the input frequency signal. Can be.

In some embodiments, the first type of delay cells may include an inverter having one terminal connected to a power supply voltage and a current source connected between the other terminal of the inverter and a ground voltage.

In some embodiments, the current source may include an NMOS transistor to which the bias voltage is applied to a gate.

According to an embodiment, the delay cells of the second type may include an inverter having one terminal connected to the power supply voltage, a current source connected to the other terminal of the inverter, and a switch transistor connected between the current source and the ground voltage. .

In example embodiments, the current source may include an NMOS transistor to which the bias voltage is applied to a gate, and the switch transistor may include an NMOS transistor to which the current control signal is applied to a gate.

According to an embodiment, the plurality of first type delay cells and the plurality of second type delay cells may each have a differential structure that receives a positive input frequency signal and a negative frequency signal.

According to an embodiment, the plurality of switches may be configured as a transmission gate.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

On the other hand, when an embodiment is otherwise implemented, a function or operation specified in a specific block may occur out of the order specified in the flowchart. For example, two consecutive blocks may actually be performed substantially simultaneously, and the blocks may be performed upside down depending on the function or operation involved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

4 is a block diagram illustrating a configuration of a multi-modulus frequency divider according to an embodiment of the present invention.

Referring to FIG. 4, a multi-modulus frequency divider according to an embodiment of the present invention includes an input delay cell 110, a ring voltage controlled oscillator 100, a bias circuit 180, and a control signal generator 190. Include.

The ring voltage controlled oscillator 100 includes second to seventh delay cells 120, 130, 140, 150, 160 and 170 and first to fifth switches S1, S2, S3, S4 and S5. Although not shown, the first to fifth switches S1, S2, S3, S4, and S5 may be configured as transmission gates.

The second and third delay cells 120 and 130 are configured in the same form as the input delay cell 110. The second and third delay cells 120 and 130 are referred to as a first type. The fourth to seventh delay cells 140, 150, 160 and 170 are referred to as a second type in a different form from the second and third delay cells 120 and 130. Delay cells are connected in series with each other. The first switch S1 connects the output of the seventh delay cell 170 to an output frequency signal. The second switch S2 connects the output of the sixth delay cell 160 to an output frequency signal. The third switch S3 connects the output of the fifth delay cell 150 to an output frequency signal. The fourth switch S4 connects the output of the fourth delay cell 140 to an output frequency signal. The fifth switch S5 connects the output of the third delay cell 130 to an output frequency signal. In addition, when the locking transistor M1 is turned on, the fifth switch S5 connects the output of the second delay cell 120 to an output frequency signal.

5 shows a configuration of an input delay cell and a delay cell of a first type. 6 shows a configuration of delay cells of a second type.

5 and 6, a delay cell of a first type includes an inverter (composed of M52 and M53) connected to a power supply voltage and a current source M51 connected to an inverter and a ground voltage. The inverter is configured by connecting the PMOS transistor M53 and the NMOS transistor M52 in a cascode form. The current source M51 connected to the inverter in the form of a cascode is composed of NMOS transistors, and a bias voltage is applied to the gate.

The second type of delay cell includes an inverter (composed of M63 and M64) connected to a power supply voltage, a current source M62 connected to the inverter, and a switch transistor M61 connected between the current source M62 and a ground voltage. The inverter is configured by connecting the PMOS transistor M64 and the NMOS transistor M63 in a cascode form. The current source M62 connected to the inverter in the form of a cascode is composed of NMOS transistors. The switch transistor M61 connected to the current source M62 in the form of a cascode is composed of an NMOS transistor. Obviously, the current sources M51 and M62 may be configured as other types of current sources other than the NMOS transistor.

Referring back to FIG. 4, a locking transistor M1 for synchronizing an input frequency signal with an output frequency signal is connected to the third delay cell 130. The locking transistor M1 has a drain connected to the input of the third delay cell 130, a source connected to the input of the third delay cell 130, and a gate configured as an NMOS transistor receiving an input frequency signal. The locking transistor M1 serves to eliminate the delay caused by the third delay cell 130.

Hereinafter, an operation of a multi-modulus divider according to an embodiment of the present invention will be described with reference to FIGS. 4 to 6.

The input frequency signal is delayed through the first delay cell 110 and input to the ring voltage controlled oscillator. In addition, the input frequency signal is provided to the gate of the locking transistor M1, and when the input frequency signal is high, the output of the second delay cell 120 is transferred to the fourth delay cell 140 without delay.

Input The input delay cell 100 and the second to seventh delay cells 120, 130, 140, 150, 160 and 170 include an inverter (consisting of M52 and M53) and a current source M53. The current source includes a bias circuit ( The bias voltage generated at 180 is applied. By the bias voltage, the amount of current flowing through the current sources M51 and M62 can be adjusted to control the delay of the delay cells. The second type of delay cells include a switch transistor M61, and the on / off of the switch transistor M61 is determined by a current control signal provided from the control signal generator 190. That is, the delay type of the delay cells of the second type are controlled by cutting off the current supplied to the current source M62.

The control signal generator 190 generates a switch control signal for determining the opening and closing of the switches S1 to S5. The division ratio of the multi-modulus frequency divider is determined according to the switch whose opening and closing is determined by this switch control signal. In addition, the division ratio of the frequency divider is determined according to the delay degree of the delay cells.

For example, the oscillation frequency (output frequency signal) of the ring voltage controlled oscillator constituted by a loop composed of delay cells 120 to 170 and the first switch S1 is the lowest. In this case, all other switches are off. In addition, the oscillation frequency of the ring voltage controlled oscillator constituted by the loop composed of the delay cells 120 to 130 and the fifth switch S5 is the highest.

For example, if the input frequency signal is 6 GHz and the oscillation frequency of the ring voltage controlled oscillator 100 is 3 GHz, the output frequency of the frequency divider is 3 GHz, in which case the frequency division ratio is 2. If the oscillation frequency of the ring voltage controlled oscillator 100 is 2 GHz by adjusting the switch control signal and the current control signal, the division ratio becomes 3. In this way, by adjusting the switch control signal and the current control signal to adjust the loop constituting the ring voltage controlled oscillator, the frequency division ratio can be adjusted. 4, the frequency division ratios obtained by adjusting the switch control signal and the current control signal are 2, 3, 4, 5, and 6. In addition, if the delay level of the delay cells is adjusted through the bias voltage, decimal division ratios such as 4.5 or 6.5 are possible. It will be apparent to those skilled in the art that a larger number of division ratios can be obtained by further including delay cells and switches in the configuration as shown in FIG. 4.

The power consumed by the multi-modulus frequency divider according to the embodiment of the present invention is 0.24 mW, which is about 1/10 of the power consumed by the CML type frequency divider.

In the above, the multi-modulus frequency divider having a single input / output structure has been described. A frequency divider having a differential structure with in-phase mode noise or noise generated from the power supply unit is required.

7 shows the structure of a delay cell that can replace the first type of delay cell in the differential structure. 8 shows the structure of a delay cell that can replace the second type of delay cell in the differential structure.

Referring to FIGS. 7 and 8, in a differential structure, delay cells of the first type may include inverters (composed of M72 and M73) to which positive input frequency signals are input, and inverters (M74 and M75) to which negative input frequency signals are input. Configuration) and a current source M71 to which a bias voltage is applied. In addition, the second type of delay cells include an inverter (composed of M83 and M84) to which a positive input frequency signal is input, an inverter (composed of M85 and M86) to which a negative input frequency signal is input, and a current source (M82) to which a bias voltage is applied. ) And a switch transistor M81 to which a current control signal is applied. Since the operation of the multi-modulus frequency divider including the delay cells of the differential structure is similar to that of the multi-modulus frequency divider having a single input / output structure, description thereof will be omitted. The delay cells of the differential structure increase the number of transistors included to increase power consumption, but have an advantage of being resistant to external noise.

As described above, the multi-modulus frequency divider according to the embodiment of the present invention can reduce the size of the circuit because no capacitor, resistor, or inductor is used, and it is easy to design because the number of transistors used is small. In addition, the circuit is simple, greatly reducing the power consumed. In addition, by adjusting the number of delay cells and switches, the division ratio can be variously designed.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (13)

An input delay cell for delaying an input frequency signal; And a plurality of first type delay cells, a plurality of second type delay cells, and a plurality of switches, and are provided with a delayed input frequency signal by the input delay cell, whereby a frequency division ratio is determined by whether the switches are opened or closed. A ring voltage controlled oscillator providing an output frequency signal; A bias circuit for generating a bias voltage for regulating a current supplied to the input delay cell, the plurality of first type delay cells and the plurality of second type delay cells; And And a control signal generator configured to generate a switch control signal for determining opening and closing of the plurality of switches and a current control signal for determining on / off of current flowing through the plurality of second type delay cells. Modulus frequency divider. 2. The multi-modulus frequency divider of claim 1, wherein the ring voltage controlled oscillator further comprises a locking transistor for synchronizing the input frequency signal with the output frequency signal. 3. The multi-modulus of claim 2, wherein the plurality of first type delay cells, the plurality of second type delay cells, and the plurality of switches form a variable loop according to the switch control signal. Frequency divider. 4. The multi-modulus frequency divider of claim 3, wherein the frequency division ratio is determined by the variable loop. 4. The multi-modulus frequency divider of claim 3, wherein a delay degree of the delay cells is determined by a magnitude of current supplied to the delay cells. 3. The method of claim 2, wherein the plurality of first types of delay cells are configured of second and third delay cells of the same type as the first delay cell, and the plurality of second types of delay cells are fourth to fourth. And a plurality of delay cells, wherein the plurality of switches comprises first to fifth switches. The NMOS transistor of claim 6, wherein the locking transistor comprises an NMOS transistor having a drain connected to an input of the third delay cell, a source connected to an output of the third delay cell, and a gate applied to the input frequency signal. Multi-modulus frequency divider. 7. The multi-modulus frequency divider of claim 6, wherein the first type delay cells comprise an inverter having one terminal connected to a power supply voltage and a current source connected between the other terminal of the inverter and a ground voltage. . 9. The multi-modulus frequency divider of claim 8, wherein the current source comprises an NMOS transistor to which the bias voltage is applied to a gate. The method of claim 6, wherein the second type of delay cells include an inverter having one terminal connected to the power supply voltage, a current source connected to the other terminal of the inverter, and a switch transistor connected between the current source and the ground voltage. Features a multi-modulus frequency divider. 12. The multi-modulus of claim 10, wherein the current source includes an NMOS transistor to which the bias voltage is applied to a gate, and the switch transistor comprises an NMOS transistor to which the current control signal is applied to a gate. Frequency divider. The method of claim 6, wherein the plurality of first type delay cells and the plurality of second type delay cells each include a first inverter and a second inverter configured to receive a positive input frequency signal and a negative frequency signal. Multi-modulus frequency divider, characterized by a differential structure. 3. The multi-modulus frequency divider of claim 2, wherein said plurality of switches are comprised of transmission gates.

Images