KR20080062536A - Method of manufacturing semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to remove particles remaining after a CMP(Chemical Mechanical Polishing) process by a nitride layer hard mask and a poly silicon layer hard mask on an upper portion of a bit line. Plural bit lines(220) are formed on a semiconductor substrate(200). A nitride layer hard mask(216) and a poly silicon layer hard mask are laminated on an upper portion of the bit lines. A dielectric is formed on the semiconductor substrate where the bit line is formed to cover the bit lines. A CMP process is performed on the dielectric to expose the poly silicon layer hard mask of the bit line. The dielectric is etched to form a hole. A conductive layer(214) for gap-filling the hole is deposited to form a storage node contact plug(240). After the bit lines are formed and before the dielectric is formed to cover the bit lines, a nitride layer(222) for a spacer is formed on both sidewalls of the bit line.

Description

Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

1 is a photograph of a semiconductor device showing a particle remains after the CMP process.

2A through 2F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to an embodiment of the present invention.

3 is a graph showing the polishing amount of the polysilicon film according to the pH change.

* Description of the symbols for the main parts of the drawings *

200 semiconductor substrate 210 interlayer insulating film

212: barrier film 214: conductive film for bit line

216: nitride film hard mask 218: polysilicon film hard mask

220: bit line 222: nitride film for spacer

230: insulation film H: hole for storage node contact plug

240: storage node contact plug

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of removing residual particles generated after CMP (Chemical Mechanical Polishing).

As is well known, in a semiconductor device such as a DRAM, a current is supplied to a junction region so that charge is stored in a capacitor through a channel, or an amount of charge difference between capacitors is converted into an amplifier so that the charge stored in the capacitor can be converted into data. Bit line is formed to transfer to.

In addition, the capacitor functions as a storage place for storing data, and is formed in a structure in which a dielectric film is interposed between the storage node and the plate node.

On the other hand, as the integration of semiconductor goggles increases, the size of the contact hole, which serves as an electrical connection path between the upper and lower conductors, is gradually decreasing. Accordingly, a method of forming a storage node contact in a line type has been proposed.

Hereinafter, a manufacturing method of a conventional semiconductor device including a line type storage node contact forming process will be briefly described.

First, a conductive film for a bit line is formed on a semiconductor substrate, a hard mask is formed on the conductive film, and the bit mask is sequentially formed by etching the hard mask and the conductive film. In the case of the 0.54 탆 DRAM device, a laminated film of a nitride film and a tungsten film is used as the hard mask.

Subsequently, an insulating film is deposited to fill the space between the bit lines on the bit line formed product, and then the insulating film is chemically polished (CMP) until the hard mask of the bit line is exposed to planarize the bit lines. Then, the substrate product on which the CMP was performed is cleaned.

Next, a mask pattern having a line type opening is formed while exposing a storage node contact forming region between the bit lines on the CMP insulating layer, and the insulating layer is etched using the mask pattern as an etching mask. Form a contact hole for.

Subsequently, the contact hole for the storage node is filled with a polysilicon layer, and the polysilicon layer is etched back until the hard mask of the bit line is exposed to form a line type storage node contact.

Subsequently, although not shown, a series of subsequent known processes are sequentially performed to fabricate the semiconductor device.

However, in the conventional case, since the insulating film and the tungsten film hard mask are exposed after the CMP process of the insulating film, the SC-1 (Standard Clean-1) solution cannot be used for cleaning. Therefore, the removal of particles remaining after the CMP process is prevented. It doesn't work out.

1 is a photograph of a semiconductor device showing a state in which particles remain after a CMP process.

In addition, in the conventional case, since the interface property between the tungsten film hard mask and the nitride film hard mask is not good, the bit line may be thinned or lost in a subsequent process.

Accordingly, the present invention provides a method of manufacturing a semiconductor device capable of effectively removing particles remaining after CMP (Chemical Mechanical Polishing).

In addition, the present invention provides a method of manufacturing a semiconductor device capable of improving the interface characteristics of the bit line hard masks.

In one embodiment, a method of manufacturing a semiconductor device includes: forming a plurality of bit lines having a nitride film hard mask and a polysilicon film hard mask stacked on a semiconductor substrate; Forming an insulating layer on the semiconductor substrate on which the bit lines are formed to cover the bit lines; Chemical mechanical polishing (CMP) of the insulating layer to expose the polysilicon layer hard mask of the bit line; Etching the insulating film to form a hole; And depositing a conductive layer to fill the hole to form a storage node contact plug.

And forming a nitride nitride film for spacers on both sidewalls of the bit line after the forming of the bit lines and before forming the insulating layer to cover the bit lines.

The insulating film is formed of a SOD (Spin-On Dielectric) film.

And annealing the semiconductor substrate on which the insulating film is formed after the forming of the insulating film and before the CMP of the insulating film.

CMP of the insulating film is performed using a slurry having a pH of 1-9.

CMP of the insulating film is performed using a ceria slurry.

The ceria slurry contains 0.1 to 10 wt% abrasive.

And cleaning the semiconductor substrate to remove particles remaining after the CMP of the insulating film, after the CMP of the insulating film and before the etching of the insulating film to form a hole.

The washing is carried out using SC-1 (Standard Clean-1) solution.

The cleaning is performed using at least one of SC-1 (Standard Clean-1) solution, Sulfuric Perioxide Mixture (SPM) and Buffer Oxide Etchant (BOE).

The forming of the storage node contact plug may include depositing a conductive film on a semiconductor substrate to fill the hole; And CMP or etch back the polysilicon film hard mask of the conductive film and the bit line until the nitride film hard mask of the bit line is exposed.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, after forming a bit line on which a nitride hard mask and a polysilicon film hard mask are stacked, the insulating film is deposited to cover the bit line, and then the CMP is exposed to expose the polysilicon film hard mask. do. The CMP substrate result is then cleaned to remove particles remaining after the CMP.

In this case, since the insulating film and the polysilicon film hard mask are exposed after the CMP, the SC-1 (Standard Clean-1) solution can be used during the cleaning, and thus, particles remaining in the substrate result can be completely removed.

In addition, since the present invention uses a slurry having a pH of 9 or less at the time of CMP, the polishing rate of the polysilicon film is slowed to increase the margin of the CMP process, and in addition, to use a ceria slurry having excellent local planarization characteristics at the time of CMP. Therefore, dishing of the insulating layer may be minimized.

2A through 2F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to an embodiment of the present invention.

Referring to FIG. 2A, an interlayer insulating layer 210 is formed on the semiconductor substrate 200 on which a predetermined substructure (not shown) is formed to cover the substructure. Subsequently, a barrier film 212, a bit line conductive film 214, a nitride film hard mask 216, and a polysilicon film hard mask 218 are sequentially deposited on the interlayer insulating film 210, and then, these (218,216,214,212) are deposited. Etch to form bit lines 220 having the nitride film 216 hard mask and the polysilicon film hard mask 218 stacked thereon.

Subsequently, after the nitride film is deposited on the entire surface of the substrate 200 including the bit line 220, the nitride film is etched back to form the spacer nitride film 222 of the bit line 220.

Referring to FIG. 2B, an insulating layer 230 is deposited to cover the bit lines 220 on the substrate 200 on which the bit lines 220 are formed. The insulating film 230 is formed of a spin-on dielectric (SOD) film, and after depositing the insulating film 230, annealing is preferably performed to harden the insulating film 230.

Referring to FIG. 2C, the insulating film 230 is subjected to chemical mechanical polishing (CMP) until the polysilicon film hard mask 218 of the bit line 220 is exposed. The CMP is performed using a ceria slurry having a pH of 9 or less and containing about 0.1 to 10 wt% of an abrasive.

In this case, since the CMP is performed using a slurry having a pH of 9 or less, the polishing rate of the polysilicon film is very slow, thereby increasing the margin of the CMP process, and the CMP uses a ceria slurry having excellent local planarization characteristics. As a result, dishing of the insulating layer 230 can be minimized.

Referring to FIG. 2D, the resultant of the substrate 200 on which the CMP is performed is cleaned to remove particles remaining after the CMP. The washing is performed using a Standard Clean-1 (SC-1) solution, and also using one or more of the SC-1 solution and Sulfuric Perioxide Mixture (SPM) and Buffer Oxide Etchant (BOE).

In the present invention, since the insulating film 230 and the polysilicon film hard mask 218 are exposed after the CMP, the SC-1 solution may be used during the cleaning, thereby effectively removing particles remaining on the substrate resultant. Can be.

Referring to FIG. 2E, a mask pattern including a bit line 220 on a result of the substrate 200 on which the cleaning is performed, exposing a storage node contact plug forming region between the bit lines 220 (not shown). To form. Next, the insulating layer and the interlayer insulating layer 210 exposed by the mask pattern are etched to form a line type storage node contact plug hole H, and then the mask pattern is removed.

Referring to FIG. 2F, a polysilicon layer is deposited on a resultant of the substrate 200 to fill the hole H for the storage node contact plug, and then a polysilicon layer hard mask of the polysilicon layer and the bit line 220 is formed. 218 is etched back or CMP until the nitride film hard mask 216 of the bit line 220 is exposed to form a line type storage node contact plug 240 in the storage node contact plug formation region of the semiconductor substrate 200. ).

Subsequently, although not shown, a series of subsequent known processes are sequentially performed to complete the semiconductor device according to the embodiment of the present invention.

Here, since the present invention uses a slurry having a pH of 9 or less during the CMP process of the insulating film, the polishing rate of the polysilicon film may be slowed to increase the margin of the CMP process, and a ceria slurry having excellent local planarization characteristics during the CMP process may be obtained. Because of this, it is possible to minimize the leveling of the insulating film.

3 is a graph showing the polishing amount of the polysilicon film according to the pH change.

As shown, when the pH is 9 or less, the polishing amount of the polysilicon film is remarkably reduced, thereby increasing the margin of the CMP process.

In addition, since the present invention uses a laminated film of a nitride film and a polysilicon film as a hard mask of the bit line, it is possible to use the SC-1 solution during the cleaning performed after the CMP, thereby effectively removing particles remaining after the CMP. have.

In addition, the polysilicon film hard mask plays a role of minimizing the loss of the nitride film hard mask, and since the interface property with the nitride film is superior to that of the conventional tungsten film, it is possible to prevent the thin line or the loss of the bit line during the subsequent process. have.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention can effectively remove particles remaining after the CMP process by forming a nitride film hard mask and a polysilicon film hard mask on the bit line.

In addition, the present invention can increase the margin of the CMP process by using a ceria slurry having a pH of 9 or less during the CMP process, it is possible to minimize the dipping phenomenon of the insulating film.

In addition, the present invention uses the polysilicon film hard mask instead of the conventional tungsten film hard mask, thereby improving the interfacial characteristics with the nitride film hard mask, thereby preventing the bit line from being thinned or lost during subsequent processing.

Claims (11)

Forming a plurality of bit lines on which a nitride hard mask and a polysilicon film hard mask are stacked on a semiconductor substrate; Forming an insulating layer on the semiconductor substrate on which the bit lines are formed to cover the bit lines; Chemical mechanical polishing (CMP) of the insulating layer to expose the polysilicon layer hard mask of the bit line; Etching the insulating film to form a hole; And Depositing a conductive layer to fill the hole to form a storage node contact plug; Method of manufacturing a semiconductor device comprising a. The method of claim 1, After the forming of the bit lines, and before forming the insulating film to cover the bit lines, Forming a nitride film for spacers on both sidewalls of the bit line; Method of manufacturing a semiconductor device further comprising. The method of claim 1, The insulating film is a manufacturing method of a semiconductor device, characterized in that formed by a SOD (Spin-On Dielectric) film. The method of claim 1, After the forming of the insulating film, and before the CMP of the insulating film, And annealing the semiconductor substrate having the insulating layer formed thereon. The method of claim 1, CMP of the insulating film is a semiconductor device manufacturing method, characterized in that performed using a slurry having a pH of 1-9. The method of claim 1, CMP of the insulating film is a semiconductor device manufacturing method, characterized in that performed using a ceria slurry. The method of claim 6, And the ceria slurry contains 0.1 to 10 wt% of abrasive. The method of claim 1, After the CMP of the insulating film, and before forming a hole by etching the insulating film, And cleaning the semiconductor substrate such that particles remaining after the CMP of the insulating film are removed. The method of claim 8, The cleaning is a method of manufacturing a semiconductor device, characterized in that carried out using a SC-1 (Standard Clean-1) solution. The method of claim 9, The cleaning is performed by using a SC-1 (Standard Clean-1) solution, SPM (Sulfuric Perioxide Mixture) and at least one or more of BOE (Buffer Oxide Etchant). The method of claim 1, Forming the storage node contact plug, Depositing a conductive film on a semiconductor substrate to fill the hole; And CMP or etching back the conductive film and the polysilicon film hard mask of the bit line until the nitride film hard mask of the bit line is exposed; Method of manufacturing a semiconductor device comprising a.

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