KR20080062530A - Electro static discharge protect circuit - Google Patents

Abstract

An electro-static discharge protection circuit is provided to lower an operation voltage of the electro-static discharge protection circuit and to be rapidly turned on by forming a trigger unit. A main discharge unit(20) discharges static electricity flowed from a pad(P2) to a first power line or a second power line. A power clamp unit(24) discharges the static electricity discharged to the first power line or the second power line. A trigger unit(26) is connected between one of the first and second power lines and the pad to detect a detection voltage by the static electricity and to drive the main discharge unit and the power clamp unit. The main discharge unit has a PMOS transistor(P20) and NMOS transistors(N20,N24). The PMOS transistor is connected between the first power line and the pad. A gate and a drain of the PMOS transistor are connected to each other. The NMOS transistors are connected between the second power line and the pad. A gate of the NMOS transistor receives the detection voltage.

Description

Electrostatic Discharge Protect Circuit

1 is an electrostatic discharge protection circuit according to the prior art.

2 is an electrostatic discharge protection circuit according to the first embodiment of the present invention.

3 is a waveform diagram showing the operation of the NMOS transistor according to the prior art and the present invention;

4 is an electrostatic discharge protection circuit according to a second embodiment of the present invention.

TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly, to an electrostatic discharge protection circuit that protects an internal circuit from static electricity.

Generally, semiconductor devices have an electrostatic discharge protection circuit for protecting an internal circuit from static electricity.

Referring to FIG. 1, a conventional electrostatic discharge protection circuit may include a discharge unit 10 for discharging static electricity introduced into a pad P1 to a power line 17 or a ground line 18, between a pad P1 and a ground line 18. Discharged to the upper power line 17 or ground line 18 discharged to the upper power line 17 or the ground line 18 connected to the secondary discharge unit 12 and the power line 17 or ground line 18 to protect the internal circuit (19) It is configured to include a power clamp unit 14 to.

As the current discharge unit 10, a GPPMOS transistor P10 and a GGNMOS transistor N10 are configured, and the auxiliary discharge unit 12 includes a resistor R10 and a GGNMOS transistor N12, and the power clamp unit 14 is an NMOS. The transistor N14 is configured.

When the static electricity flows into the pad P1, the electrostatic discharge protection circuit drains the transistors N10, N12, N14, and P10 constituting the discharging portion 10, the auxiliary discharge portion 12, and the power clamp portion 14. It is operated by parasitic bipolar operation according to the Avalanche Break down phenomenon between the substrate and the substrate. The trigger voltage at this time is approximately 8V.

However, as the integration density of semiconductor devices increases, the breakdown voltage is lowered as the thickness of the gate oxide dielectric layer of the elements constituting the internal circuit becomes thinner, thereby reducing the operating voltage and increasing the demand for an electrostatic discharge protection circuit having a high turn-on speed.

It is therefore an object of the present invention to provide an electrostatic discharge protection circuit having a low operating voltage.

In addition, another object of the present invention to provide an electrostatic discharge protection circuit capable of fast turn-on operation.

In order to achieve the above object, the present invention provides an electrostatic discharge protection circuit provided between a first power supply line and a second power supply line to protect internal circuits from static electricity. A kitchen part discharging to the second power line; A power clamp unit configured to discharge the static electricity discharged to the first or second power line to the first or second power line upward; And a trigger unit connected between any one of the first and second power lines and the pad to detect a detection voltage caused by the static electricity to drive the kitchen unit and the power clamp unit.

The discharging part includes a PMOS transistor connected between the first power line and the pad and having a gate and a drain connected thereto; And an NMOS transistor connected between the second power line and the pad and receiving the detection voltage as a gate.

The power clamp unit includes an NMOS transistor configured to receive the detection voltage through a gate.

The trigger unit may include a resistor connected between one of the first and second power lines and the discharge unit to detect the detection voltage; And a diode chain connected between the pad and the resistor.

The diode chain is composed of a plurality of diodes connected in series, the diode chain is preferably driven at a voltage higher than the operating voltage of the internal circuit.

Preferably, the first power line is a power voltage line, and the second power line is a ground voltage line.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The present invention provides an electrostatic discharge protection circuit having a trigger portion between an input / output pad and a power line and detecting a detected voltage from the trigger portion to drive the kitchen portion and the power clamp portion to lower the operating voltage and improve the operation speed. An example may be implemented as shown in FIG. 2.

Referring to FIG. 2, an internal circuit 29 may be connected between the power distributing part 20, which bypasses the static electricity flowing into the pad P2, to the power line 27 and the ground line 28, and the pad P2 and the ground line 28. A power clamp unit 24 for discharging the static electricity discharged to the auxiliary discharge unit 22, the power line 27, or the ground line 28 to the upper power line 27 or the ground line 28 to protect the discharge; It is configured to include a trigger unit 26 for lowering the operating voltage of the current discharging unit 20 and the power clamp unit 24.

The kitchen unit 20 includes a GPPMOS transistor P20 connected to a power supply line 27 and a pad P2, and an NMOS transistor N20 connected to a ground line 28 and a pad P2, and these transistors P20 and N20 flow in. In accordance with the static electricity is generated by the diode and transistor to discharge the static electricity to the power line 27 or ground line 28.

The auxiliary discharge unit 22 includes a resistor R20 connected between the pad P2 and the internal circuit 29 and a GGNMOS transistor N22 connected between the internal circuit 29 and the ground line 28. The static electricity is discharged to the ground line 28.

The power clamp part 24 is connected between the power supply line 27 and the ground line 28, and has an NMOS transistor N24 having a gate connected in common with the gate of the NMOS transistor N20 of the kitchen unit 20. In addition, by discharging the static electricity discharged to the power line 27 or ground line 28 to the opposite power line 27 or ground line 28, the power line 27 and the ground line 28 to a constant voltage Keep it.

The trigger unit 26 includes a diode chain 25 and a resistor R22 connected in series between the pad P2 and the ground line 28, and the common node N1 of the diode chain 25 and the resistor R22. Is applied to the gates of the NMOS transistors N20 and N24.

The diode chain 25 may be composed of a plurality of diodes D21, D22, and D23 connected in series, an anode of each diode is connected in the direction of the pad P1, and a cathode is connected in the direction of the resistor P22.

Here, the number of diodes constituting the diode chain 25 is preferably adjusted to have an operating voltage higher than the normal operating voltage of the internal circuit 20. For example, when the operating voltage of the internal circuit 29 is 1.8V, the diode chain 25 operates at approximately 2.1V or more by connecting three or more diodes having a cut-in voltage of approximately 0.7V in series. Configure to

Accordingly, the trigger unit 26 operates quickly when static electricity above the operating voltage of the diode chain 25 flows to increase the gate voltage of the NMOS transistors N20 and N24, thereby causing the NMOS transistors N20 and N24 to be averranged. Operates at an operating voltage lower than the breakdown voltage to discharge static electricity.

Referring to Figure 2 looks at the operation of the electrostatic discharge protection circuit of the present invention.

When positive (+) static electricity flows into the pad P2, the GPPMOS transistor P20 of the kitchen unit 20 performs a PN diode operation to apply a current according to the static electricity to the power line 27. At this time, the high voltage due to static electricity turns on the diode chain 25 of the trigger unit 26 to detect the detection voltage according to the voltage drop generated at the node N1.

The transient current due to the static electricity applied to the power supply line 27 raises the drain voltage of the NMOS transistor N24 of the power clamp unit 24, and the detected voltage detected at the node N1 increases the gate voltage of the NMOS transistor N24. As it is turned on, it quickly discharges static electricity to the ground line 28. At the same time, since the detection voltage detected at the node N1 raises the gate voltage of the NMOS transistor N20 of the current collector 20, the NMOS transistor N20 is turned on at a voltage lower than the avalanche breakdown voltage, thereby grounding static electricity to the ground line 28. To discharge).

Referring to FIG. 3, when the operation waveform of the GGNMOS transistor (N10 of FIG. 1) of the conventional electrostatic discharge protection circuit is viewed, the trigger voltage is approximately 8.7V, while the NMOS transistor of the electrostatic discharge protection circuit of the present invention (FIG. Referring to B of the operation waveform of N20) of 2, the trigger voltage is approximately 4.3V. This means that the electrostatic discharge hobo circuit of the present invention is operated at a low operating voltage.

Here, the horizontal axis represents the avalanche breakdown trigger voltage V, and the vertical axis represents the current I due to electrostatic discharge.

Referring to FIG. 4, the electrostatic discharge protection circuit according to the second embodiment of the present invention is configured in the same manner as the first embodiment of the discharging portion 30, the auxiliary discharge portion 32, and the power clamp portion 34. . That is, each component 30, 32, and 34 of FIG. 3 corresponds to 20, 22, and 24 of FIG. 2, and redundant description thereof will be omitted.

On the other hand, by varying the number of diodes D31, D32, ..., D3N constituting the diode chain 35 of the trigger unit 36, the capacitance of the parasitic capacitance is reduced, thereby improving the signal delay speed, thereby improving the static electricity having a short rising period. Discharge effectively.

Therefore, according to the present invention, the trigger unit has an effect of lowering the operating voltage of the electrostatic discharge protection circuit and turning on it in a short time to secure the internal circuit.

In addition, according to the present invention has an effect of providing an electrostatic discharge protection circuit with a high operating speed by preventing the increase in capacitance by configuring the trigger portion of the diode chain.

Claims (8)

In the electrostatic discharge protection circuit provided between the first power line and the second power line to protect the internal circuit from static electricity, A discharge unit discharging the static electricity flowing from the pad to the first or second power line; A power clamp unit configured to discharge the static electricity discharged to the first or second power line to the first or second power line upward; And A trigger unit connected between any one of the first and second power lines and the pad to detect a detection voltage by the static electricity to drive the kitchen unit and the power clamp unit; Electrostatic discharge protection circuit, characterized in that comprising a. The method of claim 1, All the kitchen A PMOS transistor connected between the first power line and the pad and having a gate and a drain connected thereto; And An NMOS transistor connected between the second power line and the pad and receiving the detection voltage as a gate; Electrostatic discharge protection circuit comprising: a. The method of claim 1, And the power clamp unit includes an NMOS transistor configured to receive the detection voltage through a gate. The method of claim 1, The trigger unit A resistor connected between any one of the first and second power lines and the discharge unit to detect the detection voltage; And A diode chain connected between the pad and the resistor; Electrostatic discharge protection circuit, characterized in that comprising a. The method of claim 4, wherein And said diode chain is comprised of a plurality of diodes connected in series. The method of claim 4, wherein And the diode chain is driven at a voltage higher than the operating voltage of the internal circuit. The method of claim 1, And the first power line is a power voltage line. The method of claim 1, And the second power line is a ground voltage line.

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