KR20080062009A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
KR20080062009A
KR20080062009A KR1020060137255A KR20060137255A KR20080062009A KR 20080062009 A KR20080062009 A KR 20080062009A KR 1020060137255 A KR1020060137255 A KR 1020060137255A KR 20060137255 A KR20060137255 A KR 20060137255A KR 20080062009 A KR20080062009 A KR 20080062009A
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KR
South Korea
Prior art keywords
layer
film
gate
insulating film
forming
Prior art date
Application number
KR1020060137255A
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Korean (ko)
Inventor
박성민
주영환
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020060137255A priority Critical patent/KR20080062009A/en
Publication of KR20080062009A publication Critical patent/KR20080062009A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Abstract

A semiconductor device and a manufacturing method thereof are provided to increase a channel region by growing a silicon epitaxial layer and forming a gate for surrounding the silicon epitaxial layer. A groove is formed in a gate region of a semiconductor substrate(200). A first gate insulating layer is formed on a bottom surface of the groove. A channel layer is formed on an upper surface of the first gate insulating layer. A second gate insulating layer(222) is formed on an upper surface and a lower surface of the channel layer. A gate conduction layer(224) is formed to surround the second gate insulating layer and the channel layer. The channel layer is composed of a silicon epitaxial layer.

Description

Semiconductor device and method for manufacturing same {SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

2A to 2F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

200 semiconductor substrate T trench for device isolation film

212: insulating film 220: silicon epi layer

222: gate insulating film 224: gate conductive film

230: gate

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same that can improve the accuracy and density of current flow control in a DRAM (DRAM) device.

As semiconductor devices are highly integrated, channel lengths of transistors are decreasing, and ion implantation concentrations into junction regions (source / drain regions) are increasing.

As a result, a so-called short channel effect is generated in which interference between the source / drain regions increases, control of the gate decreases, and the threshold voltage Vt rapidly decreases. In addition, a problem arises in that the refresh characteristics are deteriorated due to an increase in the junction leakage current due to an increase in the electric field of the junction region. Therefore, the structure of a transistor having a conventional planar channel structure has reached its limit in overcoming the problems associated with the high integration.

Accordingly, various methods of forming recess gates capable of securing an effective channel length have been proposed.

Hereinafter, a conventional recess gate forming method will be briefly described.

First, the device isolation region of the semiconductor substrate having the active region and the device isolation region is etched to form a trench, and then an element isolation film defining an active region of the substrate is formed in the trench.

Subsequently, after recessing the active region of the semiconductor substrate on which the device isolation film is formed, a gate insulating film is deposited on the entire surface of the recessed substrate, and then a conductive material such as a polysilicon film or a tungsten film is formed on the gate insulating film. The material is used to deposit the gate conductive film.

Subsequently, the gate conductive layer and the gate insulating layer are etched to form a recess gate on the recessed portion of the substrate active region.

In the case of forming the recess gate, the effective channel length is increased compared to the gate of the conventional planar channel structure, so that the current is easily controlled and the low threshold voltage due to the high channel doping concentration is solved to some extent. do.

Further, in order to further increase the effective channel length, studies have been made on a method of forming a bulb type groove in a recess gate formation region. In the case of the bulb type recess gate, as the channel length is further increased, the doping concentration of the substrate may be reduced, and the drain-induced barrier lowering (DIBL) may be improved.

On the other hand, as a method for extending the channel region, a fin gate structure has been proposed as a gate having a three-dimensional channel.

The protruding gate etches the device isolation region to protrude the active region to form a fin pattern, thereby exposing both side and top surfaces of the active region, and then forming the gate line to surround the protruding active region (pin pattern). In this case, the short channel effect due to the increased DBL (Drain Induced Barrier Lowing) is suppressed, and the channel is formed on all three exposed surfaces of the active region, thereby driving the current through the channel. Drive characteristics are improved.

However, as the trend toward higher integration of semiconductor devices has increased, there are limitations in solving the short channel effect and the high channel doping concentration of the substrate even when the bulb type recess gate and the protruding gate structures are applied. For this reason, current control at low threshold voltage is not easy.

Accordingly, the present invention provides a semiconductor device and a method of manufacturing the same, which facilitate the control of current even at a low threshold voltage, thereby improving accuracy and density of current flow control in a DRAM device.

In an embodiment, a semiconductor device may include a semiconductor substrate having grooves formed in a gate formation region; A first gate insulating film formed on the bottom surface of the groove; A channel layer formed on the first gate insulating layer; A second gate insulating film formed on each of the top and bottom surfaces of the channel layer; And a gate conductive layer including the second gate insulating layer to surround the channel layer.

Here, the channel layer is made of a silicon epi layer.

The gate conductive film is made of a polysilicon film or a tungsten film.

In another embodiment, a method of manufacturing a semiconductor device may include: recessing the active region of a semiconductor substrate having an active region and an isolation region, wherein a trench for forming an isolation layer is formed in the isolation region; Forming an insulating film so as not to completely fill the recessed substrate portion in the recessed substrate portion; Growing a silicon epi layer to cover an insulating film from sidewalls of the recessed substrate portion; Removing the insulating film; Forming a gate insulating film on a surface of the silicon epitaxial layer and a bottom surface of the recessed substrate portion; And forming a gate conductive film to completely fill the recessed substrate portion on the gate insulating film.

Here, the step of recessing the active region of the semiconductor substrate is performed such that the active region of the substrate is recessed to a depth smaller than that of the trench for device isolation film.

The insulating film is formed of an oxide film or a nitride film.

Forming an insulating film so as not to completely fill the recessed substrate portion, the method comprising: embedding an insulating film in the recessed substrate portion; And dry etching or wet etching the insulating film to remove a portion of the thickness of the upper portion of the insulating film.

The removing of the insulating layer is performed by a wet etching method.

The gate conductive film is formed of a polysilicon film or a tungsten film.

After the forming of the gate conductive film, forming a device isolation film in the trench for device isolation film; further comprises.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, a gate is formed by recessing a semiconductor substrate active region and growing a silicon epitaxial layer from the recessed substrate portion, and then forming a gate insulating film and a gate conductive film on the surface of the silicon epitaxial layer in order.

In this case, the gate electrode is formed to surround the silicon epitaxial layer so that the silicon epitaxial layer acts as a channel layer, thereby increasing the channel region, thereby effectively controlling current even at a low threshold voltage.

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device according to an exemplary embodiment may include a semiconductor substrate 100 having a groove formed in a gate formation region, a first gate insulating layer 121 formed on a bottom surface of the groove, and the first gate. The channel layer 120 including the channel layer 120 formed on the insulating layer 121, the second gate insulating layer 122 and the second gate insulating layer 122 formed on the top and bottom surfaces of the channel layer 120, respectively. It includes a gate conductive film 124 formed to surround the.

The channel layer 120 is formed of a silicon epitaxial layer, and the gate conductive layer 124 is made of a polysilicon film or a tungsten film.

Here, the present invention forms a channel layer 120 by growing a silicon epitaxial layer in a recessed groove of the active region of the semiconductor substrate 100, and surrounds the channel layer 120 with a gate insulating film 122 and a gate. By depositing the conductive layer 124 to form the gate 130, the channel region of the gate 130 may be increased, thereby improving accuracy and density of current flow control in a DRAM device. have.

2A through 2F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to another embodiment of the present invention.

Referring to FIG. 2A, the device isolation region of the semiconductor substrate 200 having the active region and the device isolation region is etched to form a trench T for the isolation layer, and recesses the active region of the substrate 200. do. In this case, the active region of the substrate 200 is recessed to a depth smaller than that of the trench T for device isolation layers.

Referring to FIG. 2B, the recessed portion of the active region of the substrate 200 is filled with a polysilica zane (PSZ) film and other oxide films or a nitride film-based insulating film 212. Subsequently, the insulating film 212 may be dry or wet etched to remove a portion of the thickness of the upper portion of the insulating film 212 so that the recessed portion of the substrate 200 may not be completely embedded in the recessed substrate 200. And form 212.

Referring to FIG. 2C, a doped silicon epitaxial layer 220 is grown from sidewalls of a portion of the recessed substrate 200 so that silicon epitaxial layers 220 grown on both sides are connected to each other to form the recessed substrate ( It is formed to cover the insulating film 212 formed in the portion 200. In this case, since the insulating layer 212 is formed at the bottom of the recessed substrate 200, the silicon epitaxial layer 220 does not contact the bottom of the recessed substrate 200.

Referring to FIG. 2D, a wet etching process is performed on the resultant of the substrate 200 on which the silicon epitaxial layer 220 is grown to remove an insulating layer under the silicon epitaxial layer 220.

Referring to FIG. 2E, the gate insulating layer 222 is formed on the surface of the silicon epitaxial layer 220 and the bottom surface of the recessed substrate 200 through a thermal oxidation process. Here, since the entire surface of the silicon epitaxial layer 220 is exposed by removing the insulating layer, the gate insulating layer 222 is formed to surround the silicon epitaxial layer 220.

Referring to FIG. 2F, a gate conductive layer 224 is formed on the gate insulating layer 222 to completely fill the recessed substrate 200. The gate conductive layer 224 may be formed in the recessed portion of the active region of the substrate 200. The gate 230 is formed. The gate conductive layer 224 is formed of a conductive material such as a polysilicon layer or a tungsten layer.

Subsequently, although not shown, an isolation layer is formed in the trench for isolation of the semiconductor substrate.

Herein, the present invention grows a silicon epitaxial layer on a recessed portion of a semiconductor substrate active region, and then forms a gate by depositing a gate insulating film and a gate conductive film to surround the silicon epitaxial layer, so that the gate electrode surrounds the entire channel. It can be formed so that.

Accordingly, the present invention can increase the channel region by the silicon epilayer acting as a channel layer when forming a recess gate, and can also easily control the current even at a low threshold voltage, thereby allowing DRAM The accuracy and density of the current flow control in the device can be improved.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention can increase the channel region by recessing the semiconductor substrate and then growing a silicon epitaxial layer serving as a channel layer and forming a gate to surround the silicon epitaxial layer.

Therefore, the present invention can facilitate the control of current even with a low threshold voltage, thereby improving the accuracy and density of current flow control in DRAM devices.

Claims (10)

A semiconductor substrate having grooves formed in the gate formation region; A first gate insulating film formed on the bottom surface of the groove; A channel layer formed on the first gate insulating layer; A second gate insulating film formed on each of the top and bottom surfaces of the channel layer; And A gate conductive layer including the second gate insulating layer to surround the channel layer; A semiconductor device comprising a. The method of claim 1, The channel layer is a semiconductor device, characterized in that consisting of a silicon epi layer. The method of claim 1, The gate conductive film is a semiconductor device, characterized in that made of a polysilicon film, or a tungsten film. Recessing the active region of the semiconductor substrate having an active region and an isolation region, wherein a trench for forming an isolation layer is formed in the isolation region; Forming an insulating film in the recessed substrate portion so as not to completely fill the recessed substrate portion; Growing a silicon epi layer to cover an insulating film from sidewalls of the recessed substrate portion; Removing the insulating film; Forming a gate insulating film on a surface of the silicon epitaxial layer and a bottom surface of the recessed substrate portion; And Forming a gate conductive film to completely fill the recessed substrate portion on the gate insulating film; Method of manufacturing a semiconductor device comprising a. The method of claim 4, wherein Recessing the active region of the semiconductor substrate, And recessing the active region of the substrate to a shallower depth than the trench for device isolation. The method of claim 4, wherein And the insulating film is formed of an oxide film or a nitride film. The method of claim 4, wherein Forming an insulating film so as not to completely fill the recessed substrate portion, Embedding an insulating film in the recessed substrate portion; And Dry etching or wet etching the insulating film to remove a portion of the thickness of the insulating film; Method of manufacturing a semiconductor device comprising a. The method of claim 4, wherein The removing of the insulating layer may be performed by a wet etching method. The method of claim 4, wherein The gate conductive film is a method of manufacturing a semiconductor device, characterized in that formed of a polysilicon film or a tungsten film. The method of claim 4, wherein And forming a device isolation film in the trench for device isolation film after the forming of the gate conductive film.
KR1020060137255A 2006-12-28 2006-12-28 Semiconductor device and method of manufacturing the same KR20080062009A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020060137255A KR20080062009A (en) 2006-12-28 2006-12-28 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060137255A KR20080062009A (en) 2006-12-28 2006-12-28 Semiconductor device and method of manufacturing the same

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KR20080062009A true KR20080062009A (en) 2008-07-03

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