KR20080060651A - Liquid crystal display device - Google Patents

Abstract

An LCD(Liquid Crystal Display) device is provided to reduce power consumption by transmitting one of odd and even numbered data from a channel recovery unit to a liquid crystal module through two channels. An LCD(Liquid Crystal Display) device includes first and second input units, an LVDS(Low Voltage Differential Signal) transmission module(108), and a controller(106). The first and second input units receive first and second data, respectively. The LVDS transmission module converts the first and second data from the first and second input units into low voltage differential signals and transmits the converted low voltage differential signals. The controller controls a transmission mode of the LVDS transmission module according to identification between the first and second data from the first and second input units.

Description

Liquid crystal display device

1 is a view showing a liquid crystal display device according to the present invention.

2 is a view illustrating in detail the transmission mode control unit of FIG.

3 is a view illustrating in detail the channel recovery unit of FIG.

<Brief description of the main parts of the drawing>

100: drive system 102a, 120: first buffer portion

102b and 122: second buffer section 104a: first delay section

104b: second delay unit 106: transmission mode control unit

108: LVDS Receive Module 110: LVDS Receive Module

112: channel recovery unit 114: liquid crystal display module

116: comparison unit 118: shift register

124: selection section 126: third buffer section

128: fourth buffer unit

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of reducing power consumption.

The liquid crystal display is controlled by a liquid crystal panel composed of a plurality of pixels arranged in a matrix and a plurality of thin film transistors for switching data signals to be supplied to each of the pixels. An image is displayed.

The liquid crystal display device is connected to a system, for example, a computer main body and a connector, and receives a predetermined image signal (R, G, B), a clock signal, a synchronization signal, a power signal, etc. output from the computer main body. Display information.

Due to this, recently, a low voltage differential signal (LVDS) transmitter which digitizes and compresses an image signal, a clock signal, and a synchronization signal and lowers the voltage below 1 V is incorporated in the computer main body, and is transmitted as a low voltage differential signal to the liquid crystal display device. The printed circuit board of the liquid crystal display device has an LVDS receiver for restoring the transmitted low voltage differential signal to its original state, thereby suppressing the emission of electromagnetic waves and noise.

The LVDS transmitter transmits the image signal, the clock signal, and the synchronization signal to the LVDS receiver. The LVDS transmitter has one channel between the LVDS transmitter and the LVDS receiver to speed up data processing.

Recently, as the number of bits of the image signal increases, two or more channels are provided between the LVDS transmitter and the LVDS receiver to process a large amount of data at once to process a large amount of data. When the odd and even data are processed in each of the two channels, the processing speed of the data is increased compared to processing the data using one channel.

When data is processed using two channels, the driving frequency of the data is increased, resulting in an increase in power consumption. Therefore, there is an urgent need for research on liquid crystal displays that can reduce power consumption while increasing data processing speed.

An object of the present invention is to provide a liquid crystal display device capable of reducing power consumption.

According to an embodiment of the present invention, a liquid crystal display device includes: a first input unit into which first data is input; a second input unit into which second data is input; and first data from the first input unit. And a transmission mode of the LVDS transmission module for transmitting the second data from the second input unit and converting the second data into a low voltage differential signal and whether the first and second data from the first and second input units are identical. It characterized in that it comprises a transmission mode control unit for controlling the.

According to a second exemplary embodiment of the present invention, there is provided a liquid crystal display (LVDS) transmitting module for transmitting first and second data transmitted through first and second channels and converting the first and second data into low voltage differential signals. An LVDS receiving module converting the first and second data transmitted from the LVDS transmitting module into original data and outputting a signal of 1 bit according to whether the first and second data are the same or 1 output from the LVDS receiving module. And a channel restoring unit for restoring the channels of the first and second data from the LVDS receiving module according to the presence or absence of a bit signal.

According to a third exemplary embodiment of the present invention, a liquid crystal display device includes a first input unit to which first data is input, a second input unit to which second data is input, and first data from the first input unit. And an LVDS transmitting module for transmitting second data from the second input unit and converting the second data into a low voltage differential signal, and transmitting the LVDS transmitting module according to whether the first and second data from the first and second input units are identical. A transmission mode control unit controlling a mode, and an LVDS reception unit converting first and second data transmitted from the LVDS transmission module into original data and outputting a signal of 1 bit according to whether the first and second data are the same; And a channel recovery unit for restoring channels of the first and second data from the LVDS receiving module according to the presence or absence of a 1-bit signal output from the LVDS receiving module. It is characterized by.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention.

1 is a view showing a liquid crystal display device according to the present invention.

As shown in FIG. 1, a liquid crystal display device according to the present invention includes a liquid crystal display module including a driving system 100 such as a personal computer (not shown), a liquid crystal panel on which an image is displayed, and a driving unit for driving the liquid crystal panel. And an LVDS transmission module 108 which is an interface unit for supplying the first and second data Data1 and Data2 and the clock signal CLK supplied from the driving system 100 to the liquid crystal display module 114. LVDS receiving module 110.

In addition, the liquid crystal display according to the present invention is located between the driving system 100 and the LVDS transmission module 108 and the transmission mode control unit 106 for controlling the transmission mode of the LVDS transmission module 108, and A channel restoring unit 112 positioned between the LVDS receiving module 110 and the liquid crystal display module 114 and restoring channels of the first and second data Data1 and Data2 supplied from the LVDS receiving module 110; It further includes.

In this case, two channels exist between the driving system 100 and the LVDS transmitting module 108, and the two channels exist between the LVDS transmitting module 108 and the LVDS receiving module 110. The two channels are also present between the LVDS receiving module 110 and the liquid crystal display module 114. The first and second data Data1 and Data2 are transmitted to the first and second channels, respectively. For example, the first data Data1 may be odd data and the second data Data2 may be even data.

The liquid crystal display module 114 includes a first substrate in which a plurality of gate lines and data lines are arranged to define a plurality of pixel regions, and a color corresponding to the pixel regions of the first substrate and having red, green, and blue colors. A liquid crystal panel comprising a second substrate having a filter and a liquid crystal layer formed between the first and second substrates, a gate driver driving a gate line of the liquid crystal panel, a data driver and a gate driving the data line; It consists of a timing controller that controls the data driver.

The driving system 100 uses odd or even data (Data1, Data2), clock signal (CLK), synchronization signal, and data enable (DE) by using a video chip (or a video controller, a CPU, etc.) not shown. ) Generates a signal. The odd-numbered data Data1 is supplied to the first channel of two channels, and the even-numbered data Data2 is supplied to the other second channel.

The LVDS transmitting module 108 transmits the odd and even data (Data1, Data2) and the clock signal CLK from the driving system 100 to the liquid crystal display module 114. The LVDS transmission module 108 digitizes and compresses the odd and even data (Data1, Data2) and the clock signal CLK, and lowers the voltage to a low voltage differential signal of 1 V or less to the liquid crystal display module 114. send.

Specifically, the LVDS transmitting module 108 controls the channel of odd and even data (Data1, Data2) supplied from the driving system 100 by the channel mode selection control signal generated by the transmission mode control unit 106. Choose.

At this time, the odd and even data (Data1, Data2) generated by the driving system 100 are located between the first and second buffer units 102a positioned between the driving system 100 and the LVDS transmission module 108. 102b) through the first and second channels, respectively. The first and second buffer units 102a and 102b serve to stabilize the odd and even data (Data1, Data2) supplied from the driving system 100. Radix and even data (Data1, Data2) transmitted to the first and second buffer units 102a and 102b are disposed between the first and second buffer units 102a and 120b and the LVDS transmission module 108. The first and second delay units 104a and 104b are located, respectively.

The odd and even data (Data1, Data2) from the first and second buffer units 102a, 102b are also transmitted to the transfer mode control unit 106. In this case, a clock signal CLK is supplied to the first and second buffer units 102a and 120b, the first and second delay units 104a and 104b, and the transmission mode control unit 106 to synchronize with each other. do.

The first and second delay units 104a and 104b transmit the odd and even data (Data1, 1) transmitted from the first and second buffer units 102a and 120b to synchronize with the transmission mode control unit 106. Data2) delays. The first and second delay units 104a and 104b delay the radix and even-numbered data Data1 and Data2 transmitted from the first and second buffer units 102a and 102b, respectively, for a predetermined time to transmit the LVDS. Send to module 108. In addition, the transmission mode control unit 106 generates a channel mode selection control signal using the odd and even data (Data1, Data2) transmitted from the first and second buffer units 102a and 102b to transmit the LVDS. Supply to module 108. A detailed description of the transmission mode control unit 106 will be described later with reference to FIG. 2.

The LVDS receiving module 110 receives the odd and even data (Data1, Data2) and the channel mode selection control signal transmitted from the LVDS transmitting module 108 according to the channel mode selected by the LVDS transmitting module 108. The odd and even data (Data1, Data2) is converted into the original data, and the converted odd and even data (Data1, Data2) are transmitted to the channel recovery unit 112. In addition, the LVDS receiving module 110 transmits the channel mode selection control signal to the channel recovery unit 112.

The channel recovery unit 112 restores the channel on which the odd and even data (Data1, Data2) are transmitted according to the channel mode selection control signal. The liquid crystal display module 114 displays an image by the data transmitted from the channel recovery unit 112 to the restored channel. Detailed description of the channel recovery unit 112 will be described later with reference to FIG. 3.

2 is a diagram illustrating the transmission mode control unit of FIG. 1 in detail.

As shown in Figs. 1 and 2, the transmission mode control unit 106 compares the radix and even-numbered data Data1 and Data2 supplied from the first and second delay units 102a and 102b, respectively. Comparing unit 116 for generating a comparison signal according to the comparison result, and the comparison signal supplied from the comparison unit 116 of the clock signal CLK generated in the driving system (100 of FIG. 1) shown in FIG. And a shift register 118 which sequentially collects the comparison signals in synchronization with each other.

The comparison unit 116 compares a signal of a first logic (eg, high) when the odd and even data (Data1, Data2) supplied from the first and second delay units 102a and 102b are the same. If the odd and even data (Data1, Data2) supplied from the first and second delay unit (102a, 102b) is different, generates a comparison signal of the second logic (for example, row) The generated comparison signal of the first and second logic is supplied to the shift register 118.

The shift register 118 of the first logic (for example, high) when the comparison signal of the first logic is supplied from the comparison unit 116 by the number of bits of the odd and even data (Data1, Data2) A channel mode selection control signal is generated and the channel mode selection control signal of the first logic is transmitted to the LVDS receiving module 110 shown in FIG. 1. The shift register 118 generates a channel mode selection control signal of the second logic (for example, a row) when the comparison signal of the second logic is supplied from the comparator 116 to generate the LVDS receiving module 110. ) Supplies the channel mode selection control signal of the second logic.

The LVDS transmitting module (108 of FIG. 1) shown in FIG. 1 receives the first and second odd-numbered data in which the odd and even data are transmitted when the channel mode selection control signal of the first logic is supplied from the transmission mode control unit 106. One of the channels is selected to transmit data transmitted from the selected channel to the LVDS receiving module (110 of FIG. 1).

For example, when the channel mode selection control signal of the first logic is supplied from the transmission mode control unit 106, the LVDS transmission module 108 selects the first channel through which the odd data is transmitted and selects the odd data. The LVDS receiving module 110 transmits the data. The LVDS transmitting module 108 transmits the channel mode selection control signal of the first logic to the LVDS receiving module 110 similarly to the selected odd-numbered data. In addition, when the channel mode selection control signal of the first logic is supplied to the LVDS transmission module 108, the LVDS transmission module 108 transmits a signal of 1 bit to the second channel through which even-numbered data is transmitted. The LVDS receiving module 110 transmits this.

The LVDS receiving module 110 converts the odd data transmitted from the LVDS transmitting module 108 into original data to convert the converted odd data and the channel mode selection control signal of the first logic into the channel restoring unit. Send to 112. In addition, the LVDS receiving module 110 transmits a 1-bit signal transmitted to the second channel of the LVDS transmitting module 108 to the channel recovery unit 112.

On the contrary, when the channel mode selection control signal of the second logic is supplied from the transmission mode control unit 106, the LVDS transmission module 108 selects the first and second channels through which odd and even data are transmitted and Odd and even data transmitted on the first and second channels are transmitted to the LVDS receiving module 110. The LVDS transmitting module 108 transmits the channel mode selection control signal of the second logic to the LVDS receiving module 110. The odd and even data transmitted to the LVDS receiving module 110 are converted into original data, and the converted odd and even data and the channel mode selection control signal of the second logic are transmitted to the channel recovery unit 112. Is sent.

As a result, since the LVDS receiving module 110 selectively transmits data to the channel recovery unit 112 according to whether the odd and even data are the same, the odd and even data are irrelevant. Compared with the conventional liquid crystal display device which transmits all the first data, power consumption can be reduced.

3 is a view illustrating in detail the channel recovery unit of FIG. 1.

As shown in FIGS. 1 and 3, the channel recovery unit 112 may include a first buffer unit 120 for stabilizing the odd data Data1 and a second buffer unit for stabilizing the even-numbered data Data2. A selection unit 124 for selecting whether to restore the odd or even-numbered data Data1 or Data2 according to the channel mode selection control signal generated by the buffer unit 122 and the transmission mode control unit 106 of FIG. And a third buffer unit 126 for stabilizing the radix-th data Data1 output from the selector 124 and a fourth buffer unit for stabilizing even-numbered data Data2 output from the selector 124. (128).

As described above, when the channel mode selection control signal of the first logic, the odd-numbered data Data1 and one bit of data are supplied from the LVDS receiving module 110 (in FIG. 1), the odd-numbered data Data1 is obtained. It is supplied to the first buffer unit 120 and stabilized. The one bit of data is supplied to the second buffer unit 122. The second buffer unit 122 does not output any signal when the one-bit data is supplied. The odd-numbered data Data1 stabilized in the first buffer unit 120 is output to the selection unit 124.

When the channel mode selection control signal of the first logic is supplied, the selector 124 may output the odd-numbered data Data1 output from the first buffer unit 120 to the third and fourth buffer units 126,. 128). The odd-numbered data Data1 supplied to the third and fourth buffer units 126 and 128 are stabilized in the third and fourth buffer units 126 and 128, respectively. The odd-numbered data Data1 stabilized in the third buffer unit 126 is transmitted to the liquid crystal display module 114 through the first channel connected to the third buffer unit 126, and the fourth buffer unit The odd-numbered data Data1 stabilized at 128 is also transmitted to the liquid crystal display module 114 through the second channel connected to the fourth buffer unit 128. The channel recovery unit 112 restores the radix data transmitted through the first channel of the LVDS receiving module 110 to the second channel and restores the radix data through the first and second channels. 114).

As a result, when the odd and even data are the same, the LVDS receiving module 110 selects any one of the odd and even data so that the selected data selects two channels from the channel recovery unit 112. The power consumption can be reduced by transmitting the power to the liquid crystal display module 114 through the LCD.

On the contrary, when the channel mode selection control signal of the second logic and the odd and even data (Data1, Data2) are supplied from the LVDS receiving module 110, the odd data (Data1) is stored in the first buffer unit 120. ) And the even-numbered data Data2 are supplied to the second buffer unit 122 and stabilized, respectively.

The odd-numbered data Data1 stabilized in the first buffer unit 120 and the even-numbered data Data2 stabilized in the second buffer unit 122 are supplied to the selection unit 124. The channel mode selection control signal of the second logic is also supplied to the selection unit 124. When the channel mode selection control signal of the second logic is supplied, the selector 124 transmits the odd-numbered data Data1 supplied from the first buffer unit 120 to the third buffer unit 126. The even-numbered data Data2 supplied from the second buffer unit 122 is transmitted to the fourth buffer unit 128.

The odd and even data (Data1, Data2) transmitted to the third and fourth buffer units 126 and 128 are stabilized and supplied to the liquid crystal display module 114 through the first and second channels, respectively. When the odd and even data (Data1, Data2) is different from each other, the LVDS receiving module 110 transmits the odd and even data to the channel recovery unit 112 through the first and second channels.

Since the liquid crystal display according to the present invention selectively transmits data according to whether the odd and even data is supplied from the system, the liquid crystal display device transmits both the odd and even data regardless of whether the odd and even data are the same. Compared with the conventional liquid crystal display, power consumption can be reduced.

As described above, since the liquid crystal display according to the present invention selectively transmits data according to whether the odd and even data is supplied from the system, the odd and even data are irrelevant regardless of whether the odd and even data are the same. Compared with the conventional liquid crystal display device which transmits all the first data, power consumption can be reduced.

Although the present invention has been described with reference to the embodiments, those skilled in the art may variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. You will understand.

Claims (9)

A first input unit to which first data is input and a second input unit to which second data is input; An LVDS transmitting module for transmitting the first data from the first input unit and the second data from the second input unit and converting the second data into a low voltage differential signal; And And a transmission mode control unit controlling a transmission mode of the LVDS transmission module according to whether the first and second data from the first and second input units are identical. The method of claim 1, The transmission mode control unit, A comparator for comparing the odd and even data and generating a comparison signal according to the comparison result; And And a shift register which collects the comparison signal corresponding to the bit number of the odd and even data and generates a control signal according to the result. The method of claim 1, And a buffer unit positioned between the first and second input units and the LVDS transmitting module to stabilize the first and second data from the first and second input units. The method of claim 3, wherein And a delay unit positioned between the buffer unit and the LVDS transmitting module and delaying first and second data transmitted from the buffer unit to adjust timing. An LVDS transmitting module for transmitting the first and second data transmitted through the first and second channels, respectively, and converting the first and second data into low voltage differential signals; An LVDS receiving module converting the first and second data transmitted from the LVDS transmitting module into original data and outputting a signal of 1 bit according to whether the first and second data are the same; And And a channel recovery unit for restoring channels of the first and second data from the LVDS receiving module according to the presence or absence of a 1-bit signal output from the LVDS receiving module. A first input unit to which first data is input and a second input unit to which second data is input; An LVDS transmitting module configured to transmit first data from the first input unit and second data from the second input unit to convert a low voltage differential signal; A transmission mode control unit controlling a transmission mode of the LVDS transmission module according to whether the first and second data from the first and second input units are identical; An LVDS receiving module converting the first and second data transmitted from the LVDS transmitting module into original data and outputting a signal of 1 bit according to whether the first and second data are the same; And And a channel recovery unit for restoring channels of the first and second data from the LVDS receiving module according to the presence or absence of a 1-bit signal output from the LVDS receiving module. The method of claim 6, The transmission mode control unit, A comparator for comparing the odd and even data and generating a comparison signal according to the comparison result; And And a shift register which collects the comparison signal corresponding to the bit number of the odd and even data and generates a control signal according to the result. The method of claim 6, And a buffer unit positioned between the first and second input units and the LVDS transmitting module to stabilize the first and second data from the first and second input units. The method of claim 8, And a delay unit positioned between the buffer unit and the LVDS transmitting module and delaying first and second data transmitted from the buffer unit to adjust timing.

Images