KR20080060018A - Composition for wet-etching process of semicondutor device and method for forming metal-line including wet-etching process using the same - Google Patents

Abstract

A composition for wet etching of a semiconductor device is provided to uniformly etching an interlayer dielectric without generating a difference in height during wet etching for forming metal interconnections, thereby improving the yield and quality of a semiconductor device. A composition for wet etching of a semiconductor device is based on an aqueous acid solution, and further comprises a surfactant represented by the following formula 1 as an additive. In formula 1, R is H, a C8-C20 alkyl or alkylaryl group; m is an integer of 5-50; and n is an integer of 3-50. The aqueous acid solution comprises at least one acid selected from the group consisting of sulfuric acid, nitric acid, phosphoric acid, hydrofluoric acid, acetic acid and a combination thereof.

Description

Composition for Wet-Etching Process of Semicondutor Device and Method for Forming Metal-line Including Wet-Etching Process Using the Same}

1 is a SEM photograph of a metal wiring after the wet etching process according to Example 5 of the present invention.

FIG. 2 is a SEM photograph of the metal wiring after the wet etching process according to Example 6 of the present invention.

The present invention relates to a wet etching composition of a semiconductor device and a method for forming a metal wiring comprising a wet etching process step using the same.

As the field of application of semiconductor devices expands, various studies have been made to manufacture semiconductor devices having increased integration and faster operation speeds.

However, as the integration of semiconductor devices proceeds, the width and contact area of the metal wirings decrease, thereby increasing the resistance of the metal wirings including the contact resistance. In addition, as the gap between the metal wiring and the contact plug becomes narrower, parasitic capacitance due to the interlayer insulating film that insulates the metal wiring increases.

Accordingly, various process technologies have been researched and applied to implement a highly integrated semiconductor device having a high operating speed by lowering resistance of metal wiring and lowering parasitic capacitance. As part of this, an attempt is made to use a high dielectric metal material having a higher electrical conductivity as the metal wiring material, while using a low dielectric film having excellent buried characteristics and a low dielectric constant as the interlayer insulating film material between the metal wirings. have.

In general, as a material for metal wiring, copper (Cu), which has excellent electrical conductivity instead of aluminum (Al), is easy to deposit and etch, and has a high dielectric constant, is currently known as the most suitable material.

On the other hand, since the resistance increases as the design rule of the semiconductor device decreases, an oxide film (SiO ₂ ) as an insulating material for reducing parasitic capacitance between adjacent metal wires in order to reduce the RC delay or power consumption, thereby improving the operation speed. And low dielectric films with dielectric constants (k) of about 3 or less, such as SQ (Spin on Dielectric) materials of the HSQ (Hydrogen Silesquioxane) series.

More specifically, in the manufacturing process of a semiconductor device including a conventional metallization forming process, first, a wafer on which a lower structure such as a lower metal interconnection is formed is prepared, and then an oxide film and a low layer as an insulating film covering the lower structure on the wafer. A laminated film of a dielectric film is formed, and a contact hole for exposing a lower structure is formed through an etching process for the insulating film. Next, a metal film filling the contact hole is deposited to form a metal wiring.

At this time, the etching process for the insulating film is a dry etching process or a wet etching process is performed. However, since the etching thickness is uneven during the dry etching process for the insulating layer, a bowing phenomenon occurs in which the contact hole inlet formed after the completion of the etching process becomes like a jar, and thus, the step coverage property when the contact hole is buried. (step coverage) is bad, so the landfill characteristics are not good.

Thus, in the mass production process, a wet etching process using an acid aqueous solution is applied. However, since the wet etching rates of the oxide film and the low dielectric film with respect to the acid aqueous solution have a large difference of 1: 1.4, the etching is not performed at the same time, thereby causing a topology between the materials. Therefore, subsequent processes cannot be stably performed.

The present invention has been made in order to improve the above problems, and an object of the present invention is to provide a wet etching composition further comprising a surfactant as an additive while containing an acid (acid) aqueous solution as a main component.

In addition, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device comprising a cleaning process step using the wet etching composition.

In order to achieve the above object, the present invention provides a composition for wet etching, further comprising a surfactant represented by the following formula (1) as an acid aqueous solution as a main component.

[Formula 1]

Where

R is H, an alkyl group or an alkylaryl group of C ₈ -C ₂₀ ,

m is an integer selected from 5 to 50,

n is an integer selected from 3-50.

The acid aqueous solution may include at least one acid selected from the group consisting of sulfuric acid (H ₂ SO ₄ ), nitric acid (HNO ₃ ), phosphoric acid (H ₃ PO ₄ ), hydrofluoric acid (HF), acetic acid (CH ₃ COOH), and combinations thereof. It contains 1 to 40wt% of the total mass of the aqueous acid solution. At this time, in the case of the hydrofluoric acid, the concentration may be adjusted with a buffer solution such as aqueous ammonia solution (NH ₄ OH).

In addition, in the compound of Formula 1, R is preferably hydrogen, butylbenzyl, octyl, octyl phenyl, nonyl, nonyl phenyl, nonyl phenyl, decyl, decyl phenyl (decyl phenyl), undecyl (undecyl), undecyl phenyl (undecyl phenyl), dodecyl (dodecyl) or dodecyl phenyl (dodecyl phenyl), and the like, and more specifically in Korean Patent Registration Publication No. 10-576477 And compounds of the formulas 1a and 1b as disclosed.

[Formula 1a]

[Formula 1b]

Wherein m is an integer selected from 5 to 50.

In the wet etching composition, the content of the compound of Formula 1, which is a surfactant, is 50 to 10,000 ppm, preferably 50 to 1,000 ppm, and more preferably 300 to 700 ppm with respect to the total wet etching composition.

If the compound of Formula 1 is included in 50ppm or less, the effect of improving the etching selectivity is insignificant, and in the case where the compound of Formula 1 is included in 10,000ppm or more, a lot of bubbles are generated on the substrate after the etching process.

Moreover, in this invention, the said composition is filtered with a 0.2 micrometer filter, and a washing | cleaning liquid composition is manufactured.

The present invention also provides a method for forming a metal wiring of a semiconductor device comprising a wet etching process using the wet etching composition:

Providing a semiconductor wafer having a lower metal wiring structure formed thereon;

Forming an oxide film on the wafer;

Forming a first low dielectric film having a lower dielectric constant than the oxide film on the oxide film; And

And performing a wet etching process on the insulating film formed of the laminated film of the oxide film and the first low dielectric film to form a contact hole in which the lower metal wiring is exposed.

The method may further include forming second and third low dielectric layers on the first low dielectric layer, the second and third low dielectric layers having a lower dielectric constant than the first low dielectric layer.

The method may further include forming a multilayer metal wiring by filling a metal film after forming the contact hole.

In this case, the oxide film is formed to a thickness of 20 to 80% of the total thickness of the insulating film.

The first low dielectric film is formed to a thickness of 20 to 80% of the total thickness of the insulating film using an HSQ or MSQ film.

In addition, the wet etching process is performed by immersing the wafer in the wet etching composition at room temperature for 300 to 500 seconds.

As described above, the present invention provides a wet etching composition including a surfactant as an additive instead of an aqueous acid solution used in a wet etching process for a laminated film of a conventional oxide film and a low dielectric film, and by performing a wet etching process step using the same, The oxide film used as the insulating film and the HSQ film, which is a low dielectric film, can be etched at the same speed of 1: 1, so that the generation of step difference between materials can be prevented.

Further, in the present invention, in using the wet etching composition, an insulating film having a laminated structure in which a low dielectric film having a relatively high dielectric constant is formed at a lower portion thereof and a low dielectric film having a relatively low dielectric constant is formed as a multilayer as the upper portion thereof is raised. By using it, the hardness of an insulating film can be made high compared with the case of using the low dielectric film of the conventional single layer structure.

In addition, the present invention provides a semiconductor device manufactured using the metallization forming method comprising the wet cleaning process step.

Hereinafter, the present invention will be described in detail by examples. However, the examples are only to illustrate the invention and the present invention is not limited by the following examples.

Example 1 Preparation of Wet Etching Composition of the Present Invention (1)

To 10 L of an aqueous acid solution prepared by mixing NHF ₄ F (35 wt%), HF (0.5 wt%) and H ₃ PO ₄ (1 Wt%), surfactant (5 g) (500 ppm) of Formula 1a was added at room temperature. Thereafter, the obtained mixed solution was filtered with a 0.2 μm PTFF filter to obtain a wet etching composition of the present invention.

Example 2. Preparation of Wet Etch Composition of the Present Invention (2)

To 10 L of an aqueous solution prepared by mixing NHF ₄ F (35 wt%), HF (0.5 wt%) and H ₃ PO ₄ (1 Wt%), the surfactant (5 g) (500 ppm) of Formula 1b was added at room temperature. Thereafter, the obtained mixed solution was filtered with a 0.2 μm PTFF filter to obtain a wet etching composition of the present invention.

Experimental Example 1. Measurement of the surface tension of the wet etching composition of the present invention

The circular ring of platinum and iridium was immersed in the wet etching composition of Example 1, and the surface tension between the liquid surface and the ring was measured while gradually raising. The device used was K9 (manufactured by Kruss, Germany). The surface tension of the composition of Example 1 was 26.2 dyne s / cm ² .

Experimental Example 2. Measurement of the surface tension of the wet etching composition of the present invention

The circular ring of platinum and iridium was immersed in the wet etching composition of Example 2, and the surface tension between the liquid surface and the ring was measured while gradually raising. The device used at this time used K9. The surface tension of the composition of Example 2 was 22.3 dyne s / cm ² .

Example 3 Comparison of Etch Selectivity Differences between Oxide and HSQ Films

The first specimen coated with an oxide film having a thickness of 15000Å and the second specimen coated with an HSQ film having a thickness of 1000Å were respectively immersed in the wet etching composition of Example 1 for 360 seconds at room temperature, washed with distilled water, and removed from the initial thickness. The thickness of each film was measured and shown in Table 1 below. As can be seen in Table 2, the etching rate of the oxide film: HSQ film in the wet etching composition of the present invention can be seen that almost 1: 1 similar.

TABLE 1

Initial thickness (Å) Thickness after removal (Å)  Removal rate Oxide film 15000 8600 600 Å / sec HSQ 10000 4570 905 Å / sec

Example 4 Comparison of etching selectivity difference between oxide film and HSQ film

The first specimen coated with an oxide film having a thickness of 15000 kPa and the second specimen coated with an HSQ film having a thickness of 15000 kPa were immersed in the wet etching composition of Example 2 for 360 seconds at room temperature, and then washed with distilled water and removed from the initial thickness. The thickness of each film was measured and shown in Table 2 below. As can be seen in Table 2, the etching rate of the oxide film: HSQ film in the wet etching composition of the present invention can be seen that almost 1: 1 similar.

TABLE 2

Initial thickness (Å) Thickness after removal (Å)  Removal rate Oxide film 15000 9930 845 Å / sec HSQ 10000 4960 840 Å / sec

Comparative Example 1. Comparison of etching selectivity difference between oxide film and HSQ film

The first specimen coated with an oxide film having a thickness of 15000 kPa and the second specimen coated with an HSQ film having a thickness of 10000 kPa were immersed in an aqueous solution of HF (0.5 wt%) / NH ₄ F (46 wt%) for 360 seconds at room temperature, followed by distilled water. The thickness of each membrane washed and removed at the initial thickness is measured and shown in Table 3 below. As can be seen in Table 3 below, the etching rate of the oxide film: HSQ film is 1: 1.4, and the rate of the HSQ film is higher.

TABLE 3

Initial thickness (Å) Thickness after removal (Å)  Removal rate Oxide film 15000 9420 930 Å / sec HSQ 10000 6016 664 Å / sec

Example 5.

The wafer with a metal wiring coated with an oxide film of 100 Å on the top was immersed in the composition of Example 1 for 400 seconds, and then washed with distilled water. As a result of measuring the obtained wafer by TEM and AFM, it was confirmed that the upper oxide film was completely removed (see FIG. 1).

Example 6.

The wafer with a metal wiring coated with an oxide film of 100 에 at the top was immersed in the composition of Example 2 for 400 seconds, and then washed with distilled water. As a result of measuring the obtained wafer by TEM and AFM, it was confirmed that the upper oxide film was completely removed (see FIG. 2).

As described above, the present invention provides a composition for wet etching comprising an aqueous solution of an acid and a surfactant, and by using this in an insulating film wet process for forming a metal wiring, the insulating film can be uniformly removed without a step, and thus the semiconductor The yield and characteristics of the device can be improved.

Claims (15)

Based on acid aqueous solution, A wet etching composition comprising a surfactant represented by the compound of formula 1 as an additive: [Formula 1]

Where R is H, an alkyl group or an alkylaryl group of C ₈ -C ₂₀ , m is an integer selected from 5 to 50, n is an integer selected from 3-50. The method of claim 1, The acid aqueous solution may include at least one acid selected from the group consisting of sulfuric acid (H ₂ SO ₄ ), nitric acid (HNO ₃ ), phosphoric acid (H ₃ PO ₄ ), hydrofluoric acid (HF), acetic acid (CH ₃ COOH), and combinations thereof. Wet etching composition comprising a. The method of claim 2, The acid is wet etching composition, characterized in that contained in 1 to 40wt% with respect to the total mass of the acid aqueous solution. The method of claim 1, Wherein R is hydrogen, butylbenzyl, octyl, octyl phenyl, nonyl, nonyl phenyl, decyl, decyl phenyl, undecyl, undecyl phenyl, dodecyl or dodecyl phenyl. The method of claim 1, The compound of formula 1 is a wet etching composition, characterized in that represented by the formula (1a) or formula (1b). [Formula 1a]

[Formula 1b]

Where m is an integer selected from 5 to 50, n is an integer selected from 3-50. The method of claim 5, M is an integer selected from 5 to 20, n is a wet etching composition, characterized in that an integer selected from 5 to 10. The method of claim 1, The content of the compound of Formula 1 is a wet etching composition, characterized in that 50 to 10,000ppm with respect to the total wet etching composition. The method of claim 7, wherein The content of the compound of Formula 1 is a wet etching composition, characterized in that 50 to 1,000ppm relative to the total wet etching composition. The method of claim 8, The content of the compound of Formula 1 is a wet etching composition, characterized in that 300 to 700ppm relative to the total wet etching composition. Providing a semiconductor wafer having a lower metal wiring structure formed thereon; Forming an oxide film on the wafer; Forming a first low dielectric film having a lower dielectric constant than the oxide film on the oxide film; And And performing a wet etching process using the wet etching composition of claim 1 on the insulating film formed of the laminated film of the oxide film and the first low dielectric film to form a contact hole in which the lower metal wiring is exposed. A metal wiring formation method of a semiconductor element. The method of claim 10, The method after the first low dielectric film forming step, And forming second and third low dielectric films on the first low dielectric film, the second and third low dielectric films having a lower dielectric constant than the first low dielectric film. The method of claim 10, And the oxide film is formed to a thickness of 20 to 80% of the total thickness of the insulating film. The method of claim 10, And the first low dielectric film is formed of an HSQ or MSQ film. The method of claim 13, And the first low dielectric film is formed to a thickness of 20 to 80% of the total thickness of the insulating film. The method of claim 10, The wet etching process is a method of forming a metal wiring of a semiconductor device, characterized in that the method is immersed in the composition of claim 1 for 300 to 500 seconds at room temperature.

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