KR20080058016A - Apparatus and method for caching data - Google Patents

Abstract

A device and a method for caching data are provided to improve entire processing speed of a computer system by reducing delay caused by access from a CPU to peripheral devices, as the previously stored data of the peripheral device is transmitted when the CPU requests the access to the peripheral device. A storage device(148) stores data of more than one peripheral device(160_1 to 160_n). A CPU interface(142) receives a data access request to the peripheral device from a CPU(120). A data controller(144) searches the corresponding data from the storage device by responding to the received data access request and transfers the searched data to the CPU interface. The CPU interface transfers the data received from the data controller to the CPU. A peripheral device interface(146) is connected to the peripheral devices, and transmits a synchronization request to the data controller when the data of the peripheral device is updated by accessing the peripheral device periodically. The data controller updates the data of the peripheral device by responding to the synchronization request. A connection interface(150) connects a data cache device(140) to the peripheral devices.

Description

Data cache device and data cache method {APPARATUS AND METHOD FOR CACHING DATA}

1 illustrates a computer system in which a data cache device may be used in accordance with one embodiment of the present invention.

2 is a diagram illustrating a configuration of a data control device according to an embodiment of the present invention.

3 is a diagram illustrating a signal flow for synchronizing data with a peripheral device in a data cache device according to one embodiment of the present invention;

4 illustrates a status register in a peripheral device according to an embodiment of the present invention.

5 is a diagram illustrating a selection signal of a device for which synchronization is requested in the data cache device according to an embodiment of the present invention.

6 is a diagram illustrating a data flow when there is a request for access to a peripheral device from a CPU in a data cache device according to an embodiment of the present invention.

7 is a logical flow diagram of a method for transferring data between a CPU and a peripheral device in a data cache device in accordance with one embodiment of the present invention.

8 illustrates a connection between a CPU and a peripheral device in a conventional computer system.

TECHNICAL FIELD The present invention relates to a computer system, and more particularly, to processing access to a peripheral device of a central processing unit (CPU).

In recent years, computer systems have been used as a host to connect portable multimedia playback devices such as digital cameras, mp3 players, or portable multimedia forming devices, to connect various auxiliary storage devices using a wired connection such as USB or IEEE 1394, CD-ROM, DVD, etc. Increasingly, peripheral devices are increasingly connected, such as the connection of a magnetic storage device such as a ROM, a connection of various portable devices using a wireless connection such as WiBro, WiFi, or BlueTooth. In conventional computer systems, the CPU performs direct access to such peripheral devices.

8 is a diagram illustrating a connection between a CPU and a peripheral device in a conventional computer system. As shown in FIG. 8, the CPU 820 directly accesses the peripheral devices 860_1, 860_2, 860_3, and 860_4. The CPU 820 first issues an address (cpu_addr) 821 and a control signal (cpu_rw) 822 of peripheral devices 860_1, 860_2, 860_3, and 860_4 that are desired to be accessed. This address is converted by the address decoding logic 840 into the chip select signal (cs_peri) 841 of the corresponding peripheral device and transferred to the peripheral devices 860_1, 860_2, 860_3 and 860_4 through the connection interface 850. The selected device processes the access request (read or write) and then issues a processing complete signal. In FIG. 8, the processing completion signal includes the processing completion signal peri_dtack1 861_1 issued by the peripheral device 1, the processing completion signal peri_dtack2 861_2 issued by the peripheral device 2, and the processing completion signal issued by the peripheral device 3 ( peri_dtack3 861_3 and a processing completion signal peri_dtack4 861_4 issued by the peripheral device 4. The CPU 820 receives the processing completion signal cpu_dtack 842 and data cpu_data 843 through the address decoding logic 840.

As described above, direct performing access of the CPU 820 in the conventional computer system 800 is only accessed after the CPU 820 receives the processing completion signal cpu_dtack 842 and data cpu_data 843. Terminates, which causes a significant delay. For example, suppose that the access times to the peripheral devices 860_1, 860_2, 860_3, and 860_4 shown in FIG. 8 are 90 ns, 120 ns, 150 ns, and 50 ns, respectively, and that accesses to these devices are issued in sequence almost simultaneously. . All accesses to the remaining peripheral devices must be stopped until the access to the peripheral device 1 860_1 to which access is first started ends, that is, for a time of 90 ns. Next, access to the remaining devices is likewise stopped until the access to peripheral device 2 860_2 ends. Thus, access to Peripheral Device 4 860_4 is delayed 360 ns because the actual access time is only 50 ns but must wait for access to other devices. As such, the structure directly accessed by the CPU increases the delay time because all accesses to one peripheral device need to be stopped. As computer processing speeds increase, the delay effect due to access to these peripherals becomes even more pronounced as a bottleneck.

In a situation where more connections to peripheral devices are being made by using various computers, in order to fully utilize the processing speed of the rapidly increasing computer, it is required to reduce the bottleneck effect of access to such peripheral devices.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data cache device and a data cache method capable of improving the overall processing speed of a computer system by reducing delay caused by access to a peripheral device from a CPU.

According to one embodiment of the invention, there is provided a data cache device connected to a CPU and one or more peripheral devices. The data cache device includes a storage device for storing data of the connected peripheral device, and when access is requested from the CPU to the connected peripheral device, the data cache device transmits the data stored in the storage device to the CPU.

According to another embodiment of the present invention, there is provided a data cache device connected to a CPU and one or more peripheral devices. The data cache device includes a storage device for storing data of a connected peripheral device, a CPU interface for receiving an access request from the CPU to the connected peripheral device, and a response to the storage device in response to the received access request. And a data control device for requesting the data and receiving the data from the storage device and transferring the data to the CPU interface. The CPU interface receives the corresponding data from the data control device and transmits the data to the CPU.

In one embodiment, the data cache device is connected to the peripheral device, the peripheral device interface for transmitting a synchronization request to the data control device when the data of the peripheral device is updated by accessing the peripheral device every predetermined time It further includes. The data control device updates corresponding data of the storage device in response to the synchronization request.

According to another embodiment of the invention, a method is provided for transferring data in a data cache device coupled between a CPU and a peripheral device. The method includes storing data of the peripheral device in a storage device located within the data cache device, and in response to receiving an access request from the CPU to the peripheral device, transferring data stored in the storage device to the CPU. Transmitting.

Hereinafter, the present invention will be described in detail with reference to FIGS. 1 to 7.

1 is a diagram illustrating a computer system in which a data cache device according to an embodiment of the present invention may be used. The computer system 100 may include one or more peripheral devices 160_1, 160_2,..., Connected to the data cache device 140 via a central processing unit 120, a data cache device 140, and a connection interface 150. 160_n). According to the present invention, the data cache device 140 stores data of the peripheral devices 160_1, 160_2,..., 160_n. In one embodiment, when there is a request for access of data from the CPU 120 to any of the peripheral devices 160_1, 160_2,..., 160_ n, the peripheral device 160_1, 160_2,... 160_n) instead of performing direct access, the data of the peripheral device stored in the data cache device 140 is searched and transmitted to the CPU 120. Instead of performing direct access to the peripheral device as described above, the access request is performed by the data cache device 140 capable of fast processing, thereby preventing the speed delay and the bottleneck caused by the access to the relatively slow peripheral device. have.

The CPU 120 shown in FIG. 1 receives and processes data from peripheral devices 160_1, 160_2,..., 160_ n and various input devices (not shown), and then outputs the results to peripheral devices 160_1 and 160_2. , ..., 160_n) and a device for controlling and adjusting a series of processes for transmitting to various output devices (not shown). The CPU 120 includes both a known device capable of performing the above-described operation or a device to be developed in the future, and the detailed description thereof will be omitted herein.

The data cache device 140 stores data of the peripheral devices 160_1, 160_2,..., And 160_n, and requests for access of data from the CPU to the peripheral devices 160_1, 160_2,..., 160_n. If the data is transmitted to the CPU (120). In an embodiment, the data cache device 140 may include a CPU interface 142 that interfaces with the CPU 120 and a peripheral device interface that interfaces with the peripheral devices 160_1, 160_2,..., 160_ n. 146), the storage device 148 that stores data of the peripheral devices 160_1, 160_2,..., 160_ n, and the CPU interface 142, the peripheral device interface 146, and the data storage device 148. It may include a data control device 144 connected to and control them. In one embodiment, the storage device 148 includes cache data RAM to facilitate rapid data communication with the CPU 120.

The CPU interface 142 is connected to the CPU 120 to detect a request for access to the peripheral devices 160_1, 160_2,..., 160_ n of the CPU 120, and select a chip for the peripheral device. Issue a. Thereafter, the access request data and the processing completion signal are received from the data control device 144 and transferred to the CPU 120.

The peripheral device interface 146 accesses the connected peripheral devices 160_1, 160_2,..., 160_ n every predetermined time to update data in the peripheral devices 160_1, 160_2,..., 160_ n. If the data update is confirmed, the data control device 144 synchronizes the data, that is, the data of the corresponding peripheral device and the data of the corresponding device stored in the storage device 148 match. Send a request to update the data in.

The data control device 144 is connected to the CPU interface 142 to receive a request for access of data from the CPU interface 142 to the peripheral device. In response to receiving such an access request, the data control device 144 receives an arbitration, an urgent access request, access to the storage device 148, that is, a corresponding peripheral device requested by the storage device 148. Searching and reading the data of the data, and issuing a stack signal indicating that the requested data has been processed. The data control device 144 is also connected to the peripheral device interface 146 to receive a data synchronization request for a peripheral device from the peripheral device interface 146. In response to receiving the data synchronization request, the data control device 144 updates the data of the peripheral device in the storage device 148.

The connection interface 150 is responsible for the connection between the data cache device 140 and the peripheral devices 160_1, 160_2,..., 160_n. The connection interface 150 includes a dedicated interface for a corresponding peripheral device, such as a printer or a display device. The connection interface 150 includes a general-purpose serial interface such as RS-232C and a SCSI or IDE for an auxiliary storage device such as a hard disk or an MO, but the connection interface 150 herein is not limited thereto.

The peripheral devices 160_1, 160_2,..., 160_n include an input / output device and an auxiliary storage device connected to the CPU and controlled by the CPU but physically located at a different location from the CPU. Among the peripheral devices 160_1, 160_2, ..., 160_ n, input devices include card readers, card punches, paper tape readers, punches, keyboards, mice, scanners, light pens, etc., and output devices include display devices. , Printers, plotters, and the like. Auxiliary storage devices include magnetic tapes, magnetic disks, optical disks, and the like, but the peripheral devices 160_1, 160_2,..., 160_n of the present application are not limited thereto.

2 is a diagram illustrating a configuration of a data control device according to an embodiment of the present invention. The data control device 200 is a state machine that stores the current state in the storage device 148 (FIG. 1) for each peripheral device connected via the peripheral interface 146 (FIG. 1). (220), an arbiter 240 for scheduling access to the storage device 148, a synchronization request from the dtack forming unit 260 and peripheral device interface 146 that issues a processing completion signal to be sent to the CPU. Update unit 280 to receive and deliver to the arbitration unit 240.

The state stored in the state machine 220 may include, for example, an update state, a read state, and an idle state. The update state means that data of the storage device 148 for the corresponding device is updated for synchronization between the peripheral device and the storage device. The read state means that data in storage 148 for that device is being read at the request of the CPU. Idle state means that no device or CPU is being accessed. The state machine 220 may store a state including a storage device such as a RAM, for example.

The arbitration unit 240 schedules operations according to the state of the state machine 220 and a predetermined priority in response to the received request signal, and transitions the state of the state machine 220. Table 1 is a table showing the data processing unit 240 processes the request according to the state of the state machine 220 and an example of state transition.

State Sync (Update) Request Read request Idle Update State Transition update Read State Transition Reading update X X State maintenance Hold Reading State maintenance Hold X X

As shown in Table 1, when the mediation unit 240 receives a data synchronization request from the update unit 280 for the device in the idle state, the arbitration unit 240 changes the state of the device in the state machine 220 to update. The storage device 148 transmits a cache address and a cache write request signal for the device. In one embodiment, the arbitration unit 240 updates the data of the storage device 148 until the reading is complete when an update request is received for the device being read by the CPU's access request, that is, for the device in the read state. You can withhold it. When the reading is complete, the arbitration unit 240 changes the state of the device in the state machine 220 to update and sends a cache address and cache write request signal for the device to the storage device 148.

Similarly, when a read request is received from the CPU for a device in an idle state, the arbitration unit 240 changes the state of the device in the state machine 220 to read and the storage device 148 for the device. Carries a cache address and a cache read request signal. In one embodiment, the arbitration unit 240 may suspend the read until the update is complete, if a read request is received from the CPU for the device that is in the update state, that is, in synchronization with the peripheral device. When the update is completed, the arbitration unit 240 changes the state of the device in the state machine 220 to read, and sends the cache address and the cache read request signal for the device to the storage device 148. When the mediation unit 240 receives data from the storage device 148, the arbitration unit 240 requests the stack forming unit 260 to form a stack signal, and transfers the received data to the CPU interface.

 In one embodiment, the arbitration unit 240 checks whether a pending operation is completed when the current operation on the storage device 148 is completed, and performs an operation according to a predetermined priority when there is a pending operation. If there is no pending operation, the state of the device in the state machine 320 is changed to idle.

As described above, according to an embodiment of the present invention, the data of the peripheral device is stored in the storage device, and when the request for access to the peripheral device is received from the CPU, the data stored in the data cache device is not directly connected to the peripheral device. Transmission can significantly reduce access time to peripheral devices, which are the bottleneck in high-performance, high-speed systems.

3 is a diagram illustrating a signal flow for synchronizing data with a peripheral device in a data cache device according to an embodiment of the present invention. The peripheral interface 146 of the data cache device 140 (FIG. 1) checks whether data is updated in the peripheral device. In one embodiment, such confirmation may be performed by accessing a predetermined status register in the peripheral device and reading whether an event has occurred. In one embodiment, the peripheral device interface 146 may access the status register in the peripheral device at predetermined intervals.

4 is a diagram illustrating a status register in a peripheral device according to an embodiment of the present invention. As shown in FIG. 4, when the predetermined bit value of the status register is 1, the third bit value in the example is 1, which means that data of the device has been updated.

When an event occurs in the peripheral device, that is, when the data update in the peripheral device is confirmed, the peripheral device interface 146 transmits a device selection signal (ref_cs) 311 to the data control device 144 to store the storage device 148. Request synchronization). In one embodiment, ref_cs 311 includes an n-bit device selection signal.

5 is a diagram illustrating a selection signal of a device for which synchronization is requested in a data cache device according to an embodiment of the present invention. As shown in FIG. 5, the device may be selected by setting the bit value corresponding to the device for which data synchronization is requested among n bits as 1. In the example of FIG. 5, the third bit value corresponding to the peripheral device 3 is set to 1 to request a data update of the peripheral device 3 among the data of the storage device 148.

The data control device 144 schedules synchronization of the storage device 148 with the device in response to receiving ref_cs 311. In an embodiment, referring to FIG. 2, the ref_cs 311 is transmitted to the updater 280, and the updater 280 sends the mediation unit 240 to the arbitration unit 240 in response to receiving the ref_cs 311. Request synchronization of storage device 148. When the data control device 144 determines the synchronization of the storage device 148 with the device, the peripheral device interface 146 sends a device selection signal (cs_peri) 313, an address (peri_addr) 314, and a read request. A signal peri_r 315 is transmitted to the peripheral device, and data peri_data 317 is received from the device. Peripheral interface 146 forwards the received data to data control device 144 (ref_data 319). In response to receiving the ref_data 319, the data control device 144 transmits a cache address, a cache write request signal w 325, and the received data cs_data 326 for the device to the storage device 148. To pass. In one embodiment, the cache address includes a device selection signal (cs) 323 and a cache address (cs_addr) 324. In one embodiment, cs 416 includes n bits of select signal. In one embodiment, cs_addr 317 contains 32 bits of address data. In one embodiment, referring to FIG. 2, ref_data 319 is received at the arbitrator 240, and the arbitrator 240 selects the device as storage 148 in response to receiving ref_data 319. The signal, address and read request signal can be sent.

 As described above, according to an exemplary embodiment of the present invention, the data stored in the data cache device is synchronized with the peripheral device at predetermined intervals so that the data can be accessed without accessing the peripheral device when requesting access from the CPU to the peripheral device, thereby increasing access time. This can significantly reduce the overall performance of the computer system.

6 is a diagram illustrating a data flow when there is a request for access to a peripheral device from a CPU in a data cache device according to an embodiment of the present invention. The CPU interface 142 of the data cache device 140 receives an address (cpu_addr) 611 and a read request signal (cpu_r) 612 of a peripheral device from the CPU. In one embodiment, cpu_addr 611 contains 32 bits of address data.

In response to receiving the cpu_addr 611 and cpu_r 612 signals, the CPU interface 142 sends the cache address and cache read request signal (cache_r) 616 for the peripheral device to the data control device 144. do. In one embodiment, the cache address includes a device selection signal (cs_cache) 614 and a cache address (cache_addr) 615. In one embodiment, cs_cache 614 includes n bits of select signal. In one embodiment, cache_addr 615 contains 32 bits of address data.

In response to receiving the cs_cache 614, cache_addr 615, and cache_r 616, the data control device 144 sends the cache address and cache read request signal r for the device to the storage device 148 according to the scheduling. 620 is received, and data (cd) 631 is received. In one embodiment, the cache address includes a device selection signal (cs) 618 and a cache address (cs_addr) 619. In one embodiment, cs 618 includes n bits of select signal. In one embodiment, cs_addr 619 contains 32 bits of address data. The cd 631 contains a 32-bit data signal. The data control device 144 transfers the received data to the CPU interface 142 in response to receiving the data (cd) 631 from the storage device 148 (cache_data) 632, and a processing completion signal (cache_dtack). 633).

The CPU interface 142 transmits the received signals to the CPU in response to receiving the data (cache_data) 632 and the processing completion signal (cache_dtack) 633 from the data control device 144 (cpu_data) 634 And processing completion signal (cpu_dtack) 635.

7 is a logical flow diagram of a method for transferring data between a CPU and a peripheral device in a data cache device according to one embodiment of the invention. In operation 710, it is checked whether data of the connected peripheral device is updated. In one example, step 710 may be performed by reading the status register in the peripheral device from the peripheral device interface 146 of the data cache device 140 to confirm whether an event has occurred. If the data update of the peripheral device is confirmed, the data of the storage device in the data cache device is synchronized (updated) (step 720). In one example, step 720, as shown in FIG. 3, requests the data control device 144 to synchronize to the peripheral device from the peripheral device interface 146, and under the control of the data control device 144. This can be done by delivering the updated data to the storage device 148. In one embodiment, the update request signal and the update data may be delivered to the update unit 280 and the arbitration unit 240 of the data cache apparatus 200, as shown in FIG. 2. In this case, the arbitration unit 240 may deliver the update data to the storage device by scheduling the state according to the state of the state machine 220 and a predetermined priority.

In response to receiving the access request from the CPU to the peripheral device in step 730, data of the peripheral device stored in the storage device is transferred to the CPU. In one example, step 730 is the data control device 144 in response to receiving an access request from the CPU to the peripheral device at the CPU interface 142 of the data cache device 140, as shown in FIG. 6. By requesting access to the storage device 148 and receiving the corresponding data from the storage device 148 under the control of the data control device 144. In one embodiment, the request for access to the storage device 148, in accordance with the state and predetermined priority of the state machine 220 in the arbitration unit 240 of the data cache device 200, as shown in FIG. Access can be performed by scheduling and requesting a read from the storage device.

While the invention and its various functional components have been described with reference to specific embodiments, the invention may be implemented in hardware, software, firmware, middleware, or a combination thereof, and the system, subsystem, components, or subs thereof. It should be understood that it can be utilized as components. If implemented in software, the elements of the invention are instructions / code segments for performing the necessary tasks. The program or code segments may be stored in a machine readable medium, such as a processor readable medium, a computer program product, or transmitted by a computer data signal or a signal modulated by a carrier that is embodied in a carrier wave. It can be sent over the link. Machine readable media or processor readable media may include any medium that can store or transmit information in a form readable and executable by a machine (eg, processor, computer, etc.).

Although the present invention has been described and illustrated with reference to the embodiments, those skilled in the art, various modifications and equivalent other embodiments without departing from the spirit and scope of the present invention defined by the appended claims It will be appreciated that examples are possible.

According to the present invention, the following effects can be obtained.

First, when a request for access from a CPU to a peripheral device is transmitted, data of a pre-stored peripheral device is transmitted to the CPU, thereby reducing the delay caused by access to the peripheral device, thereby improving the overall processing speed of the computer system.

Second, it checks whether the connected peripheral device is updated and updates the data of the peripheral device, if it is updated, so that the same data can be transmitted when the CPU requests access, but only the updated data is updated. Do not overload the entire computer system.

Claims (8)

A data cache device attached to a CPU and one or more peripherals, A storage device for storing data of the one or more peripheral devices Including, And send the data stored in the storage device to the CPU when access is requested from the CPU to the peripheral device. The device of claim 1, wherein the device accesses the peripheral device every predetermined time to synchronize data of the storage device with data of the updated peripheral device when the data of the peripheral device is updated. The apparatus of claim 1, wherein the storage device comprises cache RAM. A data cache device attached to a CPU and one or more peripherals, A storage device for storing data of the one or more peripheral devices; A CPU interface for receiving a request to access data from the CPU to the peripheral device; And A data control device for retrieving corresponding data from the storage device in response to the received access request and transferring the retrieved data to the CPU interface Wherein the CPU interface receives the retrieved data from the data control device and transmits the retrieved data to the CPU. The method of claim 4, wherein Peripheral device interface connected to the peripheral device, for accessing the peripheral device every predetermined time to transmit a synchronization request to the data control device when the data of the peripheral device is updated More, And the data control device updates corresponding data of the storage device in response to the synchronization request. A method for passing data in a data cache device connected between a CPU and a peripheral device, Storing the data of the peripheral device in a storage device in the data cache device, In response to receiving the access request from the CPU to the peripheral device, transmitting data stored in the storage device to the CPU. Including, the method. The method of claim 6, wherein storing the data of the peripheral device in a storage device located in the data cache device comprises: Accessing the peripheral device to check whether data of the peripheral device has been updated; and If data of the peripheral device is updated, synchronizing data of the peripheral device stored in the storage device with data of the updated peripheral device Including, the method. A computer readable recording medium storing computer executable instructions for performing the method of claim 6.

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