KR20080056795A - Memory device and method for testing of memory device - Google Patents

Abstract

A memory device and a method for testing the memory device are provided to perform static burn-in mode, dynamic burn-in mode and scan mode in a wafer burn-in step. A memory device comprises a memory block(400) and a number of input pins(100) to receive a number of mode selection signals. A test mode selection block(200) enables one of a number of mode signals on the basis of the mode selection signals and then outputs the enabled mode signal. A pattern generation block(300) generates a burn-in clock signal, an address and a test pattern in response to a received mode signal. A test pattern comparison block(500) compares the test pattern outputted from the memory block with a test pattern read out from the memory block, and then outputs comparison result. An output pin(600) outputs the comparison result to a host.

Description

Memory device and method for testing of memory device

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 illustrates a block diagram of a memory device according to an embodiment of the present invention.

FIG. 2 shows a detailed block diagram of the address counter block shown in FIG. 1.

FIG. 3 shows a detailed block diagram of the pattern generation block shown in FIG. 1.

4A is a diagram illustrating an example of a test pattern in the dynamic burn-in mode.

4B is a diagram illustrating an example of a test pattern in scan mode.

5A and 5B illustrate a burn-in test method that can be constructed using an embodiment of the present invention.

6 is a flowchart illustrating a test method of a memory device according to an exemplary embodiment of the present invention.

The present invention relates to a memory device and a test method of the memory device, and more particularly, to a static burn-in mode and a dynamic burn-in during wafer burn-in testing. The present invention relates to a memory device capable of performing a scan mode and a scan mode, and a test method of the memory device.

The burn-in test in a semiconductor device is a test performed to effectively remove a defective product and to improve the reliability of a semiconductor product before the product is released.

Typical burn-in tests are divided into wafer burn-in tests performed in a wafer state and package burn-in tests conducted in a package state.

The burn-in test is divided into a static burn-in mode, a dynamic burn-in mode, and a scan mode according to the type and method of stress applied to the memory cell array.

The static burn-in mode is a method of directly stressing and testing a memory cell array of the memory device. The dynamic burn-in mode is a method of applying stress by addressing respective address lines. The scan mode is a mode for testing the memory device and immediately monitoring the test result.

However, in the conventional wafer burn-in test, only the static burn-in mode test method is used because a plurality of address lines are simultaneously enabled and the test is performed, and the dynamic burn-in mode that tests each address by addressing is used. Could not be used.

In addition, conventional wafer burn-in tests using only the static burn-in mode apply the static burn-in stress directly to the memory cell array, so that peripheral circuits other than the memory cell array (eg, a low address pass) , Column address paths, and data in / out paths, etc.) have been difficult to test by applying burn-in stress.

In the wafer burn-in mode, since the scan mode for checking the test result of the memory device cannot be used, there is no method of immediately checking the test result of the memory device.

Therefore, a burn-in test method capable of performing the same test as the package burn-in test in the wafer burn-in test and immediately knowing the burn-in test result is required.

Accordingly, an object of the present invention is to provide a memory device and a test method of the memory device capable of performing the static burn-in mode, the dynamic burn-in mode, and the scan mode test modes in the wafer burn-in step. .

A memory device according to the present invention includes a memory block; A plurality of input pins for receiving a plurality of mode selection signals; A test mode selection block for enabling and outputting any one of a plurality of mode signals based on the plurality of mode selection signals; A pattern generation block for generating a burn-in clock signal, an address, and a test pattern in response to the received mode signal; A test pattern comparison block configured to receive the test pattern output to the memory block and the test pattern read from the memory block, compare each other, and output a comparison result; And an output pin for outputting the comparison result to the host.

The pattern generation block may include a clock generation block for outputting the burn-in clock signal in response to the received mode signal; An address counter block for counting and outputting an address based on the burn-in clock signal and a first selection signal, and outputting an MSB carry bit generated when the address is counted; And a test pattern generation block configured to output one of the first selection signal and the second selection signal based on the received mode signal, and generate the test pattern in response to the MSB carry bit.

Each of the plurality of mode signals is a signal for selecting a static burn-in mode, a dynamic burn-in burn-in mode, or a scan mode, respectively, The mode signal received by the pattern generator is either a dynamic burn-in mode signal or a scan mode signal. The static burn-in mode, dynamic burn-in mode, and scan mode are test modes that can be performed in the wafer state of the memory device.

The first selection signal is a signal for selecting which of a row address and a column address to be addressed first in the dynamic burn-in mode, and the second selection signal. Is a signal for selecting whether to write or read the test pattern in the scan mode.

The MSB carry bit is either the first MSB or the second MSB, and the address counter block receives the burn-in clock signal and the first MSB, and responds to the first select signal to the burn-in clock signal or the MSB. A first selection circuit outputting any one of the first MSBs; A first address counter block having a plurality of address counters, counting and outputting a first address in response to an output signal of the first selection circuit, and outputting the second MSB generated when the first address is counted; A second selection circuit which receives the burn-in clock signal and the second MSB and outputs either the burn-in clock signal or the second MSB in response to the first selection signal; And a second address counter block having a plurality of address counters, counting and outputting a second address in response to an output signal of the second selection circuit, and outputting the first MSB generated when the second address is counted. do.

The test pattern generation block includes a plurality of counters for generating and outputting the test pattern.

A test method of a memory device according to the present invention includes: receiving a plurality of mode selection signals; Enabling and outputting any one of a plurality of mode signals based on the plurality of mode selection signals; Generating and outputting pattern signals in response to the received mode signal; And receiving a data pattern output from the memory block and a data pattern read from the memory block, comparing the data pattern with each other, and outputting a comparison result.

The generating of the pattern signal may include outputting a burn-in clock signal in response to the received mode signal; Counting and outputting an address based on the burn-in clock signal and a first selection signal, and outputting an MSB carry bit generated when the address is counted; And outputting the first selection signal or the second selection signal based on the received mode signal, and generating the test pattern in response to the MSB carry bit.

The first selection signal is a signal for selecting which of a row address and a column address to be addressed first in the dynamic burn-in mode, and the second selection signal. Is a signal for selecting whether to write or read the test pattern in the scan mode.

The test method of the memory device is performed in a wafer state of the memory device.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like reference numerals.

1 illustrates a block diagram of a memory device according to an embodiment of the present invention. Referring to FIG. 1, the memory device 1 includes a plurality of input pins 100, a mode selection block 200, a pattern generation block 300, a memory block 400, a pattern comparison block 500, and an output. A pin 600 is provided.

The plurality of input pins 100 receives mode selection signals S1 and S2 and outputs them to the mode selection block 200.

The mode selection block 200 receives the mode selection signals S1 and S2 and based on the combination of the received mode selection signals S1 and S2, the mode signals (eg, the static burn-in mode). One of a signal (static burn-in), a dynamic burn-in mode signal (dynamic burn-in), and a scan mode signal (SCAN) is selected.

For example, when each of the mode selection signals S1 and S2 is 'Low, Low' (or '0, 0'), the static burn-in mode signal Static burn-in is enabled and 'Low' , High '(or' 0, 1 '), dynamic burn-in mode signal (Dynamic burn-in),' Low, Low '(or' 1, 1 ') scan mode signal (SCAN) Is enabled.

The pattern generation block 300 receives one of the dynamic burn-in mode signal and the scan mode signal SCAN.

The pattern generation block 300 includes a burn-in clock generator 310, an address generator 320, and a test pattern generator 330.

The burn-in clock generator 310 receives an input mode signal (for example, one of a dynamic burn-in mode signal and a scan mode signal), and in response to the received mode signal, burn-in clock signal ( CLK).

The clock cycle of the burn-in clock signal CLK has a fast clock cycle (for example, 15 ns to 100 ns) and may be implemented to enable various cycle options. Accordingly, the burn-in clock generator 310 may selectively output the burn-in clock cycle corresponding to the operating speed of the memory block 400.

The address counter 320 sequentially counters the addresses in response to the burn-in clock signal CLK and outputs the generated addresses to the memory block 400.

FIG. 2 shows a block diagram of the address counter shown in FIG. Referring to FIG. 2, the address counter 320 includes a first selection block 321, a first address counter block 322, a second selection block 323, and a second address counter block 324. .

The first selection block 321 receives the burn-in clock signal CLK and a first Most Significant Bit (MSB), and outputs the first selection signal X-Fast / from the test pattern generation block 330. The burn-in clock signal CLK or the first MSB is output in response to the Y-Fast or the address mode selection signal SEL.

The first selection signal X-Fast / Y-Fast is a signal for selecting which of a row address and a column address to be addressed first in the dynamic burn-in mode, and the address mode selection signal SEL is a scan. In mode, it is a signal for selecting which of the row address and the column address to be addressed first.

The first address block 322 is provided with a plurality of address counters 322-1, 322-2,..., 322-n, and in response to an output signal of the first selection block 321. One address (e.g., a row address) is counted and output, and the MSB carry bit generated at the first address count is output as the second MSB. Here, the MSB carry bit is a carry bit generated at the last address counter 322-n.

The second selection block 323 receives the burn-in clock signal CLK and the second MSB and outputs the first selection signal X-Fast / Y-Fast output from the test pattern generation block 330. Or one of the burn-in clock signal CLK or the second MSB in response to the address mode selection signal SEL.

The second address block 324 includes a plurality of address counters 324-1, 324-2,..., 324-n, and in response to an output signal of the second selection block 323. Two addresses (e.g., column addresses) are counted and output, and the MSB carry bit generated at the second address count is output as the first MSB. Here, the MSB carry bit is a carry bit generated at the last address counter 324-n.

That is, in the dynamic burn-in mode, the first selection block 321 responds to the first level of the first selection signal X-fast / Y-fast (eg, level 'High'). To output the burn-in clock signal CLK and output the first MSB in response to a second level (eg, level 'Low'). The second selection block 323 outputs a second MSB in response to a first level of the first selection signal X-fast / Y-fast (for example, the level 'High'), and outputs the second MSB. , In response to the level 'Low', outputs the burn-in clock signal CLK.

Accordingly, the address counter block 320 may include a first address (eg, a low address) during a first level (eg, level 'high') period of the first selection signal X-fast / Y-fast. Address is counted and output in order of a second address (eg, column address), and the first MSB is output as an MSB carry bit outputted to the test pattern generation block 330.

On the other hand, during the second level (eg, level 'Low') period of the first selection signal X-fast / Y-fast, the first address (eg, column address) to the first address (eg Address is counted and output in order of a row address, and the second MSB is output as an MSB carry bit outputted to the test pattern generation block 330.

In the scan mode, an address selection block (not shown) may be further provided to generate an address mode selection signal SEL based on the scan mode signal SCAN. The address mode selection signal SEL may be fixed at one signal level to operate the address counter block 320 only with one address counter path.

For example, when the address mode selection signal SEL has only a first level (eg, 'High'), the address counter block 320 may have a second address at the first address (eg, a low address). When the address is counted in order of address (for example, column address), and the address mode selection signal SEL has only a second level (for example, 'Low'), the address counter block is the second address. It operates by counting addresses in order of first address (for example, row address) from (for example, column address).

The test pattern generation block 330 receives one of the dynamic burn-in mode signal or the scan mode signal and the MSB carry bit output from the address counter block 320 to test the test pattern generation block 330. Generates a pattern.

FIG. 3 shows an internal block diagram of the test pattern generation block shown in FIG. 1. 1 to 3, the test pattern generation block 330 includes burn-in state counters 331, 332, and 333 for generating a plurality of test patterns. .

For example, the first burn-in state counter 331 determines the level of the first selection signal (X-fast / Y-fast) in the dynamic burn-in mode and the scan mode. Determines the level of the second selection signal (Write / Read). The second selection signal Write / Read is a signal for selecting whether to record or reproduce the test pattern in the scan mode.

The second burn-in state counter 332 outputs the data pattern even data and odd data at the same level or inverts the even data and odd data. Decide if

The third burn-in state counter 333 determines whether to make the data pattern low or high.

Based on the output of the second in-state counter 332 and the third burn-in state counter 333, the test pattern generation block 330 may generate a data pattern (eg, 00 / FF / AA / 55). Outputs

In other words, the test pattern generation block 330 generates eight test patterns according to a dynamic burn-in mode or a scan mode, and outputs eight test patterns to the memory block 400.

4A shows an example of a test pattern in the dynamic burn-in mode, and FIG. 4B shows an example of a test pattern in the scan mode. 3 to 4B, in the dynamic burn-in mode, the test pattern generation block 330 may include a first selection signal (X-Fast or Y-Fast) and a data pattern (eg, 00 Eight test patterns (FIG. 4A) can be generated according to / FF / AA / 55).

In the scan mode, the test pattern generation block 330 includes eight test patterns according to a second selection signal (Write / Read) and the data pattern (for example, 00 / FF / AA / 55) (FIG. 4B). Can be generated.

As a result, the pattern generation block 330 transfers the test patterns (FIG. 4A or FIG. 4B) to the memory block 400 according to the dynamic burn-in mode or the scan mode. Output

The memory block 400 includes a row address path 410, a column address path 420 and a data in pass 430, a data out pass 440, and a memory. The cell array 450 is provided.

The row address path 410 and the column address path 420 may be a dynamic burn-in mode signal output from the mode selection block 200 and an address signal output from the address counter block 320. And activates the word line and the data line of the memory cell array 450.

The memory block 400 transfers address and test patterns (eg, FIG. 4A or FIG. 4B) to the row / column address path according to a dynamic burn-in mode or a scan mode. The test patterns are received through the data in passes 410 and 420, and output to the memory cell array 450.

In addition, in the scan mode, the memory block 400 writes a data pattern (eg, 00 / FF / AA / 55) to the memory cell array 450 in response to a state of a received test pattern. Alternatively, the data pattern (eg, 00 / FF / AA / 55) recorded in the memory cell array 450 is output through the data out pass 440.

The test pattern comparison block 500 includes a data pattern (eg, 00 / FF / AA / 55) recorded in the memory cell array 450 by a test pattern in a scan mode, and a state of the test pattern. In response, data patterns (for example, 00 / FF / AA / 55) reproduced from the memory cell array 450 are received and compared with each other, and a comparison result is output.

For convenience of explanation, a test pattern composed of eight states according to an embodiment of the present invention will be described as an example. Referring back to FIG. 4B, the first state outputs and writes a '00' pattern to the memory block. The '00' pattern is reproduced in the second state.

The reproduced '00' pattern is output to the comparison block 500 through the data out pass 440, and at the same time, the test pattern generation block 330 outputs a '00' pattern to the comparison block 500. Done.

That is, eight test states are repeatedly performed by writing / reading each of four data patterns (eg, 00 / FF / AA / 55).

As a result, the pattern comparison block 500 receives a read result of a '00' data pattern output from the test pattern generation block 330 and a '00' data pattern output from the memory block 400 to each other. The comparison result is output through the output pin 600 as a pass / fail signal.

5A and 5B illustrate test methods that can be configured by applying an embodiment of the present invention. Referring to FIG. 5A, the memory device 1 performs a scan mode after performing a static burn-in mode test (S11) when performing the wafer burn-in test. Output the result (S12, S13), perform a dynamic burn-in mode based on the result (S14), and then perform the scan mode again (S15) It may be implemented to determine the failure of the memory device 1 (S16).

Referring to FIG. 5B, the wafer burn-in test is performed after performing a static burn-in mode and a dynamic burn-in mode in succession (S21 and S22). The scan mode may be performed (S23) to finally determine the failure of the memory device 1 (S24). In the embodiment of the present invention, two embodiments have been described, but a wafer burn-in test method may be implemented by more various methods.

6 is a flowchart illustrating a test method of a memory device according to an exemplary embodiment of the present invention. 1 and 6, when a wafer burn-in mode of the memory device 1 is started, the memory device 1 receives a test selection signal through a plurality of input pins 100. S1 and S2 are received (S710), and one of the plurality of mode signals is enabled based on the received test selection signals S1 and S2 (S720).

Each of the plurality of mode signals is a signal for selecting any one of a static burn-in mode, a dynamic burn-in mode, and a scan mode.

If any one of the dynamic burn-in mode or the scan mode signal is enabled among the plurality of mode signals, the mode selection block 200 is the pattern generation block 300. A dynamic burn-in mode signal or a scan mode signal is output (S720).

The memory device 1 outputs a burn-in clock signal CLK in response to the received dynamic burn-in mode signal or scan mode signal. In response to the -in clock signal CLK, the address is sequentially counted and output, and the MSB (Most Significant Bit) carry bit generated at the address counter is output. The memory device 1 generates test patterns in response to any one of the dynamic burn-in mode signal or the scan mode signal and the MSB carry bit (S730).

When the scan mode signal is enabled, the memory device 1 compares the data pattern output to the memory block 400 with the data pattern output from the memory block and compares the data pattern with the data pattern. The test result of the memory block 400 is output (S740 and S750).

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the memory device and the test method of the memory device according to the present invention perform the static burn-in mode, the dynamic burn-in mode, and the scan mode test in the wafer burn-in mode. It is possible to increase the performance of the package and to replace the package burn-in test.

Claims (11)

       Memory block; A plurality of input pins for receiving a plurality of mode selection signals; A test mode selection block for enabling and outputting any one of a plurality of mode signals based on the plurality of mode selection signals; A pattern generation block for generating a burn-in clock signal, an address, and a test pattern in response to the received mode signal; A test pattern comparison block configured to receive the test pattern output to the memory block and the test pattern read from the memory block, compare each other, and output a comparison result; And And an output pin for outputting the comparison result to a host. The method of claim 1, wherein the pattern generation block, A clock generation block for outputting the burn-in clock signal in response to the received mode signal; An address counter block for counting and outputting an address based on the burn-in clock signal and a first selection signal, and outputting an MSB carry bit generated when the address is counted; And And a test pattern generation block configured to output one of the first selection signal and the second selection signal based on the received mode signal, and generate the test pattern in response to the MSB carry bit. The method according to any one of claims 1 and 2, Each of the plurality of mode signals, A signal for selecting a static burn-in mode, a dynamic burn-in burn-in mode, or a scan mode, respectively, The mode signal received by the pattern generator, A memory device which is either a dynamic burn-in mode signal or a scan mode signal. The method of claim 3, The static burn-in mode, dynamic burn-in mode, and scan mode are test modes that may be performed in a wafer state of the memory device. The method of claim 2, The first selection signal, In the dynamic burn-in mode, the signal selects which of the row address and column address should be addressed first. The second selection signal is, The memory device is a signal for selecting whether to write or read the test pattern in the scan mode. The method of claim 2, The MSB carry bit is either one of the first MSB or the second MSB, The address counter block, A first selection circuit receiving the burn-in clock signal and the first MSB and outputting either the burn-in clock signal or the first MSB in response to the first selection signal; A first address counter block having a plurality of address counters, counting and outputting a first address in response to an output signal of the first selection circuit, and outputting the second MSB generated when the first address is counted; A second selection circuit which receives the burn-in clock signal and the second MSB and outputs either the burn-in clock signal or the second MSB in response to the first selection signal; And A second address counter block having a plurality of address counters, counting and outputting a second address in response to an output signal of the second selection circuit, and outputting the first MSB generated at the time of counting the second address; Memory device. The method of claim 2, The test pattern generation block, And a plurality of counters for generating and outputting the test pattern. Receiving a plurality of mode selection signals; Enabling and outputting any one of a plurality of mode signals based on the plurality of mode selection signals; Generating and outputting pattern signals in response to the received mode signal; And Receiving a data pattern output from the memory block and a data pattern read from the memory block, comparing the data pattern with each other, and outputting a comparison result. The method of claim 8, Generating the pattern signal, Outputting a burn-in clock signal in response to the received mode signal; Counting and outputting an address based on the burn-in clock signal and a first selection signal, and outputting an MSB carry bit generated when the address is counted; And Outputting the first selection signal or the second selection signal based on the received mode signal, and generating the test pattern in response to the MSB carry bit. The method of claim 9, The first selection signal, In the dynamic burn-in mode, the signal selects which of the row address and column address should be addressed first. The second selection signal is, The test method of a memory device, which is a signal for selecting whether to write or read the test pattern in a scan mode.        The method of claim 8, The test method of the memory device, A test method of a memory device performed in a wafer state of the memory device.

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