KR20080053547A - Semiconductor memory device having reduced pads - Google Patents

Abstract

A semiconductor memory device having reduced pads is provided to reduce the restriction of the number of pads of the memory device, by connecting two pads used only in a wafer state and two pads used only in a package state. A common pad receives a first signal and a second signal in common. The first signal and the second signal have different usage time. A first path(PWBE) transfers the first signal inputted from the common pad to the inside of a chip. A second path(PX16) transfers the second signal inputted from the common pad to the inside of the chip. A level detection part(410) judges a first level or a second level according to usage state setting. A switching control part(420-450) enables the first path and disables the second path when the judgment result of the level detection part is the first level, and enables the second path and disables the first path when the judgment result is the second level.

Description

Semiconductor memory device with reduced number of pads {SEMICONDUCTOR MEMORY DEVICE HAVING REDUCED PADS}

1 is a circuit diagram showing the structure of a conventional wafer burn-in activation pad.

2 is a circuit diagram showing the structure of a conventional X16 bonding pad.

3 is a block diagram of a semiconductor memory device having a reduced number of pads according to an embodiment of the present invention.

4 is a circuit diagram illustrating a configuration of a semiconductor memory device having a reduced number of pads according to an embodiment of the present invention.

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device in which the number of pads is reduced by combining pads used in a wafer state and pads used in a package state.

Until the conventional semiconductor process, the required number of pads was a level that can be implemented regardless of the size of the chip. However, with the development of the process, as the chip becomes more compact, the size of the pad does not become much smaller than the size of the chip, making it difficult to implement the entire number of pads required for the chip design.

1 is a circuit diagram showing the structure of a conventional wafer burn-in activation pad.

The wafer burn-in activation pad WBE is a pad for a wafer burn-in test. When a logic high is input to the wafer burn-in activation pad WBE, a wafer burn-in test is performed. Signals applied through the wafer burn-in activation pad (WBE) from the outside are transferred into the chip through a plurality of inverting buffers.

The pad for testing the redundancy cell also has a structure similar to that of FIG. 1, and a test is performed when logic high is applied to the redundancy cell test pad. Redundant cell test pads are also used in wafer conditions.

2 is a circuit diagram showing the structure of a conventional X16 bonding pad.

The X16 bonding pad PDX16 is a pad for operating the memory in the X16 mode and is an option pad for inputting and outputting data from the memory in units of 16 bits instead of a single bit. When the X16 bonding pads are connected to ground voltages, the memory operates in X16 mode.

The signal applied to the X16 bonding pad PDX16 is logically combined with the other control signals MRSORG and MRSX16 and transferred to the chip PX16. The transistor block TRB holds a signal high when the X16 bonding pad PDX16 is not grounded.

The structure of the X4 bonding pads is also similar to FIG. The X4 bonding pad is a pad for operating the memory in X4 mode. It is an option pad that inputs and outputs data from the memory in 4-bit units instead of single bits. When the X4 bonding pads are connected to ground voltages, the memory operates in X4 mode. The X4 bonding pad and the X16 bonding pad are the pads that determine whether the chip will be operated in X4, X8, or X16 at the end of the package assembly. When neither the X16 bonding pad nor the X4 bonding pad is connected to the ground voltage, the memory Will run in X8 mode.

As described above, according to the related art, since the pads for testing the memory or determining the operation mode must be individually designed on the chip, the number of chips increases and the chip area occupies a lot.

The present invention has been proposed to reduce the number of pads of the conventional semiconductor memory device described above. In the present invention, two pads used only in a wafer state and two pads used only in a package state are respectively maintained while maintaining necessary pads. By combining with each other one by one to reduce the constraint on the number of pads of the memory device.

In order to achieve the above object, a semiconductor memory device according to an exemplary embodiment of the present invention may include a common pad capable of receiving a first signal and a second signal having different points of use in common, and the first pad received from the common pad. Determine a first level or a second level according to a first path for transmitting a first signal into the chip, a second path for transmitting the second signal input from the common pad into the chip, and a use state setting The level detector to activate the first path and deactivate the second path if the determination result of the level detector is the first level, and if the determination result is the second level, deactivate the second path. And a switching controller for activating and deactivating the first path.

The level detector may determine that the semiconductor memory device is in the first level when the semiconductor memory device is in a wafer state in a manufacturing process, and determine that the second level is in the package state.

The level detector may include an NMOS transistor having a source connected to a first power terminal, a PMOS transistor having a source connected to a second power terminal, and a gate connected to a gate of the NMOS transistor, and a drain of the NMOS transistor; And a fuse connected between the drains of the PMOS transistors, and determining whether the fuse is shorted according to the use state setting, and determining the first level or the second level according to whether the fuse is shorted. can do.

The first signal may be a signal for activating a wafer burn-in test or a signal for activating a redundancy cell test.

The second signal may determine whether to operate in X4 mode or whether to operate in X16 mode according to whether the first power terminal is in contact with the first power terminal.

The switching control unit deactivates the second path at the first level, and activates the second path at the second level, and activates the first path at the first level. And a second MOS transistor for deactivating the first path when the second level is present, and a logic gate for controlling only one of the first path and the second path to be activated according to an output of the level detector. can do.

Hereinafter, an electrostatic discharge protection circuit according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a semiconductor memory device having a reduced number of pads according to an embodiment of the present invention.

Referring to FIG. 3, two conventional circuits shown in FIGS. 1 and 2 may be connected to one pad. According to the present invention, two pads are shared as one outside the conventional chip and include a first path PA1 and a second path PA2 connected to the common pad CPAD to transmit a signal into the chip. .

The level detection unit 310 transmits a detection signal to the switching control unit 320 by distinguishing a point in time of use of the signal, and the switching control unit 320 responds to the detection signal of the level detection unit 310, thereby applying a common pad CPAD. It is connected to any one of the first path PA1 and the second path PA2. The signal applied to the common pad CPAD is transferred into the chip only through a path activated by the switching controller 320.

4 is a circuit diagram illustrating a configuration of a semiconductor memory device having a reduced number of pads according to an embodiment of the present invention.

Referring to FIG. 4, a semiconductor memory device having a reduced number of pads according to an embodiment of the present invention may include a common pad CPAD, a first path PWBE, a second path PX16, and a level detector connected to the common pad. 410 and the switching control unit (420 ~ 450).

In one embodiment of the present invention, a wafer burn-in activation pad (WBE) used only in a wafer state and an X16 bonding pad used only in a package state are used as a common pad. Through the common pad, a signal used only in the wafer state and a signal used only in the package state may be input in common. Wafer burn-in activation pads (WBEs) are for wafer burn-in testing. In the waiter burn-in test, the memory is operated in harsh conditions such as high temperature and high voltage to expose potential defects in a short time. A wafer burn-in test is performed when logic high is input to the wafer burn-in activation pad (WBE). The X16 bonding pad PDX16 is a pad for operating the memory in the X16 mode and is an option pad for inputting and outputting data from the memory in units of 16 bits instead of a single bit. When the X16 bonding pad PDX16 is bonded to the ground terminal VSS, the memory operates in the X16 mode, and thus the data input / output unit is 16 bits.

Since the wafer burn-in activation pad (WBE) and the X16 bonding pad (PDX16) do not need to be used at the same time, they combine the two into one pad, and through these common pads, two different paths for transferring the applied signals inside the chip. It includes. The first is the first path (PDX16_WBE to PWBE) from the common pad (PDX16_WBE) to the inside of the chip to deliver the wafer burn-in activation signal into the chip, and the second is to deliver the X16 mode activation signal into the chip. The second path PDX16_WBE to PX16 from the common pad PDX16_WBE to the inside of the chip.

Since the common pad PDX16_WBE is used outside the chip, the level detector 410 and the switching controllers 420 to 450 are determined to determine whether to transfer the signal applied to the first path and the second path. Include.

The level detector may include an inverter for inverting the initial signal PVCCHB having a logic low value. The initial signal PVCCHB is a signal that initially maintains a logic high and moves to a logic low when a power applied to the chip passes a specific voltage. The inverter may be implemented as a PMOS transistor and an NMOS transistor, and a fuse is connected between the drain of the PMOS transistor and the drain of the NMOS transistor, and the inverted signal of the initial signal PVCCHB at the drain of the NMOS transistor is a level signal. Output to (WLVL). When outputting the inverted signal of the initial signal PVCCHB as the level signal WLVL, the inverter may be inverted or amplified using an inverter, a transistor, or the like.

In the wafer state, the fuse is held as it is, and the logic high value obtained by inverting the initial signal PVCCHB of the logic low is output to the inverter, and this value becomes the level signal WLVL.

If the fuse connected between the PMOS transistor and the NMOS transistor is shorted when the memory device is in a packaged state, the current passing through the PMOS transistor cannot pass to the inverter, and thus the level detection unit is set to logic low regardless of the initial signal PVCCHB. Is output as a level signal WLVL. As a result, it is possible to distinguish whether the memory device is in a wafer state or a package state depending on whether the fuse included in the level detector is shorted.

The switching controller includes a wafer control transistor 420, a package control transistor 430, a wafer NAND gate 440, and a package NOR gate 450.

The wafer control transistor 420 receives the level signal WLVL of the level detector 410, and when the level signal WLVL is logic high, turns on the NMOS transistor to activate the first path, and the level signal WLVL is logic. If low, the NMOS transistor is turned off to deactivate the first path.

The package control transistor 430 also receives the level signal WLVL like the wafer control transistor 420. When the level signal WLVL is logic high, the PMOS transistor is turned off to deactivate the second path for operating in X16 mode. When the level signal WLVL is logic low, the PMOS transistor is turned on. Make it active. The wafer NAND gate 440 and the package NOR gate 450 receive the level signal WLVL to activate only one of the first path and the second path and prevent both paths from being activated at the same time.

In this way, in the wafer state, the fuse included in the level detector is not cut and the level signal WLVL is logic high so that the first path is activated and the control signal input to the common pad PDX16_WBE is When the manufacturing process is transferred to the progress door package state, the fuse is included in the level detector to cut the fuse so that the level signal WLVL has a logic low, and the second path is activated. The control signal input to the PDX16_WBE may be transferred into the chip through the second path.

In addition, since the redundancy cell test pad used in the wafer state and the X4 bonding pad used in the package state can also be shared using the above-described structure, redundant description will be omitted.

In the semiconductor memory device according to the embodiment of the present invention, the pads used only in the wafer state and the pads used only in the package state can be shared so that two pads can be implemented by using two pads. The number of pads due to the miniaturization of the chip can be reduced.

Claims (8)

A common pad capable of receiving a first signal and a second signal having different points of use in common; A first path transferring the first signal received from the common pad into the chip; A second path transferring the second signal received from the common pad into the chip; A level detector determining a first level or a second level according to a use state setting; And If the determination result of the level detector is the first level, the first path is activated and the second path is deactivated. If the determination result is the second level, the second path is activated, and the second path is activated. And a switching controller to deactivate one path. The method of claim 1, wherein the level detector determines that the semiconductor memory device is in the first level when the semiconductor memory device is in a wafer state in a manufacturing process, and determines that the second level is in the package state. Semiconductor memory device. The method of claim 1, wherein the level detector An NMOS transistor whose source is connected to a first power terminal; A PMOS transistor having a source connected to the second power supply terminal and a gate connected to the gate of the NMOS transistor; And A fuse connected between the drain of the NMOS transistor and the drain of the PMOS transistor, And determining whether the fuse is shorted according to the use state setting, and determining the first level or the second level according to whether the fuse is shorted. The semiconductor memory device of claim 1, wherein the first signal activates a wafer burn-in test. The semiconductor memory device of claim 1, wherein the first signal activates a redundancy cell test. The semiconductor memory device of claim 1, wherein the second signal determines whether to operate in X4 mode according to whether the second signal is in contact with the first power supply terminal. The semiconductor memory device of claim 1, wherein the second signal determines whether to operate in X16 mode according to whether the second signal is in contact with the first power supply terminal. The method of claim 1, wherein the switching control unit A first MOS transistor configured to deactivate the second path when the determination result of the level detector is the first level, and activate the second path when the second level is determined; A second MOS transistor activating the first path when the determination result of the level detector is the first level, and deactivating the first path when the second level is determined; And And a logic gate for controlling only one of the first path and the second path to be activated according to a determination result of the level detector.

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