KR20080050049A - Liquid crystal display panel - Google Patents

Abstract

An LCD(Liquid Crystal Display) panel is provided to arrange a column spacer such that the column spacer corresponds to a storage electrode to prevent the column spacer from being moved caused by external impact to prevent light leakage. An LCD panel(500) includes lines(GL) defining pixel regions of a base substrate(110), a storage electrode(STE) independent from the lines and formed in each of the pixel regions, and an organic layer formed on the base substrate including the lines and the storage electrode. The organic layer has a hole corresponding to the storage electrode. The LCD panel further includes an array substrate(100) having a pixel electrode layer(PE) formed on the organic layer, a counter substrate(200) combined with the array substrate, and a column spacer(410) interposed between the array substrate and the counter substrate and arranged corresponding to the hole of the organic layer. A liquid crystal layer(300) is interposed between the array substrate and the counter substrate. The counter substrate includes color filters(CF) respectively corresponding to the pixel regions.

Description

Liquid Crystal Display Panel {LIQUID CRYSTAL DISPLAY PANEL}

1 is a plan view of a liquid crystal display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

3 is a plan view of a liquid crystal display panel according to another exemplary embodiment of the present invention.

4 is a cross-sectional view taken along the line II-II 'of FIG. 3.

<Explanation of symbols for the main parts of the drawings>

500, 502: first and second liquid crystal display panels STE: storage electrode

Cst: storage 140: passivation layer

150: organic layer 152: hole

PE: pixel electrode layer 410: first column spacer

420a: second column spacer 420b: third column spacer

The present invention relates to a liquid crystal display panel, and more particularly to a liquid crystal display panel that can improve the reliability and display quality of the product.

In general, the liquid crystal display panel includes an array substrate on which switching elements are formed, a color filter substrate facing the array substrate and including color filters, and a liquid crystal layer interposed between the array substrate and the color filter substrate.

Spacers are formed between the array substrate and the color filter substrate to maintain a constant gap between the array substrate and the color filter, that is, a cell gap of the liquid crystal layer. The spacer is required to maintain a margin of the liquid crystal injection process and a cell gap of the liquid crystal layer of the liquid crystal display panel even under external pressure.

The column spacer may be formed on any one of the array substrate and the color filter substrate, and may be disposed between the array substrate and the color filter substrate by combining the array substrate and the color filter substrate. The column spacer is formed in a columnar shape on a light blocking region of the liquid crystal display panel, for example, a region corresponding to the wirings and the switching elements.

The column spacer is stably disposed between the array substrate and the color filter to maintain a constant cell gap of the liquid crystal layer. Stabilization of the column spacer and maintenance of the cell gap are essential to remove external factors affecting the behavior of liquid crystal molecules in the liquid crystal layer.

However, since the column spacer is generally formed corresponding to the gate wiring of the array substrate, the column spacer is unstable because the width of the gate wiring is smaller than the width of the column spacer. In order to improve this, the column spacer may be formed over the gate line and the common voltage line adjacent to the gate line, but there is a limit in stably arranging the column spacer.

Accordingly, the technical problem of the present invention was conceived in this respect, and an object of the present invention is to provide a liquid crystal display panel which prevents light leakage and improves reliability and display quality of a product.

According to an exemplary embodiment of the present invention, a liquid crystal display panel may include wirings for partitioning a pixel area of a base substrate, a storage electrode formed in the pixel area independently of the wirings, the wirings, and the An organic layer including a hole formed on the base substrate including a storage electrode and corresponding to the storage electrode, an array substrate including a pixel electrode layer formed on the organic layer, and a liquid crystal layer interposed with the array substrate; And an opposing substrate including a color filter formed corresponding to the pixel region, and a column spacer interposed between the array substrate and the opposing substrate to correspond to the holes of the organic layer of the array substrate.

According to the liquid crystal display panel, the column spacer is stably positioned on the storage electrode, which is a flat region of the pixel region, thereby minimizing the movement of the column spacer due to an external shock and minimizing an external impact. By preventing light leakage, the product's reliability and display quality can be improved.

Hereinafter, with reference to the accompanying drawings, it will be described in detail preferred embodiments of the present invention.

1 is a plan view of a liquid crystal display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

1 and 2, the first liquid crystal display panel 500 includes an array substrate 100, an opposite substrate 200 facing the array substrate 100, the array substrate 100, and the opposite surface. The liquid crystal layer 300 is interposed between the substrate 200 and the first column spacer 410 disposed between the array substrate 100 and the opposing substrate 200.

The array substrate 100 includes a pixel area P defined by the gate line GL and the source line DL formed on the first base substrate 110. In the pixel region P, a switching element TFT connected to the gate line GL and the source line DL, a storage electrode STE, and a pixel electrode layer PE electrically connected to the switching element TFT. ).

The gate lines GL extend in a first direction, and a plurality of gate lines GL are arranged in parallel in a second direction perpendicular to the first direction. The source wiring DL extends in the second direction, and a plurality of the source lines DL are arranged in parallel in the first direction. The gate line GL and the source line DL intersect to partition the pixel area P. As shown in FIG.

The switching element TFT may include a gate electrode GE connected to the gate line GL, a source electrode SE formed on the gate electrode GE, and connected to the source line DL, and the gate electrode. And a drain electrode DE formed on the GE and spaced apart from the source electrode SE by a predetermined distance. One end of the drain electrode DE contacts the pixel electrode layer PE so that the switching element TFT is electrically connected to the pixel electrode layer PE. The semiconductor pattern 130 is formed between the gate electrode GE, the source electrode SE, and the drain electrode DE to correspond to the gate electrode GE of the switching element TFT. The semiconductor pattern 130 includes a semiconductor layer 132 and an ohmic contact layer 134 sequentially stacked.

The storage electrode STE is formed in each pixel area P, and the storage electrodes STE formed in the pixel area P adjacent to each other extend in the first direction in parallel with the gate line GL. It is connected by connecting wiring. The storage electrode STE and the connection line are formed of the same gate metal layer as the gate line GL. The connection line is formed to cross the source line DL.

The storage electrode STE is formed to have a relatively large area in a predetermined area of the pixel area P so as not to overlap the gate line GL and the source line DL. The area of the storage electrode STE is proportional to the capacitance stored in the storage unit Cst including the storage electrode STE. The storage electrode STE is formed to extend in the first direction, for example, at a central portion of the pixel area P, and to have a predetermined width in the second direction.

A gate insulating layer 120 is formed on the first base substrate 110 including the gate line GL, the gate electrode GE of the switching element TFT, and the storage electrode STE. The source wiring DL, the source electrode SE of the switching element TFT, and the drain electrode DE are formed on the gate insulating layer 120. The passivation layer 140, the organic layer 150, and the pixel electrode layer PE are disposed on the first base substrate 110 including the source wiring DL, the source electrode SE, and the drain electrode DE. These are stacked sequentially. The passivation layer 140 and the organic layer 150 formed on one end of the drain electrode DE of the switching element TFT are removed to form a contact hole CNT, and the contact hole CNT is formed. The switching element TFT and the pixel electrode layer PE are in contact with each other and electrically connected to each other.

The organic layer 150 includes a hole 152 that exposes the passivation layer 140 formed on the storage electrode STE to correspond to the storage electrode STE. The hole 152 of the organic layer 150 is formed by removing the organic layer 150 corresponding to the storage unit Cst in order to optimize the electric capacity stored in the storage unit Cst.

The storage unit Cst uses the storage electrode STE formed of the gate metal layer as one electrode, the pixel electrode layer PE formed in the pixel region P as another electrode, and the one electrode and the other electrode. Voltage is charged in the gate insulating layer 120 and the passivation layer 140 formed between the electrodes. Since the capacitance stored in the storage unit Cst is inversely proportional to the thickness between the one electrode and the other electrode of the storage unit Cst, the hole 152 of the organic layer 150 is connected to the storage unit Cst. It is formed in the to increase the electric capacity of the storage unit (Cst).

The opposing substrate 200 faces the array substrate 100, and includes the light blocking pattern BM, the color filters CF, the overcoating layer 220, and the common electrode layer CE formed on the second base substrate 210. ).

The light blocking pattern BM partitions the pixel region P of the second base substrate 210 to correspond to the gate line GL and the source line DL, and corresponds to the switching element. It prevents leakage current from occurring by blocking external light entering the device.

Each color filter CF is formed in the pixel region P that is partitioned by the light blocking pattern BM. The color filters CF include, for example, a red color filter CF, a green color filter CF, and a blue color filter CF representing red, green, and blue colors. Various colors are represented by a combination of the colors of the red, green, and blue color filters CF.

The overcoat layer 220 is formed on the second base substrate 210 including the light blocking pattern BM and the color filters CF. The overcoat layer 220 may be omitted in some cases.

The common electrode layer CE is formed on the second base substrate 210 including the light blocking pattern BM and the color filters CF. The common electrode layer CE receives a common voltage from the pixel electrode layer PE to face the pixel electrode layer PE.

The liquid crystal layer 300 is interposed between the array substrate 100 and the counter substrate 200, and includes a plurality of liquid crystal molecules (not shown). When a voltage is applied to the first liquid crystal display panel 500, an electric field is formed between the pixel electrode layer PE of the array substrate 100 and the common electrode layer CE of the opposing substrate 200. The liquid crystal molecules behave by an electric field to display an image. The liquid crystal layer 300 is a twisted nematic (TN) mode. For example, the backlight passes through a white state when no voltage is applied and implements black by blocking the backlight when the voltage is applied. The image is displayed by Mali white driving.

In the TN mode of the normally white driving, the column spacers disposed between the upper and lower substrates are moved by an impact applied to the liquid crystal display panel from the outside in the black state, and light leakage is generated by the movement of the column spacers. The column spacer is a cell gap retaining member for maintaining a constant distance between the upper and lower substrates. The light leakage phenomenon of the liquid crystal display panel is caused by various causes, and the light leakage caused by the external impact is called tapping light leakage phenomenon. The column spacer is generally formed to correspond to a pattern formed of a metal layer, and the patterns have a smaller area than the column spacer. Accordingly, the column spacer is unstable and easily moved by the impact, and there is a difficulty in returning to the original position.

The first column spacer 410 of the first liquid crystal display panel 500 according to the present invention for solving the above problems is disposed between the array substrate 100 and the opposing substrate 200, the array The substrate 100 is disposed corresponding to the storage part Cst. The storage unit Cst occupies a relatively large area by the storage electrode STE among the various portions of the pixel region P of the array substrate 100 and corresponds to a planarization region having no step. The first column spacer 410 is disposed corresponding to the hole of the organic layer formed on the storage electrode STE.

Since the first column spacer 410 is disposed on the storage electrode STE, which is a planarization region, movement of the first column spacer 410 is minimized even when the first column spacer 410 is impacted from the outside of the first liquid crystal display panel 500. can do. That is, even if the first column spacer 410 is moved to some extent at the moment when the impact is applied to the first liquid crystal display panel 500, the first column spacer 410 is originally returned to the first column spacer 410 after the impact is applied. Easily return to the area where the column spacer 410 was formed. Accordingly, the tapping light leakage phenomenon due to the movement of the first column spacer 410 can be prevented, and display quality can be improved.

The first column spacer 410 is formed on any one of the array substrate 100 and the opposing substrate 200 to bond the array substrate 100 and the opposing substrate 200 to the array substrate 100. And the opposing substrate 200. For example, the first column spacer 410 is formed on the common electrode layer CE of the counter substrate 200. The first column spacer 410 is formed by forming a photo layer made of a photosensitive organic material on the common electrode layer CE and patterning the photo layer.

3 is a plan view of a liquid crystal display panel according to another exemplary embodiment of the present invention.

4 is a cross-sectional view taken along the line II-II 'of FIG. 3.

The second liquid crystal display panel shown in FIGS. 3 and 4 has a structure similar to that of the first liquid crystal display panel. Hereinafter, the same components as those of the first liquid crystal display panel will be referred to by the same reference numerals, and the same reference numerals will be used to describe the components similar to those of the first liquid crystal display panel. A different portion from the first liquid crystal display panel will be described in detail.

3 and 4, the second liquid crystal display panel 502 includes an array substrate 100, a counter substrate 200, a liquid crystal layer 300, the array substrate 100 and the counter substrate ( Second and third column spacers 420a and 420b disposed between 200.

The array substrate 100 is formed to cross each other, and is formed in the gate line GL and the source line DL to define the pixel region P of the first base substrate 110, and the pixel region P. A switching element TFT connected to the gate line GL and the source line DL, and a storage electrode formed in the pixel area P and formed independently of the gate line GL and the source line DL, STE) and the pixel electrode layer PE formed in the pixel region P and electrically connected to the switching element TFT.

In the pixel region P, a gate insulating layer 120 formed on the gate line GL and a gate electrode GE of the switching element TFT, and the source wiring formed on the gate insulating layer 120 The passivation layer 140 and the organic layer 150 that are sequentially stacked on the DL and the source electrode SE and the drain electrode DE of the switching element TFT are formed.

The organic layer 150 includes a hole 152 that exposes the passivation layer 140 formed on the storage electrode STE to correspond to the storage electrode STE. The capacitance of the storage unit Cst may be increased by forming the hole 152 in the organic layer 150 on the storage electrode STE.

The opposing substrate 200 may include a light shielding pattern BM that partitions the pixel region P of the second base substrate, a color filter CF formed in the pixel region P, the light shielding pattern BM, and an image. The overcoat layer 220 formed on the color filter CF and the common electrode layer CE formed on the overcoat layer 220 are included.

The liquid crystal layer 300 is interposed between the array substrate 100 and the opposing substrate 200, and the liquid crystal layer 300 is driven in normally white in TN mode.

The second and third column spacers 420a and 420b are disposed between the array substrate 100 and the opposing substrate 200, and the holes 152 of the organic layer 150 of the array substrate 100 are disposed. It is arranged in correspondence with. A stepped portion in which the passivation layer 140 and the organic layer 150 defining an outer periphery of the hole 152 are formed on the storage electrode STE by the hole 152 of the organic layer 150. 154 is formed. The second and third column spacers 420a and 420b are disposed adjacent to the stepped portion 154. When the hole 152 of the organic layer 150 has a square shape, the second column spacer 420a is disposed adjacent to one side of the square shape, and the third column spacer 420b faces the one side. The second column spacer 420a may be disposed to be adjacent to another side thereof.

Even when an impact is applied from the outside of the second liquid crystal display panel 502, the second and third column spacers 420a and 420b are stably disposed on the storage electrode STE, which is a planarization region, so that the second and third After the three column spacers 420a and 420b are moved by the impact, the three column spacers 420a and 420b can be easily returned to the area where the second and third spacers 420a and 420b are originally disposed. In addition, the second and third column spacers 420a and 420b are disposed adjacent to the stepped portion 154, respectively, thereby preventing the movement of the second and third column spacers 420a and 420b due to the impact. do. For example, when an impact is applied to the right side of the second and third column spacers 420a and 420b based on the second and third column spacers 420a and 420b of FIG. 4, the second column spacer Since 420a may not move beyond the stepped portion 154, the second column spacer 420a is restricted from moving to the right. At the same time, the third column spacer 420b is restricted from moving to the right by the second column spacer 420a. On the other hand, even when an impact is applied from the left side opposite to the right side, the movement of the second column spacer 420a is also restricted as the third column spacer 420b is restricted from moving to the left side.

In the second liquid crystal display panel 502, two second and third column spacers 420a and 420b are disposed in the hole 152 on the storage electrode STE. Accordingly, a plurality of column spacers may be disposed along the stepped portion 154 of the hole 152. The number of the column spacers is inversely proportional to the liquid crystal injection margin when the liquid crystal material is injected between the array substrate 100 and the counter substrate 200 to determine the number of column spacers in consideration of the liquid crystal injection margin. have.

According to the liquid crystal display panel, the column spacer is disposed to correspond to the storage electrode which is the planarization region of the liquid crystal display panel, thereby preventing the movement of the column spacer due to an external impact, and the column spacer is to some extent. Even if it moves, it can easily be returned to its original position after the impact is applied. Accordingly, tapping light leakage due to the movement of the column spacer may be prevented to improve product reliability and display quality of the liquid crystal display panel.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (7)

Wires defining a pixel area of the base substrate, a storage electrode formed in the pixel area independent of the wires, and the wires and the storage electrode formed on the base substrate including the storage electrode and corresponding to the storage electrode. An array substrate including an organic layer including formed holes and a pixel electrode layer formed on the organic layer; An opposing substrate coupled to the array substrate to interpose a liquid crystal layer and including a color filter formed corresponding to the pixel region; And And a column spacer interposed between the array substrate and the opposing substrate and disposed to correspond to the holes of the organic layer of the array substrate. The method of claim 1, wherein the array substrate is And a passivation layer formed on the base substrate including the storage electrode and formed under the organic layer. The liquid crystal display panel of claim 2, wherein a plurality of column spacers is disposed in the hole of the organic layer. The method of claim 3, wherein the column spacers And a step portion adjacent to a step portion formed by the organic layer and the passivation layer defining an outer portion of the hole. The method of claim 2, wherein the array substrate is Further comprising a gate insulating layer formed on the lower portion of the passivation layer, And a storage electrode formed of the same gate metal layer as the gate wiring under the gate insulating layer. The liquid crystal display panel of claim 1, wherein the opposing substrate comprises a light shielding pattern formed to correspond to the wirings to partition pixel regions. The liquid crystal display panel of claim 1, wherein the column spacer is formed on the opposing substrate.

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