KR20080047081A - Liquid crystal display and driving method thereof - Google Patents

Abstract

An LCD device and a driving method thereof are provided to enhance display quality by rapidly processing the response speed of a liquid crystal. An LCD(Liquid Crystal Display) device includes an image analyzer(81), an encoder(82), a memory(83), decoders(84A,84B), a look-up table(85), and a driver. The image analyzer analyzes information amounts of source digital video data and selects one of compress/recovery schemes according to the analyzed information amounts. The encoder compresses the source digital video data according to the selected compress scheme. The memory stores the data compressed by the encoder. The decoders recover the compressed data from the encoder and the memory according to the selected compress scheme. The look-up table compares recovery data of previous with current frames supplied from the decoders, and selects modulation data according to the comparison result. The driver displays the modulation data selected by the look-up table on an LCD panel.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD THEREOF}

1 is a waveform diagram showing a change in luminance in accordance with data in a conventional liquid crystal display device.

2 is a waveform diagram showing an example of a luminance change caused by data modulation in an ODC.

3 shows an example of an ODC circuit;

4 is a view showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 5 is a diagram showing an example of a block-by-block histogram created by a modulator shown in FIG. 4; FIG.

6 is a diagram illustrating a compression / restore algorithm of BTC (Block Truncation Coding) and an example thereof.

7 illustrates a compression / restore algorithm of compressed over-driving (COD).

FIG. 8 is a circuit diagram illustrating in detail a modulator shown in FIG. 4. FIG.

9 and 10 show examples of selection signals added in front of a source digital video data stream.

11 is a flowchart showing step by step a control procedure of a method of driving a liquid crystal display device according to an embodiment of the present invention;

<Description of Symbols for Main Parts of Drawings>

41: timing controller 42: modulator

43: data driver 44: gate driver

45: data line 46: gate line

47: liquid crystal display panel 81: image analysis unit

82: encoder 83: memory

84A, 84B: Decoder 85: Lookup Table

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof for reducing the number of frame memories.

Liquid crystal displays display an image by adjusting light transmittance of liquid crystal cells according to a video signal.

Among the liquid crystal display devices, an active matrix type liquid crystal display device in which switching elements are formed for each liquid crystal cell is advantageous in implementing a moving image because active control of the switching element is possible. As a switching element used in an active matrix type liquid crystal display device, a thin film transistor (hereinafter, referred to as TFT) is mainly used.

As the liquid crystal display device can be seen in Equations 1 and 2, the response speed is slow due to the inherent viscosity and elasticity of the liquid crystal.

(gamma)는 액정분자의 회전점도(rotational viscosity)를 각각 의미한다. Where τr is the rising time when voltage is applied to the liquid crystal, Va is the applied voltage, VF is the Freederick Transition Voltage at which the liquid crystal molecules start the tilt motion, and d is the liquid crystal. The cell gap of the cell,

(gamma) means rotational viscosity of liquid crystal molecules, respectively.

Here, τf denotes a falling time during which the liquid crystal is restored to its original position by the elastic restoring force after the voltage applied to the liquid crystal is turned off, and K denotes an elastic modulus inherent to the liquid crystal.

The liquid crystal response speed of TN mode (Twisted Nematic mode), which has been the most commonly used liquid crystal display device, can vary depending on the material properties and cell gap of the liquid crystal material. This is 20-30ms. The response speed of the liquid crystal is longer than one frame period (NTSC: 16.67ms). For this reason, as shown in FIG. 1, since the voltage charged in the liquid crystal cell reaches the next voltage, the motion blurring phenomenon occurs in which the screen is blurred in the video.

Referring to FIG. 1, in the conventional LCD, when the data VD changes from one level to another level due to a slow response speed, the corresponding display luminance BL does not reach the desired luminance. Will not be represented. As a result, the motion blurring phenomenon appears in the moving image, and the image quality is deteriorated due to the decrease in the contrast ratio.

In order to solve the slow response speed of the liquid crystal display device, U.S. Patent No. 5,495,265 and PCT International Publication No. WO 99/05567 use a lookup table to modulate the data according to whether or not the data is changed (hereinafter, 'ODC ( "Over driving control" has been proposed. The ODC modulates data on the same principle as in FIG. 2.

을 크게 하게 된다. 따라서, ODC로 구동되는 액정표시소자는 액정의 늦은 응답속도를 데이터값의 변조로 보상하여 동영상에서 모션 블러링 현상을 완화시킨다. Referring to FIG. 2, the ODC modulates an input data voltage VD into a voltage MVD of preset modulation data and applies a voltage MVD of the modulation data to the liquid crystal cell to obtain a desired luminance MBL. The ODC is expressed by Equation 1 based on the change of data so as to obtain a desired luminance (MBL) within one frame period.

To make it larger. Therefore, the liquid crystal display device driven by the ODC compensates for the late response speed of the liquid crystal by modulating the data value to mitigate the motion blur phenomenon in the video.

As a result, the ODC compares the data between the previous frame and the current frame and, if there is a change between the data, modulates the data of the current frame with the preset modulation data.

3 is a block diagram schematically illustrating an ODC circuit.

Referring to FIG. 3, the ODC circuit includes first and second frame memories 33a and 33b for storing data from the data bus 32 and a lookup table 34 for modulating the data.

The first and second frame memories 33a and 33b alternately store data in units of frames in accordance with the pixel clock, alternately output the stored data, and output the previous frame data, that is, the n-1 th frame data, to the lookup table 34. (Fn-1) is supplied.

The lookup table 34 stores n-th frame data Fn from the n-th frame data Fn and the first and second frame memories 33a and 33b as shown in Table 1 below. Is selected as an address to modulate the data. This lookup table 34 includes a read only memory (ROM) and a memory address control circuit.

division 0 One 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 2 3 4 5 6 7 9 10 12 13 14 15 15 15 15 One 0 One 3 4 5 6 7 8 10 12 13 14 15 15 15 15 2 0 0 2 4 5 6 7 8 10 12 13 14 15 15 15 15 3 0 0 One 3 5 6 7 8 10 11 13 14 15 15 15 15 4 0 0 One 3 4 6 7 8 9 11 12 13 14 15 15 15 5 0 0 One 2 3 5 7 8 9 11 12 13 14 15 15 15 6 0 0 One 2 3 4 6 8 9 10 12 13 14 15 15 15 7 0 0 One 2 3 4 5 7 9 10 11 13 14 15 15 15 8 0 0 One 2 3 4 5 6 8 10 11 12 14 15 15 15 9 0 0 One 2 3 4 5 6 7 9 11 12 13 14 15 15 10 0 0 One 2 3 4 5 6 7 8 10 12 13 14 15 15 11 0 0 One 2 3 4 5 6 7 8 9 11 13 14 15 15 12 0 0 One 2 3 4 5 6 7 8 9 10 12 14 15 15 13 0 0 One 2 3 3 4 5 6 7 8 10 11 13 15 15 14 0 0 One 2 3 3 4 5 6 7 8 9 11 12 14 15 15 0 0 0 One 2 3 3 4 5 6 7 8 9 11 13 15

In Table 1, the leftmost column is data of the previous frame Fn-1, and the uppermost row is data of the current frame Fn.

During the nth frame period, the nth frame data Fn is stored in the first frame memory 33a and supplied to the lookup table 34 at the same pixel clock as indicated by the solid line. At the same time, the second frame memory 33b supplies the n−1 th frame data Fn−1 to the lookup table 34 during the n th frame period.

In contrast, during the n + 1 th frame period, the current n + 1 th frame data Fn + 1 is stored in the second frame memory 33b at the same time as the dotted pixel clock, and the lookup table 34 Is supplied. At the same time, the first frame memory 33b supplies the nth frame data Fn to the lookup table 34 during the n + 1th frame period.

As such, the ODC circuit requires two frame memories 33a and 33b to alternately supply previous frame data to the lookup table 34. Since the frame memory acts as a factor to increase the circuit cost, there is an urgent need for a method of reducing the number and the memory capacity of the frame memory.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a method of driving the same, which increase the display quality by reducing the response speed of the liquid crystal and reduce the memory capacity required for the ODC circuit.

In order to achieve the above object, the liquid crystal display according to the embodiment of the present invention analyzes the information amount of the source digital video data in predetermined block units and selects one of a plurality of compression / restore methods according to the analyzed information amount. An image analyzer; An encoder for compressing the source digital video data according to a compression method selected by the image analyzer; A memory for storing data compressed by the encoder; A decoder for reconstructing the compressed data delayed by the memory and the compressed data supplied from the encoder according to the reconstruction method selected by the image analyzer; A lookup table for comparing the reconstruction data of the previous frame and the reconstruction data of the current frame supplied from the decoder and selecting modulation data according to the comparison result; And a driving unit which displays the modulation data selected by the lookup table on the liquid crystal display panel.

The image analyzer generates a histogram of the source digital video data in units of blocks, and analyzes the amount of information based on the analysis of the histogram.

The image analyzing unit selects a first compression method having a high compression ratio when the variance value of the histogram is smaller than a predetermined reference value. 2 Select a compression method.

The first compression scheme is Block Truncation Coding (BTC), and the second compression scheme is Compressed Over-Driving (COD).

The image analyzer generates a selection signal indicating any one of the plurality of compression / restore schemes according to the information amount, and adds the selection signal to the encoder and the decoder in front of the source digital video data of one block. The encoder and the decoder select a compression / restore scheme according to the selection signal.

The modulation data of the lookup table is determined to be a value that accelerates the response characteristic of the liquid crystal.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method comprising: analyzing information amounts of input digital video data received in predetermined block units; Selecting any one of a plurality of compression / restore methods according to the analyzed information amount; Compressing the source digital video data according to the selected compression scheme; Storing the compressed data in a memory; Restoring each of the compressed data delayed by the memory and the compressed data supplied from the encoder according to the selected restoration scheme; Comparing the reconstructed data of the previous frame with the reconstructed data of the current frame and selecting modulation data according to the comparison result; And displaying the selected modulation data on a liquid crystal display panel.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 11.

Referring to FIG. 4, in the liquid crystal display according to the exemplary embodiment of the present invention, a liquid crystal display panel in which a data line 45 and a gate line 46 cross each other and a TFT for driving the liquid crystal cell Clc is formed at an intersection thereof. A data driver 43 for supplying the modulated digital video data MRGB to the data line 45 of the liquid crystal display panel 47 and the gate line 46 of the liquid crystal display panel 47. A gate driver 44 for supplying scan pulses, a modulator 42 for modulating the source digital video data SRGB subjected to compression and reconstruction into preset modulation data MRGB, a data driver 43, A timing controller 41 is provided to control the gate driver 44 and to supply source digital video data SRGB to the modulator 42.

In the liquid crystal display panel 47, liquid crystal is injected between two glass substrates, and the data lines 45 and the gate lines 46 are orthogonal to each other on the lower glass substrate. A TFT formed at the intersection of the data lines 45 and the gate lines 46 supplies the data from the data lines 45 to the liquid crystal cell Clc in response to a scan pulse from the gate line 46. do. For this purpose, the gate electrode of the TFT is connected to the gate line 46 and the source electrode is connected to the data line 45. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. In addition, a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 47 to maintain the voltage of the liquid crystal cell Clc. The storage capacitor Cst may be formed between the liquid crystal cell Clc and the front gate line 46 and may be formed between the liquid crystal cell Clc and a separate common line.

The timing controller 41 controls the gate control signal GDC and the data driver 43 to control the gate driver 44 using the vertical / horizontal synchronization signals V and H and the pixel clock CLK. A control signal for controlling the data control signal DDC and the modulator 42 is generated. The timing controller 41 samples the source digital video data SRGB in accordance with the pixel clock CLK, supplies the data SRGB to the modulator 42, and modulates the digital video modulated by the modulator 42. The data MRGB is supplied to the data driver 43.

The modulator 42 blocks the source digital video data SRGB input from the timing controller 41 into blocks, such as 2 × 2, 2 × 4, 4 × 4, and the like. The amount of information of the source digital video data SRGB is calculated, a compression method is selected according to the information amount, the source digital video data SRGB is compressed by the compression method, and the data stream for each block is compressed. The compression method selectable by the modulator 42 may be any known compression method. The modulator 42 stores the compressed source digital video data SRGB in the memory of the ODC. According to a comparison result between the source digital video data SRGB of the previous frame delayed by the memory and the source digital video data SRGB of the current frame which is not delayed, the modulator 42 satisfies Equations 3 to 5 as follows. The ODC algorithm modulates the source digital video data (SRGB).

Fn (RGB) <Fn-1 (RGB) ---> Fn (MRGB) <Fn (RGB)

Fn (RGB) = Fn-1 (RGB) ---> Fn (MRGB) = Fn (RGB)

Fn (RGB)> Fn-1 (RGB) ---> Fn (MRGB)> Fn (RGB)

As can be seen from Equations 3 to 5, the modulated digital video data MRGB has the current frame Fn if the pixel data value of the same pixel is larger in the current frame Fn than in the previous frame Fn-1. On the other hand, a smaller value in the current frame Fn than the previous frame Fn-1 is smaller than the current frame Fn. The modulation data MRGB has the same value as the current frame Fn if the pixel data value of the same pixel is the same in the previous frame Fn-1 and the current frame Fn.

이면 압축율이 높은 압축방식 예를 들면, BTC(Block Truncation Coding)으로 소스 디지털 비디오 데이터(SRGB)를 압축한다. 여기서,

는 블록 내의 소스 디지털 비디오 데이터들(SRGB)이 히스토그램(Hist[])에서 어느 계조범위 내에 집중되어 정보양이 작다는 것을 의미한다. 이에 비하여, 변조부(42)는 히스토그램(Hist[])의 표준 분산값(μ)의 절대치가 1 이상이면 압축율이 낮더라도 정보 손실율이 상대적으로 높은 압축방식 예를 들면, COD(Compressed OD)로 소스 디지털 비디오 데이터(SRGB)를 압축한다. 여기서,

≥1는 블록 내의 소스 디지털 비디오 데이터들(SRGB)이 히스토그램(Hist[])에서 도 5와 같이 전 계조범위 내에 분산되어 정보양이 상대적으로 크다는 것을 의미한다. The modulator 42 may calculate various information amounts of the source digital video data SRGB for each block. For example, the modulator 42 creates a histogram (Histogram, Hist []) of the source digital video data SRGB in units of blocks as shown in FIG. 5, and the standard variance value of the histogram Hist [] is standard. deviation, μ) is less than 1,

The back side compresses the source digital video data (SRGB) using a compression scheme having a high compression rate, for example, block truncation coding (BTC). here,

Means that the source digital video data SRGB in the block is concentrated within a certain gradation range in the histogram Hist [], so that the amount of information is small. On the contrary, if the absolute value of the standard variance value (μ) of the histogram Hist [] is 1 or more, the modulator 42 uses a compression method having a relatively high information loss rate even if the compression ratio is low, for example, a compressed OD (COD). Compresses the source digital video data (SRGB). here,

≥ 1 means that the source digital video data SRGB in the block is distributed within the entire gradation range as shown in FIG. 5 in the histogram Hist [], so that the amount of information is relatively large.

The modulator 42 may be built in the timing controller 41.

The data driver 43 converts the modulated digital video data MRGB supplied from the timing controller 41 into an analog gamma voltage and supplies the converted data to the data lines 45.

The gate driver 44 sequentially generates scan pulses under the control of the timing controller 41 and supplies them to the gate lines 46. The scan pulses select one horizontal line to be displayed by turning on the TFTs having the gate electrode connected to the gate lines 46.

6 shows an example of a compression / restoration algorithm of BTC known to have a high compression ratio among compression methods.

)을 문턱치(Xth)로 선정하고, 인코딩 과정에서 블록 내의 픽셀 값들 중에 문턱치(Xth) 이상의 값을 '1'로, 문턱치(Xth)보다 낮은 값을 '0'으로 치환하여 데이터들(SRGB)을 압축한다. 그리고, BTC는 복원을 위한 디코딩 과정에서 각각 평균값(

)과 분산값(

)을 변수로 하는 'a'와 'b'로 '1'과 '0'을 복원한다. 이러한 BTC는 압축율이 50% 이상인 반면에 정보 손실율이 5%에서 최대 15%로 비교적 크다. Referring to FIG. 6, the BTC is a method of compressing an image in units of blocks. The BTC averages pixel values, that is, source digital video data SRGB, in a block, and averages the average value (

) Is selected as the threshold value Xth, and in the encoding process, the data SRGB is replaced by replacing '1' with a value greater than or equal to the threshold value Xth and '0' with a value lower than the threshold value Xth. Compress. In addition, the BTC has an average value (d) in the decoding process for restoration.

) And variance (

) Restores '1' and '0' to 'a' and 'b'. Such BTC has a compression ratio of 50% or more, while the information loss rate is relatively large, from 5% up to 15%.

7 shows the compression / restore of COD, which is known to have a low information loss rate among compression methods.

Referring to FIG. 7, the COD is a method of compressing an image in units of blocks and performs quantization and down-sampling of the luminance component Y and the color difference unit UV of each pixel in units of blocks. The compression method is performed by reducing the number of bits of the source digital video data (SRGB) of each pixel. This COD has a relatively small compression rate of about 30% compared to BTC, but a very small error rate of about 2%.

The modulator 42 of the present invention can compress the source digital video data (SRGB) using any known compression schemes other than BTC or COD, and selects one compression scheme according to the amount of information of the input image. By compressing the source digital video data (SRGB) can reduce the memory capacity of the ODC circuit.

8 is a circuit diagram showing the modulation unit 42 in detail.

Referring to FIG. 8, the modulator 42 includes an image analyzer 81, an encoder 82, a memory 83, decoders 84A and 84B, and a lookup table 85.

The image analyzer 81 generates a histogram by analyzing the frequency for each gray level of the source digital video data SRGB in units of blocks smaller than one screen, and determines the amount of information in the block according to the dispersion degree of the histogram. If the degree of dispersion of the block is smaller than a predetermined reference value, for example, '1', the image analyzer 81 determines that the amount of information of the block is small and compresses with a high compression ratio in front of the source digital video data SRGB of the block. The selection signal '1' indicating the scheme is added. On the other hand, if the degree of dispersion of the block is greater than or equal to a predetermined reference value, for example, '1', the image analyzer 81 determines that the information amount of the block is large. A selection signal '0' indicating a small compression method is added.

9 and 10 are diagrams illustrating a data stream of one block having a small amount of information, and show an example in which a selection signal SEL generated by the image analyzer 81 is added to a header position of a source digital video data stream. give. The selection signal SEL of FIG. 9 is added to the source digital video data stream with a logic value '1' for selecting a compression method having a high compression ratio. The selection signal SEL of FIG. 10 is added to the source digital video data stream with a logic value '0' for selecting a compression method with a small information loss rate.

The encoder 82 stores a plurality of compression algorithms having different compression ratios and information loss ratios, and selects a compression algorithm indicated by the selection signal SEL from the image analyzer 81 among the compression algorithms. The encoder 82 compresses the source digital video data SRGB in units of blocks according to the selected compression scheme.

The memory 83 delays the source digital video data SRGB from the encoder 82 and transfers the delayed data SRGB by storing the source digital video data SRGB compressed by the encoder 82. The lookup table 85 is supplied as frame data Fn-1.

The first decoder 84A stores a plurality of decompression algorithms corresponding to each of the plurality of compression algorithms executable by the encoder 82, and selects and executes one of them according to the selection signal SEL. The first decoder 84A decompresses the compressed data CRGB of the current frame Fn input from the encoder 82 with the selected decompression algorithm and supplies the decompressed data to the lookup table 85. For example, when the logic value of the selection signal SEL is '1', the first decoder 84A restores the compressed data of the current frame in units of blocks using the BTC reconstruction algorithm, while the logic of the selection signal SEL is used. If the value is '0', the compressed data of the current frame is restored in units of blocks using a COD decompression algorithm.

The second decoder 84B stores a plurality of decompression algorithms corresponding to each of the plurality of compression algorithms executable by the encoder 82, and selects and executes any one of them according to the selection signal SEL. The second decoder 84B restores the compressed data CRGB of the previous frame Fn-1 input from the memory 83 with the selected reconstruction algorithm and supplies the reconstructed data to the lookup table 85. For example, if the logic value of the selection signal SEL is '1', the second decoder 84B recovers the compressed data of the current frame in units of blocks using the BTC reconstruction algorithm, while the logic of the selection signal SEL is used. If the value is '0', the compressed data of the current frame is restored in units of blocks using a COD decompression algorithm.

The lookup table 85 compares the current frame data SRGB (Fn) restored with the previous frame data SRGB (Fn-1) restored through the compression / restore algorithm indicated by the selection signal SEL, and compares the result with the comparison result. According to the conditions of Equations 3 to 5, preset modulation data, for example, modulation data of Table 1, is selected. The modulated data selected by this lookup table 85 is supplied to the data driver 43 as modulated digital video data MRGB. On the other hand, the modulation data stored in the lookup table 85 is applicable to any modulation data previously filed by the applicant.

11 is a flowchart showing step by step a control procedure of a method of driving a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 11, when the source digital video data SRGB is input, the image analyzer 81 generates a histogram in units of blocks, and the source digital video data in units of blocks according to the variance value μ of the histogram. SRGB) information amount is analyzed (S1, S2).

Subsequently, the image analyzing unit 81 selects a compression method having a high compression ratio when the dispersion value μ is less than '1', and selects a compression method having a small information loss rate when the dispersion value μ is more than '1'. (S3 to S5) The source digital video data SRGB is compressed by the encoder 82 on a block-by-block basis according to the selected compression scheme.

The source digital video data SRGB compressed by the encoder 82 is stored in the memory 83. The compressed source digital video data SRGB delayed by the memory 83 is reconstructed by the second decoder 84B and the undelayed compressed source digital video data SRGB is received by the second decoder 84A. Is restored. The restored previous frame data SRGB (Fn-1) and the restored current frame data SRGB (Fn-1) are compared by the lookup table 85. As a result of the comparison, the lookup table 85 determines Modulated data for improving the response characteristics is output as modulated digital video data (MRGB) (S8).

As described above, the liquid crystal display and the driving method thereof according to the present invention select a compression method based on the amount of information of the source digital video data to selectively increase the compression ratio of the data to be stored in the memory and reduce the information loss rate. In addition, the liquid crystal display device and the driving method thereof according to the present invention modulate the source digital video data into modulated data to improve the response characteristics of the liquid crystal using data stored in the memory. Therefore, the liquid crystal display and the driving method thereof according to the present invention can increase the display quality by reducing the response speed of the liquid crystal, reduce the memory capacity required for the ODC circuit, and minimize information loss due to data compression.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (12)

An image analyzer for analyzing the information amount of the source digital video data in predetermined block units and selecting one of a plurality of compression / restore methods according to the analyzed information amount; An encoder for compressing the source digital video data according to a compression method selected by the image analyzer; A memory for storing data compressed by the encoder; A decoder for reconstructing the compressed data delayed by the memory and the compressed data supplied from the encoder according to the reconstruction method selected by the image analyzer; A lookup table for comparing the reconstruction data of the previous frame and the reconstruction data of the current frame supplied from the decoder and selecting modulation data according to the comparison result; And And a driving unit which displays the modulation data selected by the lookup table on the liquid crystal display panel. The method of claim 1, The image analyzer, And generating a histogram of the source digital video data in units of blocks, and analyzing the amount of information based on the analysis of the histogram. The method of claim 2, The image analyzer, If the dispersion value of the histogram is smaller than a predetermined reference value, the first compression method having a high compression ratio is selected. And a second compression method having a lower information loss rate than the first compression method when the dispersion value of the histogram is equal to or greater than a predetermined reference value. The method of claim 3, wherein The first compression method is BTC (Block Truncation Coding), And the second compression method is COD (Compressed OD). The method of claim 3, wherein The image analyzer generates a selection signal indicating any one of the plurality of compression / restore schemes according to the information amount, and adds the selection signal to the encoder and the decoder in front of the source digital video data of one block. Supply, And the encoder and the decoder select a compression / restore method according to the selection signal. The method of claim 1, And the modulation data of the lookup table is determined as a value for accelerating the response characteristics of the liquid crystal. Analyzing the amount of information of the input source digital video data in predetermined block units; Selecting any one of a plurality of compression / restore methods according to the analyzed information amount; Compressing the source digital video data according to the selected compression scheme; Storing the compressed data in a memory; Restoring each of the compressed data delayed by the memory and the compressed data supplied from the encoder according to the selected restoration scheme; Comparing the reconstructed data of the previous frame with the reconstructed data of the current frame and selecting modulation data according to the comparison result; And And displaying the selected modulated data on a liquid crystal display panel. The method of claim 7, wherein Analyzing the information amount in predetermined block units, And generating a histogram of the source digital video data in units of blocks, and analyzing the amount of information based on the analysis of the histogram. The method of claim 8, Selecting any one of the plurality of compression / restoration method, Selecting a first compression method having a high compression ratio when the variance value of the histogram is smaller than a predetermined reference value; And And selecting a second compression method having a lower information loss rate than the first compression method if the dispersion value of the histogram is equal to or greater than a predetermined reference value. The method of claim 9, The first compression method is BTC (Block Truncation Coding), And the second compression method is COD (Compressed OD). The method of claim 9, Selecting any one of the plurality of compression / restoration method, Generating a selection signal indicating one of the plurality of compression / restore schemes according to the information amount; Adding the selection signal to the front of the source digital video data in one block and supplying the encoder to perform compression of the data and the decoder to perform restoration of the compressed data, And the encoder and the decoder select a compression / restore method according to the selection signal. The method of claim 7, wherein And wherein the modulated data is determined as a value for accelerating the response characteristics of the liquid crystal.

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