KR20080042463A - Non volatile memory device - Google Patents

Abstract

A non-volatile memory device is provided to increase a degree of integration and to obtain a multi-bit structure by using a plurality of variable resistant elements connected in parallel to each other. A selective element is formed on a semiconductor substrate. A plurality of variable resistant elements(45,55,65) are electrically connected to the selective. The variable resistant elements are connected in parallel to each other. Each of the variable resistant elements includes a variable resistor having a variable resistance dependently on a voltage applied between upper and lower electrodes. The variable resistor includes a perovskite type oxide.

Description

Non volatile memory device

1 is a circuit diagram illustrating a portion of a nonvolatile memory device according to an embodiment of the present invention.

2 is a cross-sectional view illustrating a portion of a nonvolatile memory device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10: semiconductor substrate 20: select transistor

45, 55, 65: first, second and third variable resistance elements

42, 52, 62: lower electrode 43, 53, 63: variable resistor

44, 54, 65: upper electrode

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device using a variable resistance element.

Recently, as a next-generation nonvolatile random access memory (NVRAM) capable of high-speed operation in place of flash memory, various device structures such as FeRAM (Ferroelectric RAM), MRAM (Magnetic RAM), and OUM (Ovonic Unified Memory) are proposed. It is becoming.

For example, FeRAM has low power consumption and high speed operation by utilizing spontaneous polarization inversion of oxide ferroelectric, but has disadvantages of high cost and destruction read.

In addition, the ferromagnetic tunneling effect device using the giant magnetoresistive effect (GMR) used in the MRAM has two ferromagnetic layers made of iron (Fe), cobalt (Co), nickel (Ni), etc., aluminum oxide (Al ₂ O _3). It has a structure located between the ultra-thin insulating layers, such as). Here, the amount of tunnel current flowing through the insulating layers can be controlled by changing the orientation of the magnetization of the ferromagnetic layers, so that there is a memory effect. Such devices have high power consumption for magnetization reversal and difficult size reduction during programming.

OUM based on the thermal phase change of the chalcogenide material also has advantages in low cost and processing matching, but has problems in high speed operation and size reduction by thermal operation.

In addition, a resistive random access memory (RRAM) device using a variable resistance element has extremely low power consumption, is easy to be miniaturized and highly integrated, and multivalue memory is possible because the dynamic range of resistance change is wider than that of MRAM. Has excellent features.

In the resistive random access memory device, a program and erase operation is performed by adjusting a voltage of one variable resistance element. In this case, as the memory device scales down, there is a limit in achieving high integration.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a nonvolatile memory device capable of increasing integration and enabling multi-bit implementation.

According to an aspect of the present invention, a nonvolatile memory device includes a selection device on a semiconductor substrate, and a plurality of variable resistance devices electrically connected to the selection device, and having an electrical resistance changed. The plurality of variable resistance elements are connected in parallel with each other.

The plurality of variable resistance elements may include a variable resistor having a resistance value changed depending on an applied voltage between upper and lower electrodes, and the variable resistor may include a perovskite oxide.

In addition, each of the variable resistors included in the plurality of variable resistance elements may have a different thickness.

The voltage of both ends of the plurality of variable resistance elements may be changed to adjust a resistance of some or all of the plurality of variable resistance elements to perform a program or erase operation.

In addition, the selection device electrically connected to the variable resistance device may be a transistor or a diode.

Specific details of other embodiments are included in the detailed description and drawings.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms different from each other, and only the present embodiment makes the disclosure of the present invention complete, and has ordinary skill in the art It is provided to fully inform the scope of the invention, and the invention is defined only by the scope of the claims. Thus, in some embodiments, well known process steps, well known device structures and well known techniques are not described in detail in order to avoid obscuring the present invention. Like reference numerals refer to like elements throughout.

The spatially relative terms below, beneath, lower, above, upper, etc. may be used to easily describe the correlation of one component with another as shown in the figures. Can be. Spatially relative terms are to be understood as including terms that differ in the direction of use of the components in use or operation in addition to the directions shown in the figures. For example, when inverting the components shown in the figures, components described as beneath beneath other components may be placed above and above other components. Thus, the exemplary term below may include both the direction below and above. The components can be oriented in other directions as well, so that spatially relative terms can be interpreted according to the orientation.

Hereinafter, a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. 1 is a circuit diagram illustrating a portion of a nonvolatile memory device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view illustrating a nonvolatile memory device according to an embodiment of the present invention.

As shown in FIGS. 1 and 2, in the nonvolatile memory device 100 according to an exemplary embodiment, the selection element 20 is positioned on a substrate 10, for example, a P-type semiconductor substrate 10. do. The selection element 20 may be a transistor or a diode. Herein, a case where the selection element 20 is a transistor (hereinafter, referred to as a "selection transistor") will be described.

The select transistor 20 overlaps the source / drain regions 22 and 23 formed by doping conductive impurities on both sides of the channel region 21 in the semiconductor substrate 10 and the channel region 11. 10) a gate stack 26 located on it. The gate stack 26 includes a gate insulating layer 24 and a gate electrode 25 sequentially stacked.

The first interlayer insulating film 30 covering the selection transistor 20 is formed on the semiconductor substrate 10. The first interlayer insulating film 30 is provided with first and second contact holes 31 and 32 penetrating the first interlayer insulating film 30, and each of the contact holes 31 and 32 has first and second conductivity. Plugs 33 and 34 are located. The first and second conductive plugs 33 and 34 may be conductive layers or semiconductor layers doped with conductive impurities.

The junction of any one of the source region 22 and the drain region 23 of the variable resistance elements 45, 55, 65 and the selection transistor 20 through the first or second conductive plugs 33, 34. The regions may be electrically connected. Hereinafter, a case in which the drain region 23 of the selection transistor 20 and the plurality of variable resistance elements 45, 55, and 65 are electrically connected will be described.

The drain region 23 of the select transistor 20 is a variable resistance element adjacent to the drain region 23 among the plurality of variable resistance elements 45, 55, and 65 (hereinafter referred to as a “first variable resistance element”). 45 and the first conductive plug 33 formed in the first interlayer insulating film 30 are electrically connected to each other. The first conductive plug 33 is directly connected to the first metal wire 41a which is in contact with the lower portion of the first variable resistance element 45, and the portion 41b of the first metal wire forms a source line. , Which is electrically connected to the source region 22 of the selection transistor 20 through the second conductive plug 34.

The variable resistance element 45 may have a stacked structure including a variable resistor 43 including a perovskite oxide between the upper and lower electrodes 42 and 44.

As a perovskite type oxide used as the variable resistor 43, the chemical formula is represented by "ABO ₃ ", and typically, titanium tri lead (PbTiO ₃ ), titanium tribarium (BaTiO ₃ ), and the like can be given. For example, praseodymium (Pr) and manganese (Mn) -based perovskite oxides are partially or completely substituted with proseodymium (Pr) at the position of "A" in the chemical formula of "ABO ₃ ", and "B Manganese (Mn) may be substituted at part or all.

For example, it may be a simple form such as Pr _x A _{1 - x} MnO ₃ system (0 = x = 1), and also (Pr _x A _1-x ) (Mn _y B _1-y ) O ₃ system The number of atoms substituted by A or B, such as (0 = x = 1, 0 = y <1), may be increased.

A may use at least one element selected from calcium (Ca), lanthanum (La), strontium (Sr), gadolinium (Gd), neodymium (Nd), bismuth (Bi) and cerium (Ce), and B is At least one element selected from tantalum (Ta), titanium (Ti), copper (Cu), chromium (Cr), cobalt (Co), iron (Fe), nickel (Ni) and gallium (Ga) may be used.

As the oxide of the perovskite structure to be such a variable resistor 42, (Pr, Ca) MnO ₃ , SrTiO ₃ , (Ba, Sr) TiO ₃ , LaMnO ₃ , LaTiO ₃ , (Nd, Sr) MnO ₃ , (La, Sr) MnO _3, etc. may be mentioned.

This type of material exhibit phenomenon that the electric resistance changed by the application of the voltage pulse, particularly Pr _{1 - x} Ca _x MnO material (PCMO film) of ₃ family shows a resistance change due to a larger voltage pulse.

In addition, the lower electrode 42 positioned on the drain region 23 side of the select transistor 20 includes platinum (Pt) and iridium (Ir) having high lattice matching with a perovskite oxide and high conductivity and high oxidation resistance. ), A noble metal body of platinum group metal represented by palladium (Pd) or an alloy based on noble metal, or an oxide conductor of iridium (Ir), ruthenium (Ru), rhenium (Re), osmium (Os), or SRO ( Oxide conductors such as SrRuO ₃ ), LSCO ((LaSr) CoO ₃ ), and YBCO (YbBa ₂ Cu ₃ O ₇ ) can be used.

On the other hand, since the upper electrode 44 is not necessarily exposed in a high temperature oxygen atmosphere, the upper electrode is not limited to precious metal elements such as platinum (Pt), iridium (Ir), ruthenium (Ru), and the like. Various materials, such as metals, such as aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti), and tantalum (Ta), and an oxide conductor, are applicable.

In addition, the second metal wires 51a and 51b are formed on the first variable resistance element 45 via the second interlayer insulating film 40, and a part of the second metal wires 51a forms a bit line. Is connected to the upper electrode 44 of the first variable resistance element 45 via a third conductive plug 48 located in the first via 46 so that the other part 51b of the second metal wire 51 is formed. The first metal wire 41a in contact with the lower electrode 42 of the first variable resistance element 45 and the fourth conductive plug 49 positioned in the second via 47 are electrically connected to each other. Through the fourth conductive plug 49, the variable resistance element (hereinafter referred to as “second variable”) is brought into contact with the second metal wire 51b electrically connected to the lower electrode 42 of the first variable resistance element 45. 55 "is located. Here, the second variable resistance element 55 has a stacked structure of the lower electrode 52, the variable resistor 53, and the upper electrode 54, except for the thickness of the variable resistor 53. Since it is substantially the same as (45), the overlapping description is abbreviate | omitted.

In addition, the third metal wires 61a and 61b are formed on the second variable resistance element 55 via the third interlayer insulating film 50, and a part of the third metal wires 61a forms a bit line. Is connected to the upper electrode 54 of the second variable resistance element 55 via a fifth conductive plug 58 located in the third via 56, and the other portion 61b of the third metal wire is connected. The second metal wire 51b in contact with the lower electrode 52 of the second variable resistance element 55 and the sixth conductive plug 59 positioned in the fourth via 57 are electrically connected to each other. The sixth conductive plug 59 contacts the third metal wire 61b electrically connected to the lower electrode 52 of the second variable resistance element 55 to form a variable resistance element (hereinafter referred to as “third variable”). 65 "is located. The third variable resistance element 65 has a stacked structure of a lower electrode 62, a variable resistor 63, and an upper electrode 64, except for the thickness of the variable resistor 63. Since it is substantially the same as (45), the overlapping description is abbreviate | omitted.

In addition, the fourth metal wiring 68 is formed on the third variable resistance element 65 via the fourth interlayer insulating film 60 and is positioned in the fifth via 66 so as to be used to form the bit line. It is connected to the upper electrode 64 of the third variable resistance element 65 via the conductive plug 67.

As described above, the plurality of variable resistance elements 45, 55, and 65 are formed at different levels on the select transistor 20 to enable high density integration of memory cells.

In addition, the plurality of variable resistance elements 45, 55, and 65 vary the thicknesses of the variable resistors 43, 53, and 63, and then parallel the plurality of variable resistance elements 45, 55, and 65 including the same. In connection, by adjusting the voltage across the variable resistance elements 45, 55, 65, the resistance of the entire variable resistance elements 45, 55, 65 can be adjusted in multiple stages. According to the thickness of the variable resistors 43, 53, and 63, the electric field applied to the variable resistor elements 45, 55, and 65 including the same decreases or increases, so that a voltage required to perform a program or erase operation varies. It is to use what is lost.

For example, when a program operation is to be performed on the nonvolatile memory device 100 according to the exemplary embodiment of the present invention as shown in FIGS. 1 and 2, the gate voltage Vg is about 5V and the source voltage ( When Vs) is applied at 0V and the drain voltage Vd is 3V, the resistance value of the first variable resistance element 45 having the relatively thin variable resistor 43 can be changed, and the drain voltage Vd is 3.5. When V is applied, not only the first variable resistance element 45 but also the second variable resistance element 55 having the variable resistor 53 relatively thicker than the first variable resistance element 45 may change the resistance value. In the case where the drain voltage Vd is applied to 4V, the resistance value may be set together with the first and second variable resistance elements 45 and 55 as well as the third variable resistance element 65 having the relatively thickest variable resistor 63. Can be changed to perform program operations.

Similarly, when the erase operation is to be performed, when the gate voltage Vg is about 5V, the source voltage Vs is 0V, and the drain voltage Vd is 1V, a relatively thin variable resistor 43 is provided. The resistance value of the first variable resistance element 45 may be changed, and when the drain voltage Vd is applied at 1.5 V, the first variable resistance element 45 may be relatively thicker than the first variable resistance element 45 as well as the first variable resistance element 45. The second variable resistance element 55 having the variable resistor 53 can also change the resistance value, and when the drain voltage Vd is applied to 2 V, the third variable resistor having the relatively thick variable resistor 63 is used. The erase operation may be performed by changing the resistance value together with the element 65.

Therefore, the variable resistance elements 45, 55, and 65 including the variable resistors 43, 53, and 63 having different thicknesses are arranged in parallel, so that the ends of the variable resistance elements 45, 55, and 65 are arranged in parallel. Since the resistance of the entire variable resistance elements 45, 55, and 65 may be adjusted in multiple stages by adjusting the applied voltage, the multi-bit may be implemented by using a current by the resistance that varies in multiple stages.

Here, the case where three variable resistance elements 45, 55, and 65 are connected in parallel has been described as an example. However, the number of variable resistance elements arranged in one memory cell depends on the characteristics and functions of the entire configuration of the nonvolatile memory device. Can be determined.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the present invention, by including a plurality of variable resistance elements connected in parallel, it is possible to provide a nonvolatile memory device capable of increasing the degree of integration of a memory device and enabling multi-bit implementation.

Claims (6)

Select elements on a semiconductor substrate; And Is electrically connected to the selection element, and includes a plurality of variable resistance element, the electrical resistance is changed, And the plurality of variable resistance elements are connected in parallel to each other. The method of claim 1, The plurality of variable resistance elements may include a variable resistor whose resistance value is changed between upper and lower electrodes depending on an applied voltage. The method of claim 2, The variable resistor includes a perovskite oxide. The method of claim 2, Each of the variable resistors included in the plurality of variable resistance elements has a different thickness. The method of claim 1, And a program or erase operation by changing a voltage across both of the plurality of variable resistance elements to adjust a resistance of some or all of the plurality of variable resistance elements. The method of claim 1, And the selection device is a transistor or a diode.

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