KR20080041936A - Method for testing weak cell of phase-change random access memory and a semiconductor memory device using the method - Google Patents

Abstract

A method for testing a weak cell of a phase change random access memory and a semiconductor memory device using the same are provided rapidly to detect a defective cell capable of performing normal read operation because of changed resistance of a phase change material according to repetitive read operation. A plurality of memory cell arrays(210_1-210_n) include a plurality of sectors comprising a plurality of cells. A word line pulse control part(230) controls to change width or period of a word line pulse applied to the memory cell array. The word line pulse control part controls to increase the width of the word line pulse, and to reduce the period of the word line pulse. A current control part(250) controls a current flowing in a cell to be tested. A control part(270) controls to apply the changed word line pulse to each sector at the same time.

Description

Method for testing weak cell of phase-change random access memory and a semiconductor memory device using the method

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is an equivalent circuit diagram of a phase change memory device.

2 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 3 is a circuit diagram for determining whether one cell included in the memory cell array of FIG. 2 is defective.

4 is a waveform diagram of each signal in the circuit diagram of FIG. 3.

5 is a voltage waveform diagram of a word line and a bit line according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a state in which defective cells are detected by resistance change and defect detection according to an exemplary embodiment of the present invention.

7 is a detailed block diagram illustrating the semiconductor memory device of FIG. 2.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to detecting defective cells, and more particularly, to a method of detecting defective cells in a phase-change random access memory (PRAM) and a semiconductor memory device using the method.

A phase change memory (PRAM) is a nonvolatile memory device that stores data using a phase change material whose resistance changes with temperature change, for example, a material such as Ge-Sb-Te (GST). PRAM has both the advantages of flash memory, which does not erase stored information even when the power is turned off, and the advantages of DRAM that process data faster.

1 is an equivalent circuit diagram of a phase change memory device.

Referring to FIG. 1, the unit cell C of the phase change memory device includes one phase change material GST. The unit cell C may further include one P-N diode D connected to the phase change material GST. The phase change material GST is connected to the bit line BL, the phase change material GST is connected to the P-junction of the diode D, and the word line WL is connected to the N-junction. . The phase change material (Ge-Sb-Te) of the cell C of the phase change memory stores information by crystallizing or decrystallizing the phase change material according to temperature and heating time. In order to change the phase of a phase change material, a high temperature of 900 ° C. or more is generally required, which is obtained by Joule heating using a current flowing in a phase change memory cell.

During a write operation, when a current flows through the phase change material GST, the phase change material GST transitions to a crystalline state or an amorphous state. The crystalline state or amorphous state of the phase change material GST depends on the magnitude and amount of current flowing through the phase change material GST. When a large current flows through the phase change material GST for a short time, the phase change material GST changes to an amorphous state, which is generally referred to as a reset state and corresponds to data "1". When a current smaller than the reset current flows for a long time in the phase change material (GST), the phase change material (GST) changes to a crystalline state. This state is generally called a set state and the data corresponds to "0". do. When the phase change material GST is in the reset state, the resistance is greater than that in the set state.

The read operation selects a specific memory cell by selecting a bit line and a word line, and then flows a current from the outside to determine "1" and "0" as a difference in voltage change depending on the resistance state of the phase change material (GST). Separate.

In this case, if the repetitive read operation is performed, there is a possibility that the resistance of the phase change material GST may change continuously, thereby preventing the normal read operation. In particular, a cell formed with a low threshold voltage of the phase change material GST is more likely to have this problem. Therefore, the above-described bad cell should be detected by repeatedly performing the read operation. However, since it takes a long time to detect the bad cell, it is difficult to detect it.

An object of the present invention is to provide a semiconductor memory device for quickly detecting a defective cell in which the resistance of the phase change material (GST) is changed as the read operation is repeatedly performed, thereby failing to perform a normal read operation.

Another object of the present invention is to provide a method for detecting the defective cell using the semiconductor memory device.

In accordance with another aspect of the present invention, a semiconductor memory device includes a plurality of memory cell arrays and a word line pulse controller. The memory cell array includes a plurality of sectors having a plurality of cells. The word line pulse controller controls the width or period of a word line pulse applied to the memory cell array to be changed.

The word line pulse controller may be configured to control the width of the word line pulse to increase or to reduce the period of the word line pulse.

The semiconductor memory device may further include a current controller configured to control a current flowing in a cell to be tested among the plurality of cells.

The current controller preferably controls the current flowing in the cell to be tested to increase.

The semiconductor memory device may further include a control unit for controlling the changed word line pulses to be simultaneously applied to each sector.

The semiconductor memory device may further include a controller configured to control the changed word line pulse and the changed current to be simultaneously applied to each sector.

The semiconductor memory device may be a phase-change random access memory (PRAM).

According to another aspect of the present invention, there is provided a method for detecting a bad cell, wherein the method for detecting a bad cell of a plurality of memory cell arrays includes a plurality of sectors having a plurality of cells. Changing a width or a period of an applied word line pulse and detecting a defective cell by performing a read operation using the changed word line pulse.

The method may further include controlling a current flowing in the cell to be tested among the plurality of cells.

Preferably, the bad cell detection method further includes controlling the modified word line pulses to be simultaneously applied to the respective sectors.

The bad cell detection method may further include controlling the changed word line pulse and the changed current to be simultaneously applied to each sector.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a block diagram of a semiconductor memory device 200 according to an embodiment of the present invention.

Referring to FIG. 2, the semiconductor memory device 200 includes a plurality of memory cell arrays 210_1, 210_2,..., 210_n, a word line pulse controller 230, a current controller 250, and a controller 270. do.

Each of the plurality of memory cell arrays 210_1, 210_2,..., 210_n includes a plurality of sectors including a plurality of cells. The word line pulse controller 230 controls the width or period of the word line pulse (WLP) applied to each of the memory cell arrays 210_1, 210_2,..., 210_n to be changed. The current controller 250 controls a current flowing in a cell currently being tested among the plurality of cells. The controller 270 is configured to apply the word line pulse WLP or / or the changed current to which the width or the period is changed at the same time to the sectors included in each of the memory cell arrays 210_1, 210_2,..., 210_n. To control. Hereinafter, a method of determining whether a cell is a bad cell in FIG. 3 will be described.

3 is a circuit diagram 300 for determining whether a single cell 310 included in the memory cell array of FIG. 2 is defective.

Referring to FIG. 3, a cell 310 includes an NMOS transistor N310 and a resistor R. Referring to FIG. A gate of the NMOS transistor N310 is connected to the word line WL, a first end thereof is connected to a resistor R, and a second end thereof is connected to a ground voltage VSS. The other end of the resistor that is not connected to the NMOS transistor N310 is connected to a bit line BL.

4 is a waveform diagram of each signal in the circuit diagram of FIG. 3.

A method of detecting a defective cell will be described with reference to FIGS. 3 and 4. The read control signal is a signal meaning that the read operation is performed while in the first logic state. Hereinafter, the first logic state means a logic high state. The barrier voltage VCMP applies a constant DC voltage to control the current in the read operation so that the current does not flow into the light region.

While the read control signal is in the first logic state, the bit line voltage VBL and the wordline voltage VWL maintain the first logic state to perform a read operation. In the case of performing the read operation, the present invention provides two embodiments. The first embodiment is to change the width of the word line pulse WLP, and the second embodiment is to change the period of the word line pulse WLP. Simultaneously with the above embodiments, the current controller 250 controls the read current. That is, the current controller 250 controls the current Is flowing in the cell under test. The current controller 250 increases the current flowing in the cell under test so that a higher read current RC flows. Thus, the same effect as performing more read operations is obtained for the cell.

5 is a voltage waveform diagram of a word line and a bit line according to an embodiment of the present invention.

The first and second embodiments will be described with reference to FIGS. 3 and 5. 5A is a waveform diagram of a voltage VWL of a word line according to the prior art, and FIG. 5B is a waveform diagram of a voltage VWL of a word line and a voltage VBL of a bit line according to the first embodiment. ) / Waveform of lead current RC. FIG. 5C is a waveform diagram of a voltage VWL of a word line and a waveform of voltage VBL / read current RC of a bit line according to the second embodiment.

First, the first embodiment will be described. The first embodiment makes the width of the word line pulse WLP larger than the width of the conventional word line pulse WLP of FIG. The word line pulse controller 230 makes the width of the word line pulse WLP wider than that of the related art, thereby widening the width of the voltage VWL pulse of the bit line. Therefore, since the time during which the read current RC has the first logic state is much longer than in the prior art, the same effect as performing the read operation for a longer time than in the related art is obtained.

The second embodiment makes the period of the word line pulse WLP shorter than that of the conventional word line pulse WLP of FIG. In other words, the word line pulse controller 230 may shorten the period of the word line pulse WLP by repeatedly turning on or off the word line WL. In this case, the voltage VWL pulse and the read current RC of the bit line change as shown in FIG. 5C. When the voltage VWL of the word line starts to rise, the read current RC also starts to rise, and a peak current flows instantaneously. That is, whenever the word line WL is turned on, a peak read current is generated instantaneously, and the peak read current is repeatedly generated as the word line WL is repeatedly turned on and off. do. Therefore, the read current RC of the peak value is transferred to the cell, thereby obtaining the same effect as performing the read operation more.

FIG. 6 is a diagram illustrating a state in which defective cells are detected by resistance change and defect detection according to an exemplary embodiment of the present invention.

An effect according to the first and second embodiments will now be described with reference to FIG. 6. When performing the present invention according to the first embodiment it can be detected that the resistance of the phase change material (GST) shifts according to the temperature characteristics or current characteristics. In other words, the solid line portion of the reset region Rreset of FIG. 6 becomes smaller as a resistance due to the repetitive read operation, and thus changes as a dotted line. As described above, when the resistor shifts, the reset region Rreset is not normally detected, and thus, the normal read operation cannot be performed. In addition, when performing the present invention according to the second embodiment, it is possible to detect not only the shift of the resistance, but also a circuit defect or noise. The circuit defect means that the read operation cannot be normally performed because the threshold voltage of the phase change material GST is lower than the normal value.

FIG. 7 is a detailed block diagram illustrating the semiconductor memory device 200 of FIG. 2.

Referring to FIG. 7, the memory cell array 210_1 includes n sectors (sector 1_1, sector 1_2,..., Sector 1_n). In addition, the other memory cell arrays 210_2,..., 210_n have the same n sectors. The controller 270 controls the word line pulses WLP to be simultaneously applied to each sector. That is, the plurality of sectors may be tested at a time by applying the changed word line pulse WLP to the plurality of sectors according to the first embodiment or the second embodiment. In addition, the controller 270 controls the current changed by the current controller 250 to be applied to each sector at the same time.

8 is a flowchart of a method of performing a bad cell test according to an embodiment of the present invention.

Referring to FIG. 8, a width of a word line pulse WLP having a predetermined width or period is changed according to the first embodiment or the period is changed according to the second embodiment (step S810). As described above, the width of the word line pulse WLP is increased according to the first embodiment or the period of the word line pulse WLP is reduced according to the second embodiment. In operation S820, the current flowing through the cell under test is changed among the cells of the memory cell array. The current flowing through the cell under test is increased so that a higher current flows through the cell under test. In addition, the changed word line pulse WLP and the changed current are simultaneously applied to each sector included in each memory cell array in order to shorten the test time (S830). By determining whether the read operation is normally performed through the above steps, it is determined whether the cell to be tested is a defective cell (step S840).

The above defective cell detection method is preferably applied to a phase change memory (PRAM), and the semiconductor memory device using the method is also preferably a phase change memory (PRAM).

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, in the method of detecting a defective cell of a phase change memory (PRAM) according to the present invention and a semiconductor memory device using the method, the resistance of the phase change material (GST) is changed as a read operation is repeatedly performed. There is an advantage in that it is possible to quickly detect a defective cell that cannot perform a normal read operation.

Claims (15)

A plurality of memory cell arrays comprising a plurality of sectors having a plurality of cells; And And a word line pulse controller configured to control a width or a period of a word line pulse applied to the memory cell array to be changed. The word line pulse controller of claim 1, wherein: And controlling the width of the word line pulse to increase. The word line pulse controller of claim 1, wherein: And controlling the period of the word line pulse to be reduced. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises: And a current controller for controlling a current flowing in a cell to be tested among the plurality of cells. The method of claim 4, wherein the current control unit, And controlling the current flowing in the test cell to increase. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises: And a controller for controlling the modified word line pulses to be simultaneously applied to the respective sectors. The semiconductor memory device of claim 4, wherein the semiconductor memory device comprises: And a control unit for controlling the changed word line pulse and the changed current to be simultaneously applied to each of the sectors. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises: A semiconductor memory device, characterized in that it is a phase-change random access memory (PRAM). A method of detecting a defective cell of a plurality of memory cell arrays comprising a plurality of sectors having a plurality of cells, the method comprising: Changing a width or a period of a word line pulse applied to the memory cell array; And And detecting a defective cell by performing a read operation using the changed word line pulse. The method of claim 9, wherein changing the width of the word line pulses comprises: And increasing the width of the word line pulses. The method of claim 9, wherein the changing of the period of the word line pulse comprises: And decreasing the period of the word line pulses. The method of claim 9, wherein the defective cell detection method, And controlling a current flowing in a cell to be tested among the plurality of cells. The method of claim 12, wherein controlling the current comprises: And controlling the current flowing in the cell to be tested to increase. The method of claim 9, wherein the defective cell detection method, And controlling the modified word line pulses to be simultaneously applied to each of the sectors. The method of claim 12, wherein the defective cell detection method, And controlling the modified word line pulse and the changed current to be simultaneously applied to each of the sectors.

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