KR20080034750A - Apparatus and method for processing clock signal of serial communication system - Google Patents

Abstract

An apparatus and a method for processing clock signals of a serial communication system are provided to prevent the attenuation of signals due to the length of wires by utilizing a reference clock according to clock signal conditions. A serial communication system includes a transmitter and a receiver(200). The receiver includes a reference clock generator(220), a serial transceiver(210), a control logic(240), a HDLC(High level Data Link Control) controller(230), and a microprocessor. The reference clock generator generates a reference clock. The serial transceiver converts clock and data signals received through a serial line into TTL(Transistor Transistor Logic) signals. The control logic processes serial data using the TTL and clock signals, sets an error detection range using the reference clock, and processes the serial data using the TTL signal and reference clock when a positive edge is not detected in the error detection range. The HDLC controller processes the serial data. The microprocessor executes a communication function according to the serial data.

Description

Method and apparatus for processing clock signal in serial communication system {APPARATUS AND METHOD FOR PROCESSING CLOCK SIGNAL OF SERIAL COMMUNICATION SYSTEM}

1 is a block diagram for explaining data exchange in a serial communication scheme in a general data communication network.

2 is a diagram for explaining reception communication equipment of a serial communication system according to a preferred embodiment of the present invention.

3 is a view for explaining a clock signal processing apparatus of a serial network module according to an embodiment of the present invention.

4 is a flowchart for explaining a clock signal processing method of a serial communication system according to a preferred embodiment of the present invention.

** Description of the symbols for the main parts of the drawings **

200: serial network module 210: serial transceiver

220: reference clock generator 230: HDLC controller

240: control logic 241: synchronous control logic

242: Register 243: mux

244: Inverter

The present invention relates to a method and apparatus for processing a clock signal of a serial communication system. More particularly, the clock signal (RXC) received at the receiving side of the serial communication system has errors due to attenuation of the signal along the length of the serial line. The present invention relates to a clock signal processing method and apparatus thereof of a serial communication system that do not occur.

Currently, a serial network module capable of exchanging data by serial communication in a wide area network is being applied. That is, a serial network module capable of exchanging data in a serial communication method is mounted in a communication device to exchange data in a data communication network such as a broadband network.

1 is a block diagram for explaining data exchange in a serial communication method in a general data communication network.

Referring to FIG. 1, a transmission communication device 10 that transmits a clock signal TXC and a data signal TXD, and a reception communication device 20 that receives a clock signal RXC and a data signal RXD receive data. It is connected through a network.

That is, the reception communication device 20 receives the clock signal RXC and the data signal RXD from the transmission communication device 10 through a data communication network such as a broadband communication network. The clock signal and the data signal are received through the respective serial lines, and the data signal is transmitted in synchronization with the clock signal.

The transmission communication device 10 synchronizes the data signal with a reference clock generated by itself, and transmits the clock signal TXC and the data signal TXD to the reception communication device 20 through respective serial lines.

That is, the transmission communication equipment 10 processes the data to be transmitted through the physical layer, synchronizes the data signal with the reference clock, and converts each serial line into a differential signal, that is, a clock signal and a data signal. To the data network.

Meanwhile, the reception communication equipment 20 converts the clock signal and the data signal received through each serial line into a 0-5 volt TTL (transistor-transistor logic) signal to restore data of the second layer (LAYER-2). And process the data processing.

That is, the receiving communication device 20 refers to the reference clock generated by itself, converts the differential signal received on each serial line, that is, the clock signal and the data signal into the TTL signal, and muxes the reference clock and the data. Restore data of the second layer.

In brief, the method of processing the data received by the receiving communication device 20 in the serial communication method, the clock signal RXC received through each serial line in the serial network module and the data signal RXD synchronized thereto are Signal level translation is done, and mux / demux operations are then processed into two layers of data, depending on the module's set mode or configuration.

In the data processing method of the serial network module of the general communication equipment, it does not satisfy the high speed data transmission due to the characteristics of the serial communication, such as encoding / decoding performance or signal attenuation according to the length of the serial line between the transmitting end and the receiving end. If the clock signal is abnormally received for a reason, an error occurs during data synchronization.

If an error occurs in the data synchronization process, a cyclic redundancy check (CRC) error may occur according to this, and there is no way to solve the clock signal (RXC) error. In the protocol, a limitation of a transmission rate or a limitation of a serial transceiver occurs.

Therefore, the present invention was devised to solve the above problems, and the clock signal RXC received at the receiving side of the serial communication system exchanging data in the serial communication method is the same as the signal attenuation according to the length of the serial line. It is an object of the present invention to provide a clock signal processing method and apparatus for a serial communication system that detects an error and handles it so that a problem caused by the error does not occur and minimizes communication restrictions.

A serial communication system according to an aspect of the present invention for achieving the above object, the transmission communication equipment for transmitting a clock signal (TXC) and the data signal (TXD) in synchronization with it through a data communication network, and each through the data communication network Receives the clock signal RXC and the data signal RXD synchronized with the serial line of the signal, and does not detect the positive edge through the serial line through which the clock signal RXC is received within the set error detection range. Or a receiving communication device for processing the data signal using a self-generated reference clock.

The receiving communication equipment includes: a reference clock generator for generating the reference clock, a serial transceiver for converting a clock signal (RXC) and a data signal (RXD) received through each serial line into a TTL signal, and the serial The serial data is processed using the TTL signal and the clock signal converted by the transceiver, an error detection range is set using the reference clock generated by the reference clock generator, and the positive edge is detected within the error detection range. Otherwise, the control logic for processing the serial data using the TTL signal and the reference clock, the HDLC controller for two-layer processing the serial data processed in the control logic, and a communication function according to the serial data. A microprocessor for processing.

The control logic preferably inverts the reference clock to process the serial data.

The error detection range is preferably set according to the number of pulses of the clock signal RXC corresponding to an input error allowable value.

According to another aspect of the present invention, a serial network module of a serial communication system includes a reference clock generator for generating a reference clock and a clock signal (RXC) and a data signal (RXD) received through serial lines of a data communication network, respectively. A serial transceiver converting the signal into a signal, the serial data is processed using the TTL signal and the clock signal converted from the serial transceiver, and the error detection range is set using the reference clock generated by the reference clock generator; If the positive edge is not detected within the error detection range, the control logic for processing the serial data using the TTL signal and the reference clock, and the HDLC controller for two-layer processing the serial data processed by the control logic. It includes.

The control logic may include synchronous control logic for outputting first and second selection signals depending on whether the positive edge is detected within the error detection range through the serial line, an inverter for inverting the reference clock, and a first; The clock signal RXC is input to an input terminal, an inverted reference clock inverted from the inverter is input to a second input terminal, and when the first selection signal is input, the clock signal is output and the second selection is performed. When a signal is input, the first mux outputs the inverted reference clock.

In the control logic, when the reference clock is input to a first input terminal, an inverted reference clock inverted by the inverter is input to a second input terminal, and when the first selection signal is input, the reference clock is converted into the first clock. And a second mux outputting the second input terminal of the mux and outputting the inverted reference clock to the second input terminal of the first mux when the second selection signal is input.

According to another aspect of the present invention, there is provided a method of processing a clock signal at a receiving side of a serial communication system, the method comprising: generating a reference clock synchronized with a reference clock at a transmitting side transmitting data through a data communication network; Setting a predetermined period of error detection range, receiving a clock signal RXC and a data signal RXD through each serial line, and detecting a positive edge on the serial line within the error detection range. A) the data signal RXD is processed using the clock signal RXC when the positive edge is detected, and b) the generated reference clock is detected if the positive edge is not detected. And processing the data signal RXD.

A method of processing a clock signal at a receiving side of the serial communication system may include blocking the clock signal RXC inputted through the serial line from being input if the positive edge is not detected. And inverting the reference clock to prevent skew between the data signals RXD.

Hereinafter, a method and apparatus for processing a clock signal of a serial communication system according to the present invention will be described in detail with reference to the accompanying drawings. In the technical field of the present invention, an error occurs in the clock signal RXC at the data receiving side of the serial communication system. Since it is a case of occurrence, detailed description of the data transmission side is omitted.

2 is a view for explaining the reception communication equipment of the serial communication system according to an embodiment of the present invention.

Referring to FIG. 2, a receiving communication device according to the present invention includes a serial network module 200 and a serial network module 200 for receiving and processing a clock signal RXC and a data signal RXD through respective serial lines. Microprocessor 300 for processing / controlling the communication function set in the equipment based on the data received through the.

The serial network module 200 includes a serial transceiver 210, a reference clock generator 220, a high-level data link control (HDLC) controller 230, and control logic 240. Logic 240 includes synchronous control logic 241.

The reference clock generator 220 generates a reference clock signal and provides it to the control logic 240. At this time, the reference clock generator 220 preferably generates a reference clock of the same frequency as the reference clock of the data transmission side of the serial communication system.

The serial transceiver 210 converts a differential signal, that is, a clock signal RXC and a data signal RXD, received through each serial line through a data communication network into a TTL signal.

The control logic 240 may be implemented as a programmable logic device (PLD). The control logic 240 may mux / demux the TTL signal and the clock signal changed in the serial transceiver 210 to transmit serial data to the HDLC controller 230. Each component of the serial network module 200 is controlled.

The HDLC controller 230 restores serial data received from the control logic 240 to data of two layers. That is, the HDLC controller 230 processes the data link layer corresponding to the two layers of the OSI model.

In HDLC, data is stored in the form of frames such as Flag (8bit), Address (8bit), Control (8bit), Data information (arbitrary), Error checking of frame (16bit), Flag (8bit), The HDLC controller 230 processes data according to the conventions defined in the HLDC.

On the other hand, the control logic 240 detects the clock signal RXC received through the serial line during the set error detection range, and if the clock signal is not received through the serial line, from the reference clock generator 220. The generated reference clock is input to the clock signal RXC.

The synchronous control logic 241 of the control logic 240 checks whether a positive edge is input through the serial line within an error detection range, for example, a set error detection range, and when the positive edge is detected, The data processing clock signal HDLC_RXC, which is processed based on the clock signal RXC received through the serial line, is transmitted to the HDLC controller 230. That is, the data is processed using the clock signal RXC input to the serial line.

On the other hand, the synchronization control logic 241 indicates that an error has occurred in the clock signal RXC input through the serial line when the positive edge is not detected within the error detection range, that is, when the positive edge to be input at a predetermined period is not detected. In operation, the data is processed based on the reference clock generated by the reference clock generator 220.

In addition, the synchronous control logic 241 preferably prevents any signal input from the serial line from being input. This is to prevent the errored clock signal RXC from being input.

At this time, the synchronization control logic 241 inverts the reference clock such that skew between the data signal RXD and the reference clock received through the serial line does not occur.

Thereafter, when the positive edge is detected within the set error detection range, the synchronization control logic 241 again processes the serial data using the clock signal RXC input through the serial line.

That is, the synchronization control logic 241 automatically detects an error by checking whether an error of the clock signal RXC received through the serial line is received within the error detection range and automatically detects the error, and an error is detected in the clock signal RXC. When generated, the reference clock generated by the reference clock generator 220 is replaced with a clock signal RXC to be used.

In addition, an error detection range in which the synchronization control logic 241 detects an error of the clock signal RXC may be set according to the allowable number of clock errors, and it is preferable to set the allowable number of clock errors to a minimum.

3 is a diagram illustrating a clock signal processing apparatus of a serial network module according to an exemplary embodiment of the present invention.

Referring to FIG. 3, when the error of the clock signal RXC received through the serial line is detected and an error of the clock signal RXC occurs, the synchronization is replaced by a reference clock generated by the reference clock generator 220. The control logic 241, a pair of muxes 243 for outputting one of a plurality of input signals in accordance with the selection signals a and b, and a register for storing signals output from the synchronous control logic 241 ( 242 and an inverter 244 for inverting the reference clock.

The synchronization control logic 241 generates a counter having a predetermined period (CNT_MAX period) by using the reference clock generated by the reference clock generator 220, and generates a clock signal (RXC) error state based on the generated counter value. A latch start (STAT_LAT) signal for generating a final interrupt signal (RXC_INT) is generated by latching a clear start (STAT_CLR) signal and a clock signal start (RXC_STAT) value for clearing the register 242 to be stored. At this time, the error detection range may be adjusted by changing the maximum value (CNT_MAX value) of the counter.

Here, the constant period CNT_MAX consequently represents the allowable number of consecutive input errors of the clock signal RXC pulse.

In addition, the synchronization control logic 241 defines a counter using the generated reference clock, generates a clear start and a latch start signal at a specific value, and the clear start signal may appear two clocks later than the latch start signal.

The synchronous control logic 241 selects an input of a first selection signal and a reference clock for selecting an input of the clock signal RXC using the clear start (STAT_CLR) and latch start (STAT_LAT) signals that are generated control signals. Generates a second selection signal.

Each mux 243 outputs one of the input signals according to the input selection signal. For example, each mux 243 outputs a signal input from the first input terminal if the selection signal is high, and outputs a signal input from the second input terminal if the selection signal is high.

The clock signal processing scheme of the serial network module 240 will be described below.

The synchronization control logic 241 generates a counter having a predetermined period (CNT_MAX period) using the reference clock generated by the reference clock generator 220, and the synchronization control logic 241 detects an error using the generated counter. Set the range.

When the positive edge is detected within the error detection range, the synchronization control logic 241 latches the clock start signal to logic high.

Therefore, since high is input to the selection signals of the first and second muxes 243-1 and 243-2, the first mux 243-1 is a signal input to the first input terminal 1 according to an example. The in clock signal RXC is output and processes serial data based on the clock signal RXC input to the serial line.

At this time, the reference clock generated by the reference clock generator 220 is not output through the first mux 243-1.

On the other hand, if the clock start signal is initialized to a logic heavy rain by the clear start (STAT_CLR) signal generated every predetermined period (CNT_MAX), the synchronous control logic 241 is the first mux in the state that the clock signal (RXC) is not input The first select signal of 243-1 is prevented from being held at a logic high.

On the other hand, if the positive edge is not detected within the error detection range, the synchronous control logic 241 turns the clock start signal to a logic low.

Therefore, since low is inputted to the selection signals of the first and second muxes 243-1 and 243-2, the second mux 243-2 is inverted in the inverter 244 according to an example and the second input terminal is provided. The reference clock is output to (4), and the first mux 243-1 outputs an inverted reference clock, which is a signal input to the second input terminal 2, to process serial data based on the reference clock.

At this time, the clock signal RXC input to the first input terminal 1 through the first mux 243-1 is not output.

4 is a flowchart illustrating a clock signal processing method of a serial communication system according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the serial network module 200 of the receiving side of the serial communication system, that is, the receiving communication equipment, generates its own reference clock (S 100).

The serial network module 200 sets an error detection range having a certain period using the reference clock (S110). Here, the predetermined period may mean the allowable number of continuous input errors of the clock signal RXC pulse.

Thereafter, the serial network module 200 detects the clock signal RXC input through the serial line. According to an example, the serial network module 200 checks whether a positive edge is detected within an error detection range (S 120).

When the positive edge is detected within the error detection range, the serial network module 200 processes the serial data using a clock signal input through the serial line since the clock signal RXC is normally received through the serial line. (S 130).

On the other hand, the serial network module 200 indicates that an error has occurred in the clock signal RXC input through the serial line when the positive edge is not detected within the error detection range, that is, when the positive edge to be input at a predetermined period is not detected. In operation S140, the serial data is processed based on the reference clock generated by the reference clock generator 220.

At this time, the serial network module 200 inverts the reference clock such that skew between the data signal RXD and the reference clock received through the serial line does not occur.

In addition, the serial network module 200 initializes when the error detection range expires, that is, when a certain period passes, and checks again whether a positive edge is detected within the error detection range.

Although the present invention has been described in detail only with respect to the described embodiments, it will be apparent to those skilled in the art that various modifications and changes are possible within the technical spirit of the present invention, and such modifications and modifications belong to the appended claims.

As described above, according to the present invention, by adding a simple logic in the communication device of the receiving side of the serial communication system, if the clock signal (RXC) error occurs for reasons such as signal attenuation according to the length of the serial line, In addition to preventing problems from occurring due to errors, communication restrictions can be minimized.

Claims (9)

In a serial communication system, A transmission communication device for transmitting a clock signal TXC and a data signal TXD synchronized with the same through a data communication network; Receive a clock signal (RXC) and a data signal (RXD) in synchronization with each serial line through the data communication network, and a positive edge (via a serial line through which the clock signal (RXC) is received within a set error detection range). and a receiving communication device for processing the data signal using a reference clock generated by itself if a positive edge is not detected. The method of claim 1, wherein the receiving communication equipment, A reference clock generator for generating the reference clock; A serial transceiver for converting a clock signal RXC and a data signal RXD received through each serial line into a TTL signal; The serial data is processed using the TTL signal and the clock signal converted by the serial transceiver, an error detection range is set using the reference clock generated by the reference clock generator, and the positive edge is within the error detection range. If is not detected, the control logic for processing the serial data using the TTL signal and the reference clock, An HDLC controller for performing two-layer processing on the serial data processed by the control logic; And a microprocessor for processing a communication function in accordance with the serial data. The method of claim 2, wherein the control logic, And inverting said reference clock to process said serial data. The method of claim 1, wherein the error detection range is, And the number of pulses of the clock signal (RXC) corresponding to an input error allowable value. In a serial network module of a serial communication system, A reference clock generator for generating a reference clock; A serial transceiver for converting a clock signal (RXC) and a data signal (RXD) received through a serial line of the data communication network into a TTL signal, respectively; The serial data is processed using the TTL signal and the clock signal converted by the serial transceiver, an error detection range is set using the reference clock generated by the reference clock generator, and the positive edge is within the error detection range. If is not detected, the control logic to process the serial data using the TTL signal and the reference clock, And a HDLC controller for two-layer processing the serial data processed by the control logic. The method of claim 5, wherein the control logic, Synchronous control logic for outputting a first and a second selection signal depending on whether the positive edge is detected within the error detection range via the serial line; An inverter for inverting the reference clock; The clock signal RXC is input to a first input terminal, an inverted reference clock inverted by the inverter is input to a second input terminal, and when the first selection signal is input, the clock signal is outputted. And a second mux for outputting the inverted reference clock when a two selection signal is input. The method of claim 6, wherein the control logic, When the reference clock is input to a first input terminal, an inverted reference clock inverted by the inverter is input to a second input terminal, and when the first selection signal is input, the reference clock is input to the second input of the first mux. And a second mux for outputting to the terminal and outputting the inverted reference clock to the second input terminal of the first mux when the second selection signal is input. A method for processing a clock signal at a receiving side of a serial communication system, Generating a reference clock synchronized with a reference clock of the calling party transmitting data through the data communication network; Setting an error detection range of a predetermined period using the reference clock; Receiving a clock signal (RXC) and a data signal (RXD) over each serial line, Checking whether a positive edge is detected on the serial line within the error detection range, a) when the positive edge is detected, processes the data signal RXD using the clock signal RXC, b) if the positive edger is not detected, processing the data signal (RXD) using the generated reference clock. The method of claim 8, If the positive edge is not detected, blocking the clock signal RXC input through the serial line from being input; Inverting said reference clock to prevent skew between said reference clock and said data signal (RXD).

Images