KR20080034227A - Esd and eos protection circuit - Google Patents

Abstract

An ESD(Electrostatic Discharge) and an EOS(Electrical Over-Stress) protection circuits are provided to protect an inside core from ESD and EOS events by using an ESD detection circuit, an EOS detection circuit and a static electricity discharging circuit together and by controlling turn-on time of a clamping circuit on an on-time control circuit. A first detection circuit(310) is connected between a first power source line and a second power source line, and outputs a first detection signal by detecting an ESD event. A second detection circuit(320) is connected between the fist power source line and the second power source line, and outputs a second detection signal by detecting the EDS event or an EOS event. An on-time control circuit(330) activates a clam signal by responding to the detection signals, and latches the clamping signal to keep the active state until the charges caused by the EOS event or the ESD event is discharged. A clamping circuit(340) receives the clamping signal, and discharges the charges.

Description

ESD and EOS Protection Circuit {ESD and EOS Protection Circuit}

1 is a circuit diagram showing a conventional GGNMOS and GCNMOS.

2 is a conceptual diagram illustrating a structure of an electrostatic discharge protection circuit according to an embodiment of the present invention.

3 is a circuit diagram illustrating various embodiments of the ESD detection circuit of FIG. 2.

4 is a circuit diagram illustrating various embodiments of the EOS detection circuit of FIG. 2.

5 is a conceptual diagram illustrating an on-time circuit.

6 is a circuit diagram of an on-time control circuit using a MOS transistor.

7 is a circuit diagram of a clamping circuit.

8 is a circuit diagram of an electrostatic discharge protection circuit using a MOS transistor.

The present invention relates to an electrostatic discharge protection circuit, and more particularly, to an electrostatic discharge circuit that effectively protects the inner core from both electrostatic discharge (ESD) and electrical over-stress (EOS).

ESD is a discharge phenomenon in which a finite amount of charge moves rapidly between two objects with different potentials, which is discharged from hundreds of picoseconds (ps) to several microseconds (μs). Electrical shocks, such as leakage currents and abnormal transient voltages due to voltage, usually occur from several nanoseconds (ns) to several milliseconds (ms). As such, ESD and EOS differ in the electrical transient pulse width.

If ESD and EOS occur in products in the CMOS process, a circuit that can protect them is needed because it can cause the breakdown of thin insulating layers such as gate oxides. In addition, with the development of semiconductor technology, the integration density of integrated circuits greatly increases and power consumption tends to be easily exposed to ESD. When the thickness of the gate oxide film of the MOS transistor is 3 to 4 nm, the insulating layer may be destroyed even at a voltage of 3 to 4 V. Therefore, the need for a protection circuit capable of protecting the internal core from ESD and EOS is increasing.

Due to this need, various protection techniques have been developed to protect circuits from ESD.

FIG. 1 is a circuit diagram illustrating a gate-grounded NMOS transistor (GGNMOS) 100A and a gate-coupled NMOS transistor (GCNMOS) 100B that have been used in the related art.

GGNMOS (100A), which has a gate, a source, and a body connected to ground, uses a snap back phenomenon and has a very strong characteristic for EOS having a relatively long pulse duration, but a trigger that discharges through a transistor It is vulnerable to protecting the inner core from static electricity flowing into the inner core until the triggering voltage.

Complementing this, the GCNMOS 100B, which is widely used in recent years, uses a structure in which a silicide blocking layer (SBL) is removed. However, this structure is excellent for shocks with relatively short pulse durations, such as ESD, but ineffective for shocks with relatively short pulse durations, such as EOS.

The present invention has been proposed to improve the inefficiency of the above-described conventional static electricity protection circuit, and an object of the present invention is to provide a protection circuit that effectively protects an internal core during an ESD event and an EOS event.

In order to achieve the above object, the electrostatic discharge protection circuit according to an embodiment of the present invention includes a first detection circuit, a second detection circuit, an on-time control circuit, a clamping circuit. The first detection circuit is connected between the first power supply line and the second power supply line, and detects occurrence of an ESD event and outputs a first detection signal. The second detection circuit is connected between the first power line and the second power line, and detects the occurrence of the ESD event or the occurrence of the EOS event to output a second detection signal. The on-time adjustment circuit activates the clamp signal in response to the first detection signal or the second detection signal, and latches the clamping signal until the charge due to the ESD event or the EOS event is discharged. The clamping circuit is connected between the first power line and the second power line, receives the clamping signal, and discharges the charge due to the ESD event or the EOS event.

The first detection circuit may include a high pass filter that passes a high frequency component of the voltage caused by the ESD event and outputs the first detection signal using a capacitor and a resistor. It may include a capacitor.

The second detection circuit may discharge the charge generated by the negative EOS event or the negative ESD event when a negative EOS event occurs or a negative ESD event occurs.

The second detection circuit may include an NMOS transistor having a first power line connected to a drain, a gate, a source, and a body connected to a node, and a resistor connected between the node and the second power line. Silicon controlled rectifiers may be used instead of NMOS transistors. The second detection signal may be output through the node.

The on-time control circuit may activate a clamping signal when any one of the first detection signal and the second detection signal is activated, the first inverter for inverting the first detection signal, and the first inverter. And a third inverter for inverting the output signal of the output signal as the clamping signal, and a third inverter for inverting the clamp signal or the second detection signal and outputting the inverted signal as an input signal of the second inverter.

The clamping circuit may include an NMOS transistor connected to the first power line and a drain, connected to the second power line, a source and a body, and receiving the second detection signal through a gate.

An electrostatic discharge protection circuit according to an embodiment of the present invention includes a capacitor connected between a first power line and a first node, a first resistor connected between the first node and a second power line, and a drain of the first power supply. A first NMOS transistor connected to a line and having a gate, a source, and a body connected to a second node, a second resistor connected between the second node and the second power line, and the first node and the second node And a second NMOS transistor connected between the on-time controller, a drain connected to the first power line, a source and a body connected to a second power line, and a gate connected to the second node.

Here, the on-time controller includes a first PMOS transistor having a source and a body connected to the first power line, a gate connected to the first node, and a drain connected to a third node, and the source and body connected to the first PMOS transistor. A third NMOS transistor connected to a second power line, a gate connected to the first node, a drain connected to the third node, a source and a body connected to the first power line, and a gate connected to the first power line; A second PMOS transistor connected to a third node, a drain connected to the second node, a source and a body connected to the second power line, a gate connected to the third node, and a drain connected to the second node A fourth PMOS transistor connected with the source, a source and a body connected to the first power line, a gate connected to the second node, and a drain connected to the third node; The body may include a fifth NMOS transistor connected to the second power line, a gate connected to the second node, and a drain connected to the third node.

The ratio of the characteristic ratio of the first PMOS transistor and the characteristic ratio (W / L) of the third NMOS transistor is 2: 1, and the characteristic ratio of the second PMOS transistor and the characteristic ratio of the fourth NMOS transistor ( The ratio of W / L) may be 2: 1, and the ratio of the characteristic ratio (W / L) of the third PMOS transistor to the characteristic ratio (W / L) of the fifth NMOS transistor may be 2: 1.

Hereinafter, an electrostatic discharge protection circuit according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a conceptual diagram illustrating an electrostatic discharge protection circuit according to an embodiment of the present invention.

2, an electrostatic discharge protection circuit 200 according to an embodiment of the present invention may include an ESD detection circuit 210, an EOS detection circuit 220, an on-time control circuit 230, and a clamping circuit 240. ). Generally, driving power is applied to the first power line VDD, and the second power line VSS is grounded.

The ESD detection circuit 210 is connected between the first power line VDD and the second power line VSS to detect an ESD event, and when the ESD event is detected, the detection signal S1 is controlled on-time. Output to the circuit 230.

The EOS detection circuit 220 is connected between the first power supply line VDD and the second power supply line VSS to detect an EOS event. When the EOS event is detected, the EOS detection circuit 220 adjusts the detection signal S2 on-time. Output to the circuit 230. The EOS detection circuit 220 detects an EOS event and performs a complementary detection function to the ESD detection circuit 220 for an ESD event, and a negative ESD event or an EOS event having a negative polarity of an electric shock is generated. In the case of 1 power line, it also performs a clamping function to discharge the electric charge itself.

The on-time adjustment circuit 230 transmits the detection signals S1 and S2 provided from the ESD detection circuit 210 and the EOS detection circuit 220 to the clamping circuit 240. The on-time adjustment circuit 230 includes a configuration for latching the clamping signal S3. The on-time control circuit 230 continuously provides the clamping signal S3 to the clamping circuit 240 until the charge is sufficiently discharged in the ESD event and the EOS event so that the clamping circuit 240 is turned off early. By preventing the occurrence of an ESD event with a relatively short pulse duration, charges can be discharged even when an EOS event with a relatively long pulse duration occurs.

The clamping circuit 240 substantially discharges the charge due to the ESD event and the EOS event in response to the clamping signal S3 provided from the on-time control circuit 230.

3 is a circuit diagram illustrating various embodiments of the ESD detection circuit 210 of FIG. 2.

Referring to FIG. 3, the ESD detection circuit of the capacitor type 210A is implemented as an RC circuit in which the capacitor 211A and the resistor 212A are connected in series. High-pass filter that passes high-frequency components when the voltage between the first power line VDD and the second power line VSS is viewed as an input and the voltage across the resistor 212A is viewed as an output on the RC circuit. Filter). Therefore, when an ESD event with a relatively short pulse duration occurs, it is reflected by the voltage across the resistor 212A, which is effective for detecting an ESD event. The voltage across the resistor 212A is provided to the on-type control circuit 230 of FIG. 2 as the detection signal S1.

In the semiconductor process, since most devices are implemented using MOS transistors, the device may be implemented as a MOS capacitor type 210B. When using the PMOS transistor 211B, the drain and the source may be connected to the first power line VDD, and the gate may be connected to the resistor 212B.

4 is a circuit diagram illustrating various embodiments of the EOS detection circuit 220 of FIG. 2.

Referring to FIG. 4, the EOS detection circuit includes an NMOS transistor type 220A, a diode type 220B, a silicon controlled rectifier (SCR) type 220C, and the like. In the case of the NMOS transistor type 220A, the drain of the NMOS transistor 221A is connected to the first power line VDD, the gate, the source and the body are connected to the node N2, and the resistor 222A is connected to the node N2. ) And the second power line (VSS). The NMOS transistor type 220A has a structure similar to that of GGNMOS and has a relatively high characteristic ratio (W / L). In the event of an ESD event or ESO event, a breakdown phenomenon causes the internal parasitic NPN bipolar junction transistor to turn on and send a current that flows into the resistor 222A. The voltage of the node N2 is raised, and the voltage of the node N2 becomes the second detection signal S2. In the case of the diode type 220B, the cathode of the diode 221B is connected to the first power line VDD, the anode is connected to the node N2, and the resistor 222B is connected to the node N2 and the second power line. It is connected between the VSS, and may be implemented using the SCR 221C, such as a silicon controlled rectifier (SCR) type 220C.

As described above, when the EOS detection circuit is implemented, a positive EOS event having an electrical polarity of positive polarity may be effectively detected on the first power line, and when a negative EOS event having a negative polarity of electrical polarity occurs, the detection itself may be performed. Can be discharged. It also complements the ESD detection circuitry, which can detect ESD events or discharge charges generated by ESD events. When the EOS event or the ESD event is detected, the detection signal is output to the on-time control circuit 230 of FIG.

5 is a conceptual diagram illustrating an on-time circuit.

Referring to FIG. 5, the on-time circuit 230A receives a detection signal S1 of the ESD detection circuit and receives a signal inverted by the inverter 231A and a detection signal S2 of the EOS detection circuit. A portion 234A is included, and the latch portion 234A latches the detection signals S1 and S2 or the inverted signals of the signals and outputs the clamping signal S3 to turn on the transistors in the clamping circuit. Adjust While the conventional ESD protection circuit has not turned on the clamping transistor until the charge due to the ESD event or the EOS event is sufficiently discharged, the circuit according to the embodiment of the present invention is clamped by the latch portion 234A. By continually activating the signal S3, the charge caused by the ESD event and the EOS event can be effectively discharged. In the embodiment of Fig. 5, the detection signal S1 is inverted and the detection signal S2 is used as the clamping signal S3. However, this configuration may be modified according to the embodiment.

6 is a circuit diagram of an on-time control circuit using a MOS transistor.

The on-time control circuit of FIG. 6 implements the on-time control circuit of FIG. 5 using Morse transistors and includes an inverter 237B and a latch unit 238B. In a normal case where an ESD event or an EOS event does not occur, the detection signal S1 and the detection signal S2 remain at a low level voltage. If a positive ESD event or an ESO event occurs on the first power line, a high level voltage appears in the detection signal S1 and the detection signal S2, and the clamping signal S3 also becomes a high level voltage and is activated. When the charge is discharged through the clamping circuit, the detection signal S1 and the detection signal S2 are returned to the low level voltage, and the power lines VDD and VSS of the inverter 237B and the latch unit 238B are driven. Since the voltage is also stabilized, the clamping signal S3 returns to the low level voltage and the clamping circuit is turned off. When the on-time control circuit 230B is implemented using the PMOS transistors 231B, 233B, and 235B together with the NMOS transistors 232B, 234B, and 236B, the ratio of the characteristic ratio is 2 due to the difference in the mobility of holes and electrons. It is effective to set it to: 1.

7 is a circuit diagram of a clamping circuit.

Referring to FIG. 7, the clamping circuit is implemented as an NMOS transistor connected to a drain and a source, respectively, and receiving a clamping signal S3 through a gate. When the clamping signal S3 becomes a high level voltage, the clamping transistor is turned on to discharge the charges introduced into the first power line VDD by the ESD event or the EOS event to the second power line VSS. . The clamping circuit 240 may also be implemented using a PMOS transistor instead of the NMOS transistor.

8 is a circuit diagram of an electrostatic discharge protection circuit using a MOS transistor.

Referring to FIG. 8, a MOS capacitor type is used as an ESD detection circuit 310, and an EOS detection circuit 320 uses a MOS transistor type.

Since each component has already been described, the connection relation between the components will be described. The ESD detection circuit 310 is connected to the on-time control circuit 330 through the first node N1, and the voltage of the first node N1 is provided as the detection signal S1. The EOS detection circuit 320 is connected to the on-time control circuit 330 through the second node N2, and the voltage of the second node N2 is provided as the detection signal S2. The on-time control circuit 330 is connected to the clamping circuit 340 through the second node N2, and the voltage of the second node is provided to the clamping circuit 340 as the clamping signal S3.

Hereinafter, referring to FIG. 8, the overall operation when the ESD event and the EOS event are introduced will be described.

When a positive ESD event occurs in the first power line VDD, a high level voltage appears at the first node N1 and the second node N2. When the voltage of the first node N1 is provided to the on-type control circuit 330 as the detection signal S1, the voltage of the third node N3 becomes inverted at the third node N3 to become a low level voltage. Is reversed to again become the voltage of the second node N2 at the high level. The voltage of the second node N2 is latched by the on-time control circuit 330 until the charge introduced by the ESD event is discharged. Since the voltage of the second node N2 at the high level is input to the gate of the clamping transistor NM2, the clamping transistor NM2 is turned on so that the charges of the first power line VDD are first generated through the clamping transistor NM2. 2 is discharged to the power supply line VSS.

When charge flows into the first power line by the positive EOS event, it is detected by the EOS detection circuit 320 and the voltage of the second node N2 becomes high level. To drive.

When a negative ESD event or a negative EOS event occurs on the first power line, the voltage of the first power line is temporarily lower than the voltage of the second power line, so that the transistor NM1 and the clamping circuit in the ESO detection circuit 320 are temporarily blocked. Since a forward voltage is applied to the clamping transistor NM2 in 340, the charges introduced through the turned-on transistors NM1 and NM2 are discharged. As a result, the circuit can be protected against more severe electrical shocks than in general positive events.

Table 1

1 time Episode 2 3rd time CONVENTIONAL 5 V 5 V 5 V PRESENT 9 V 9 V 9 V

Table 1 shows the test results of the electrostatic discharge protection circuit according to an embodiment of the present invention manufactured by a semiconductor process.

Although the conventional protection circuit has an effect of about 5V, in the present invention, the internal core can be protected even when the positive ESD event and the positive EOS event are generated at about 9V, which is an improvement effect of about 80% or more. In addition, when the negative ESD event and the negative EOS event occurs, the excellent effect of about 20V.

Protect the internal core from both ESD and ESO events by using the ESO detection circuit together with the ESD protection circuit and the turn-on time of the clamping circuit in the on-time control circuit in accordance with an embodiment of the present invention. can do.

Claims (12)

A first detection circuit connected between the first power supply line and the second power supply line, and configured to detect occurrence of an ESD event and output a first detection signal; A second detection circuit connected between the first power line and the second power line, the second detection circuit detecting the ESD event occurrence or the EOS event occurrence and outputting a second detection signal; On-time for activating the clamp signal in response to the first detection signal or the second detection signal, and latching the clamping signal to maintain activation until the charge due to the ESD event occurrence or EOS event occurrence is discharged Regulating circuit; And And a clamping circuit connected between the first power line and the second power line, the clamping circuit receiving the clamping signal and discharging the charge due to the ESD event or the EOS event. Circuit. The method of claim 1, wherein the first detection circuit And a high pass filter passing through a high frequency component of the voltage caused by the ESD event and outputting the high frequency component as the first detection signal using a capacitor and a resistor. 3. The electrostatic discharge protection circuit according to claim 2, wherein the capacitor comprises a MOS capacitor. 2. The electrostatic discharge protection circuit of claim 1, wherein the second detection circuit discharges electric charges generated by the negative EOS event or the negative ESD event when a negative EOS event occurs or a negative ESD event occurs. . The method of claim 1, wherein the second detection circuit An NMOS transistor having a drain connected to the first power line and a gate, a source, and a body connected to a node; And A resistor coupled between the node and the second power line, And outputting a second detection signal through the node. The method of claim 1, wherein the second detection circuit A silicon controlled rectifier coupled between the first power line and a node; And A resistor coupled between the node and the second power line, And outputting a second detection signal through the node. The electrostatic discharge protection circuit of claim 1, wherein the on-time control circuit activates a clamping signal when one of the first detection signal and the second detection signal is activated. The circuit of claim 1, wherein the on-time adjustment circuit is A first inverter for inverting the first detection signal; A second inverter inverting the output signal of the first inverter and outputting the clamping signal; And And a third inverter for inverting the clamp signal or the second detection signal and outputting the clamp signal again as an input signal of the second inverter. The method of claim 1, wherein the clamping circuit And an NMOS transistor connected between the first power line and the drain, the second power line, the source and the body, and receiving the second detection signal through a gate. A capacitor connected between the first power line and the first node; A first resistor connected between the first node and a second power line; A first NMOS transistor having a drain connected to the first power line and a gate, a source, and a body connected to a second node; A second resistor connected between the second node and the second power line; An on-time controller connected between the first node and the second node; And a second NMOS transistor having a drain connected to the first power line, a source and a body connected to a second power line, and a gate connected to the second node. The method of claim 15, wherein the on-time control unit A first PMOS transistor having a source and a body connected to the first power line, a gate connected to the first node, and a drain connected to a third node; A third NMOS transistor having a source and a body connected to the second power line, a gate connected to the first node, and a drain connected to the third node; A second PMOS transistor having a source and a body connected to the first power line, a gate connected to the third node, and a drain connected to the second node; A fourth NMOS transistor having a source and a body connected to the second power line, a gate connected to the third node, and a drain connected to the second node; A third PMOS transistor having a source and a body connected to the first power line, a gate connected to the second node, and a drain connected to the third node; And a fifth NMOS transistor having a source and a body connected to the second power line, a gate connected to the second node, and a drain connected to the third node. The method of claim 15, The ratio of the characteristic ratio of the first PMOS transistor to the characteristic ratio (W / L) of the third NMOS transistor is 2: 1, The ratio of the characteristic ratio of the second PMOS transistor and the characteristic ratio (W / L) of the fourth NMOS transistor is 2: 1, And a ratio of the characteristic ratio of the third PMOS transistor to the characteristic ratio (W / L) of the fifth NMOS transistor is 2: 1.

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