KR20080032685A - Fabrication method of multi quantum dot nano device - Google Patents

Fabrication method of multi quantum dot nano device Download PDF

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KR20080032685A
KR20080032685A KR1020060098175A KR20060098175A KR20080032685A KR 20080032685 A KR20080032685 A KR 20080032685A KR 1020060098175 A KR1020060098175 A KR 1020060098175A KR 20060098175 A KR20060098175 A KR 20060098175A KR 20080032685 A KR20080032685 A KR 20080032685A
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quantum dot
oxide film
electron beam
dot nano
manufacturing
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KR101036692B1 (en
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최중범
승 준 신
정래식
이종진
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최중범
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/501—Wavelength conversion elements characterised by the materials, e.g. binder
    • H01L33/502—Wavelength conversion materials
    • H01L33/504—Elements with two or more wavelength conversion materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/505—Wavelength conversion elements characterised by the shape, e.g. plate or foil

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Abstract

A method for manufacturing a multi-quantum dot nano-device is provided to apply the multi-quantum dot nano-device to a quantum logic gate as well as a single electron multifunctional logic gate by forming a control gate at each of quantum dots. A conductive channel of a nanometer scale is formed by applying an electron beam lithography method or a photolithography method on an upper silicon layer(3) by using an SOI substrate(1). An impurity is doped onto the silicon substrate except for the conductive channel. A lower gate oxide layer(4) is formed by growing a silicon oxide layer through a thermal oxidation process. A single or multi-fine pattern(5,6,7) is formed perpendicularly to the conductive channel by applying the electron beam lithography method. A polysilicon layer is laminated by using a CVD method. A multi-ultra-fine polysilicon line(9-14) is formed at a lateral surface of the single or multi-fine pattern by performing an anisotropic etch process. An upper gate oxide layer(15) is formed by laminating the silicon oxide layer. An upper gate(16) is formed by depositing a metal.

Description

다중 양자점 나노소자 제조방법 {Fabrication Method of Multi Quantum dot Nano Device}Fabrication Method of Multi Quantum dot Nano Device

도 1은 본 발명에 의한 다중 양자점 나노소자를 나타낸 사시도이다.1 is a perspective view showing a multi-quantum dot nano device according to the present invention.

도 2는 본 발명에 의한 다중 양자점 나노소자의 제조공정 중, 나노미터 스케일의 전도채널이 상층 실리콘층에 형성된 상태를 나타낸 사시도이고,2 is a perspective view showing a state in which a conductive channel of a nanometer scale is formed in an upper silicon layer during a manufacturing process of a multi-quantum dot nano device according to the present invention;

도 3은 도 2의 단면도이다.3 is a cross-sectional view of FIG. 2.

도 4는 본 발명에 의한 다중 양자점 나노소자의 제조공정 중, 하층 게이트 산화막이 형성된 상태를 나타낸 사시도이고,4 is a perspective view showing a state in which a lower gate oxide film is formed during a manufacturing process of a multi-quantum dot nano device according to the present invention;

도 5는 도 4의 단면도이다.5 is a cross-sectional view of FIG. 4.

도 6은 본 발명에 의한 다중 양자점 나노소자의 제조공정 중, 전자빔 리소그래피 기법을 적용하여 상층 실리콘층에 형성된 전도채널에 대하여 직교하는 다중 NER 미세패턴이 형성된 상태를 나타낸 사시도이고,FIG. 6 is a perspective view illustrating a state in which a multi-NER micropattern orthogonal to a conductive channel formed in an upper silicon layer is formed by applying an electron beam lithography technique during a manufacturing process of a multi-quantum dot nanodevice according to the present invention;

도 7은 도 6의 단면도이다.7 is a cross-sectional view of FIG. 6.

도 8은 본 발명에 의한 다중 양자점 나노소자의 제조공정 중, CVD기법으로 폴리 실리콘층을 적층한 상태를 나타낸 사시도이고,8 is a perspective view showing a state in which a polysilicon layer is laminated by a CVD method during a manufacturing process of a multi-quantum dot nano device according to the present invention;

도 9는 도 8의 단면도이다.9 is a cross-sectional view of FIG. 8.

도 10은 본 발명에 의한 다중 양자점 나노소자의 제조공정 중, 이방성 식각을 통하여 다중 NER 미세패턴의 측면에 다중 극미세 폴리실리콘라인이 형성된 상태를 나타낸 사시도이고,FIG. 10 is a perspective view illustrating a state in which multiple ultrafine polysilicon lines are formed on sides of multiple NER micropatterns through anisotropic etching during a manufacturing process of multiple quantum dot nanodevices according to the present invention;

도 11은 도 10의 단면도이다.FIG. 11 is a cross-sectional view of FIG. 10.

도 12는 본 발명에 의한 다중 양자점 나노소자의 제조공정 중, CVD기법으로 실리콘 산화막을 적층하여 상층 게이트산화막이 형성된 상태를 나타낸 사시도이고,12 is a perspective view illustrating a state in which an upper gate oxide film is formed by stacking a silicon oxide film by a CVD method during a manufacturing process of a multi-quantum dot nano device according to the present invention;

도 13은 도 12의 단면도이다.FIG. 13 is a cross-sectional view of FIG. 12.

도 14는 본 발명에 의한 다중 양자점 나노소자의 제조공정 중, 금속을 증착하여 상층게이트가 형성된 상태를 나타낸 사시도이고,14 is a perspective view illustrating a state in which an upper gate is formed by depositing a metal during the manufacturing process of the multi-quantum dot nano device according to the present invention;

도 15는 도 14의 단면도이다.15 is a cross-sectional view of FIG. 14.

도 16은 본 발명에 의한 다중 양자점 나노소자의 전도채널에 이중 양자점이 형성된 대략적인 개념도이다.FIG. 16 is a schematic conceptual view of double quantum dots formed in a conduction channel of a multi-quantum dot nano device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

1: 하층 실리콘 기판1: Underlayer Silicon Substrate

2: 실리콘 산화막층2: silicon oxide layer

3: 상층 실리콘층3: upper silicon layer

4: 하층 게이트 산화막4: lower gate oxide film

5: NER 미세패턴15: NER Fine Pattern 1

6: NER 미세패턴26: NER fine pattern 2

7: NER 미세패턴37: NER fine pattern 3

8: 폴리실리콘층8: polysilicon layer

9: 극미세 폴리실리콘라인1 (하층 게이트)9: Ultra-fine polysilicon line 1 (lower gate)

10: 극미세 폴리실리콘라인2 (하층 게이트)10: ultra fine polysilicon line 2 (lower gate)

11: 극미세 폴리실리콘라인3 (하층 게이트)11: Ultra-fine polysilicon line 3 (lower gate)

12: 극미세 폴리실리콘라인4 (하층 게이트)12: Ultra-fine polysilicon line 4 (lower gate)

13: 극미세 폴리실리콘라인5 (하층 게이트)13: Ultra-fine polysilicon line 5 (lower gate)

14: 극미세 폴리실리콘라인6 (하층 게이트)14: Ultrafine Polysilicon Line 6 (Lower Layer Gate)

15: 상층 게이트 산화막15: upper gate oxide film

16: 상층게이트16: upper gate

실리콘 기판위에 양자점을 형성시키기 위한 대표적인 방법으로 전자빔 리소그래피 기법을 적용하여 나노미터 스케일의 미세 패턴으로 양자점을 제작하였다. 이러한 방법은 단일 미세 패턴을 이용한 단일 양자점 형성에는 적합하지만 다중 미세 패턴을 이용한 다중 양자점 제작에는 문제점을 유발한다. 다중 미세 패턴 형성시 패턴의 간격이 가까워질수록 전자의 간섭과 회절에 의한 근접효과(proximity effect)가 발생하여 균일한 패턴을 형성시키기가 어렵기 때문이다. 반면에 VLSI기술을 적용하여 극미세 패턴을 형성시키는 측벽(side wall)기법은 근접효과가 없으며 현재의 반도체 기술을 그대로 이용 할 수 있으나, 다중 극미세 패턴을 형성하기 위해서는 다중 적층공정과 이에 따른 식각공정의 반복은 공정 횟수를 증가시키는 단점을 지니고 있다. As a representative method for forming a quantum dot on a silicon substrate, an electron beam lithography technique was used to fabricate a quantum dot in a nanometer-scale fine pattern. This method is suitable for forming a single quantum dot using a single fine pattern, but causes a problem in manufacturing a multi-quantum dot using multiple fine patterns. This is because the closer the pattern spacing is when the multiple fine patterns are formed, the more proximity effect due to electron interference and diffraction occurs, making it difficult to form a uniform pattern. On the other hand, the side wall technique that forms the ultra fine pattern by applying the VLSI technology has no proximity effect and can use the current semiconductor technology as it is, but to form the multiple ultra fine pattern, the multiple lamination process and the etching accordingly Repetition of the process has the disadvantage of increasing the number of processes.

본 발명은 다중 양자점 나노소자 제조방법에 관한 것으로 제조공정 중, 다중 극미세 패턴 형성 기술이 핵심 공정으로서 전자빔 리소그래피 기법의 기술적 한계를 VLSI기술을 융합하여 극복 하고자 한다. 즉 전자빔 리소그래피 기법으로 형성된 다중 미세패턴위에 CVD기법의 적층 공정과 이방성 식각기술을 적용하여 다중 극미세 패턴을 형성시키고자 한다. The present invention relates to a method for manufacturing a multi-quantum dot nano device, and to overcome the technical limitations of the electron beam lithography technique by fusing the VLSI technique as the core process of the multiple ultra-fine pattern formation technology. In other words, a multi-micron pattern is formed by applying an CVD lamination process and an anisotropic etching technique on a multi-micron pattern formed by electron beam lithography.

본 발명의 다중 양자점 나노소자는 SOI 웨이퍼를 사용하여 다음과 같은 공정 단계를 통하여 제작한다. The multi-quantum dot nanodevice of the present invention is manufactured through the following process steps using an SOI wafer.

먼저 전자빔 리소그래피 기법을 적용하여 상층 실리콘층에 나노미터 스케일의 전도채널을 형성시키는 단계[도2]; 전도채널을 제외한 부분에 도핑공정을 통하여 소오스와 드레인을 형성시키는 단계; 열산화 공정으로 도펀트의 활성화 및 하층 게이트산화막을 성장시키는 단계[도3]; 전자빔 리소그래피 기법을 적용하여 다중 NER 미세 패턴을 전도채널에 직교하도록 형성시키는 단계[도4]; CVD기법으로 폴리실리콘층을 적층하는 단계[도5]; 이방성 식각을 통하여 다중 NER 미세패턴 측면에 다중 극미세 폴리실리콘라인을 형성시키는 단계[도6]; CVD기법으로 실리콘 산화막을 적층하여 상층 게이트 산화막을 형성하는 단계[도7]; 상층게이트를 형성시키기 위해 금속을 증착하는 단계[도8]로 다중 양자점 나노소자는 완성된다.First, forming a nanometer-scale conduction channel in the upper silicon layer by applying an electron beam lithography technique [FIG. 2]; Forming a source and a drain through the doping process except for the conductive channel; Activating the dopant and growing the lower gate oxide film by a thermal oxidation process [FIG. 3]; Applying an electron beam lithography technique to form multiple NER fine patterns orthogonal to the conduction channel [FIG. 4]; Stacking a polysilicon layer by CVD [Fig. 5]; Forming multiple ultrafine polysilicon lines on the side of the multiple NER micropatterns through anisotropic etching [FIG. 6]; Stacking a silicon oxide film by a CVD method to form an upper gate oxide film [FIG. 7]; A multi-quantum dot nanodevice is completed by depositing a metal to form an upper gate [Fig. 8].

본 발명의 다중 양자점 나노소자의 작용은 다음과 같이 이루어진다.The action of the multi-quantum dot nano device of the present invention is as follows.

제어게이트에 양의 전압을 인가하면 전도채널의 계면에 2차원 전자가스층(2DEG)을 형성시키고, 극미세 폴리실리콘라인1,2에 음의 전압을 인가하면 2DEG의 전자를 고갈시켜 터널링 장벽이 형성되고, 단일 양자점을 형성 시킬 수 있을 뿐만 아니라 극미세 폴리실리콘라인1,3,5에 음의 전압을 인가하면 이중 양자점이 형성된다. 여기서 극미세 폴리실리콘라인3에 인가하는 음의 전압의 크기에 따라 양자점간의 커플링을 제어할 수 있으며, 극미세 폴리실리콘라인2,4는 각각의 양자점의 제어게이트로 사용하게 된다. 드레인에 양의 전압을 인가하면 전자는 소오스에서 양자점1과 양자점2로 단전자 터널링과 쿨롱봉쇄(Coulomb blockade)현상을 일으키며 드레인으로 이동하게 된다.Applying a positive voltage to the control gate forms a two-dimensional electron gas layer (2DEG) at the interface of the conduction channel, and applying a negative voltage to the ultrafine polysilicon lines 1 and 2 depletes the electrons of the 2DEG to form a tunneling barrier. In addition, not only a single quantum dot can be formed, but a negative voltage is applied to the ultrafine polysilicon lines 1, 3 and 5 to form a double quantum dot. Here, the coupling between the quantum dots can be controlled according to the magnitude of the negative voltage applied to the ultrafine polysilicon line 3, and the ultrafine polysilicon lines 2 and 4 are used as control gates of the respective quantum dots. When a positive voltage is applied to the drain, electrons move to the drain, causing single-electron tunneling and coulomb blockade to the quantum dots 1 and 2 in the source.

본 발명에 의한 다중 양자점 나노소자는 각각의 양자점의 제어게이트(극미세 폴리실리콘라인2,4)를 지니고 있으므로 단전자 다기능 로직 게이트로서 적용할 수 있을 뿐만 아니라 양자 로직 게이트로 응용 할 수 있다.Since the multi-quantum dot nano device according to the present invention has a control gate (micro polysilicon lines 2 and 4) of each quantum dot, it can be applied not only as a single-electron multifunctional logic gate but also as a quantum logic gate.

Claims (3)

다중 양자점 나노소자의 제조방법에 있어서,In the method of manufacturing a multi-quantum dot nano device, SOI 기판을 사용하여 상층 실리콘층에 전자빔 리소그래피 또는 포토리소그래피 기법를 적용, 나노미터 스케일의 전도채널을 형성하는 단계; Applying an electron beam lithography or photolithography technique to the upper silicon layer using the SOI substrate to form a nanometer scale conducting channel; 상층 실리콘층의 전도채널을 제외한 부분에 소오스, 드레인 영역을 형성하기 위해 불순물을 도핑하는 단계; Doping an impurity to form a source and a drain region in portions other than the conductive channels of the upper silicon layer; 열 산화 공정을 통하여 실리콘 산화막을 성장시켜 하층 게이트 산화막을 형성하는 단계; Growing a silicon oxide film through a thermal oxidation process to form a lower gate oxide film; 전자빔 리소그래피 기법을 적용하여 상층실리콘에 형성된 전도채널에 직교하도록 음성 또는 양성 전자빔 감광막의 단일 또는 다중 미세 패턴을 형성하는 단계; Applying an electron beam lithography technique to form a single or multiple fine patterns of a negative or positive electron beam photosensitive film so as to be orthogonal to the conducting channel formed in the upper silicon; CVD기법을 통한 폴리실리콘층을 적층하는 단계; Stacking a polysilicon layer through a CVD technique; 이방성 식각을 통하여 단일 또는 다중 미세패턴 측면에 다중 극미세 폴리실리콘 라인을 형성하는 단계; Forming multiple ultrafine polysilicon lines on a single or multiple micropattern side through anisotropic etching; CVD기법을 통한 실리콘 산화막을 적층하여 상층게이트 산화막을 형성하는 단계; 금속을 증착하여 상층게이트를 형성하는 단계;를 포함하는 공정으로 이루어짐을 특징으로 하는 다중 양자점 나노소자 제조방법Stacking a silicon oxide film through a CVD technique to form an upper gate oxide film; Forming an upper gate by depositing a metal; multi-quantum dot nano device manufacturing method characterized in that the process comprising a 다중 양자점 나노소자의 제조방법에 있어서,In the method of manufacturing a multi-quantum dot nano device, SOI 기판을 사용하여 상층 실리콘층에 전자빔 리소그래피 또는 포토리소그래피를 적용, 나노미터 스케일의 전도채널을 형성하는 단계; Applying electron beam lithography or photolithography to the upper silicon layer using an SOI substrate to form a nanometer-scale conducting channel; 상층 실리콘층의 전도채널을 제외한 부분에 소오스, 드레인 영역을 형성하기 위해 불순물을 도핑하는 단계; Doping an impurity to form a source and a drain region in portions other than the conductive channels of the upper silicon layer; 열 산화 공정을 통하여 실리콘 산화막을 성장시켜 하층 게이트 산화막을 형성하는 단계; Growing a silicon oxide film through a thermal oxidation process to form a lower gate oxide film; CVD기법을 통한 폴리실리콘층을 적층하는 단계; Stacking a polysilicon layer through a CVD technique; 전자빔 리소그래피 기법을 적용하여 상층실리콘에 형성된 전도채널에 직교하도록 음성 또는 양성 전자빔 감광막의 단일 또는 다중 미세 패턴을 형성하는 단계; Applying an electron beam lithography technique to form a single or multiple fine patterns of a negative or positive electron beam photosensitive film so as to be orthogonal to the conducting channel formed in the upper silicon; 형성된 단일 또는 다중 미세패턴을 마스크로 하여 이방성식각을 실행하여 적층한 폴리실리콘층에 단일 또는 다중 폴리 실리콘 패턴의 하층게이트를 형성하는 단계; Forming an underlayer gate of a single or multiple polysilicon pattern on the stacked polysilicon layer by performing anisotropic etching using the formed single or multiple fine patterns as a mask; CVD기법을 통한 실리콘 산화막을 적층하여 상층게이트 산화막을 형성하는 단계; 금속을 증착하여 상층게이트를 형성하는 단계;를 포함하는 공정으로 이루어짐을 특징으로 하는 다중 양자점 나노소자 제조방법Stacking a silicon oxide film through a CVD technique to form an upper gate oxide film; Forming an upper gate by depositing a metal; multi-quantum dot nano device manufacturing method characterized in that the process comprising a 다중 양자점 나노소자의 제조방법에 있어서,In the method of manufacturing a multi-quantum dot nano device, 청구항1 또는 청구항2의 제조방법을 포함하여 하층 실리콘기판 밑면에 금속을 증착하는 공정을 포함하여 이루어짐을 특징으로 하는 다중 양자점 나노소자 제조방법 Method of manufacturing a multi-quantum dot nano device comprising the step of depositing a metal on the bottom of the lower silicon substrate including the manufacturing method of claim 1 or claim 2.
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KR100966264B1 (en) * 2008-01-17 2010-06-28 재단법인서울대학교산학협력재단 Single electron transistor with vertical quantum dot and fabrication method of the same
KR101009139B1 (en) * 2006-10-02 2011-01-18 충북대학교 산학협력단 Fabrication method for room temperature operating Si-SET
US8299520B2 (en) 2008-09-16 2012-10-30 Samsung Electronics Co., Ltd. Semiconductor devices including auxiliary gate electrodes and methods of fabricating the same

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KR20000073155A (en) * 1999-05-07 2000-12-05 최중범 SOI single electron transistor and its manufacture
KR100347673B1 (en) * 1999-12-31 2002-08-07 한국표준과학연구원 Method of fabricating single electron device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101009139B1 (en) * 2006-10-02 2011-01-18 충북대학교 산학협력단 Fabrication method for room temperature operating Si-SET
KR100966264B1 (en) * 2008-01-17 2010-06-28 재단법인서울대학교산학협력재단 Single electron transistor with vertical quantum dot and fabrication method of the same
US8299520B2 (en) 2008-09-16 2012-10-30 Samsung Electronics Co., Ltd. Semiconductor devices including auxiliary gate electrodes and methods of fabricating the same

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