KR20080025056A - Method and device for frame synchronization - Google Patents

Abstract

A method (10) for frame synchronization, the method (10) includes providing (30) a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller (410) and to at least one component (421); characterized by defining (20) a short synchronization period; processing (40) at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining (70) at least the clock line in a low power mode when the data line is substantially idle. A device (400) having frame synchronization capabilities, the device includes a clock signal provider (415) and at least one component (421) connected to a data line (430). The clock signal provider (415) is adapted to provide a high frequency clock signal over a clock line during a transmission of information over the data line. The at least one component (421) is adapted to process at least one signal conveyed over the data line during a short synchronization period to determine a presence of a synchronization error. The device (400) is further adapted to maintain at least the clock line in a low power mode when the data line is substantially idle. ® KIPO & WIPO 2008

Description

Frame Synchronization Method and Device {METHOD AND DEVICE FOR FRAME SYNCHRONIZATION}

The present invention relates to a device and a method for frame synchronization, and more particularly to a power efficient method and device for frame synchronization.

The complexity of integrated circuits has increased dramatically over the last decade. System on chip (SOC) and other multi-core integrated circuits are being developed to support various applications such as, but not limited to, multimedia applications, real-time applications, and the like.

Various protocols and buses have been developed for exchanging information between semiconductor components. These include, for example, an I ² C serial communication protocol, a serial peripheral interface (SPI) serial communication protocol, and a PowerWise® serial communication protocol.

The following patents and patent applications, all of which are incorporated herein by reference, provide a brief overview of various devices and methods for exchanging information. US Patent 6483847 to Ross, entitled "Arbitration scheme for a serial interface"; United States Patent Application Publication No. 20040049619 by Lin, titled "One wire serial communication protocol method and circuit"; United States Patent Application Publication No. 20040049611 by Kotlow et al., Entitled “Flexible port configuration and method”; US Patent Application Publication No. 20040148446 and US Patent 6697884 to Katsch, entitled “Communication protocol for serial peripheral devices”; And US Patent Application Publication No. 20030090939 to Perroni et al., Entitled " Nonvolatile memory device with parallel and serial functioning mode and selectable communication protocol. &Quot;

Many power management measures have been developed to reduce the power consumption of modern integrated circuits. These include, for example, clock frequency reduction, dynamic voltage scaling (DVS), dynamic body biasing, dynamic threshold scaling, adaptive body biasing, and the like.

The following patents and patent applications, all of which are incorporated herein by reference, provide a brief overview of various power management measures. US patent application 20040052098 to Burstein et al., entitled " digital voltage using current control "; US Patent Application 20030139927 to Gabara et al. Entitled "Block processing in a maximum a posteriori processor for reduced power consumption"; US patent application 20020000797 to Burstein et al., Entitled "Switching regulator with capacitance near load"; US Patent Application 20040025068 to Gary et al., Entitled "Methodology for coordinating and tuning application power"; And US Patent Application 20010038277 to Burstein et al. Entitled "Digital voltage regulator using current control."

There is a need to avoid collisions when multiple components share the same medium. Collisions can occur when two devices start transmitting over the line at substantially the same time.

Collision detection measures consume relatively power when they cause a collision and then try to reschedule another transmission.

There is a need to provide an efficient device and method for frame synchronization.

A device and method for frame synchronization as described in the appended claims are provided.

The invention will be more fully understood and appreciated from the following detailed description taken in conjunction with the drawings.

1 shows a device according to an embodiment of the invention.

2 shows a device according to another embodiment of the invention.

3 illustrates data line interfaces of master and slave components in accordance with an embodiment of the invention.

4 illustrates data line interfaces of a media access controller according to an embodiment of the invention.

5 illustrates a clock line interface in accordance with an embodiment of the invention.

6 illustrates an information frame according to an embodiment of the invention.

7-8 illustrate execution sessions of identification data commands in accordance with an embodiment of the invention.

9 illustrates a method for media access control in accordance with an embodiment of the invention.

10 is a flowchart of a method for exchanging signals over a data line in accordance with an embodiment of the invention.

11 is a flowchart of a method for media access control in accordance with an embodiment of the invention.

12 is a flowchart of a method for exchanging signals over a data line in accordance with an embodiment of the invention.

13 is a flow diagram of a method for media access control in accordance with an embodiment of the invention.

The following figures illustrate embodiments of the invention. They are not intended to limit the scope of the invention but to help understand some embodiments of the invention. Also note that not all the drawings are to scale.

1 illustrates a device 400 'in accordance with an embodiment of the invention. Device 400 ′ may include one or more integrated circuits and include, but not limited to, additional components such as a keypad, display, microphones, and the like. Device 400 may be a mobile device, such as a cell phone, personal data accessory, laptop computer, palm computer, game console, or the like. Device 400 'may also be a non-mobile device such as a desktop computer, workstation, server, or the like.

Device 400 ′ includes a first component 421 and a media access controller 410. Media access controller 410 is connected to first component 421 by data line 430 and clock line 440. Media access controller 410 conveniently provides a clock signal to clock line 440 for certain periods of time. Media access controller 410 does not provide any clock signal to clock line 440 for other periods.

Media access controller 410 may send and receive information over data line 430.

Conveniently, media access controller 410 provides high frequency clock signals via clock line 440 even during reception of data via data line 430. Conveniently, media access controller 410 can operate as a data transfer slave, providing high frequency clock signals via clock line 440. Accordingly, if media access controller 410 has granted access to a component, media access controller 410 provides clock signals during transmission of data by the component, even if the media access controller is the destination of the data. .

Media access controller 410 and first component 421 have various interfaces, such as interfaces 460 ', 470, 465, 475 shown in FIGS.

2 illustrates a device 400 according to another embodiment of the invention. Device 400 differs from device 400 'by including a plurality of components 422-427. For convenience of description, FIG. 2 shows seven components (denoted collectively 420) in addition to the media access controller 410.

Each component has two interfaces, but only the interfaces of the second component 422 are shown for convenience of description. 3 to 5 show these interfaces in more detail.

Conveniently, some of the components operate as masters and other components act as slaves. Typically, the amount of slaves is equal to the amount of masters, but this is not necessarily the case. Media access controller 410 may be considered a master, but this is not necessarily the case.

Note that some of these components may be included in a single integrated circuit, but this is not necessarily the case.

Conveniently, at least one component from components 420 is a power management component.

Conveniently, the master can send not only data but also commands (commands) to the slave and the slave can send data to its master. In addition, the component may send an interrupt request over the data bus.

According to an embodiment of the invention, device 400 includes a plurality of components, such as two power management integrated circuits, a graphics processing unit, and a baseband integrated circuit. The baseband integrated circuit includes a media access controller 410 and an application processor. For convenience, the first power management controller is a slave of the baseband integrated circuit and the second power management integrated circuit is a slave of the graphics processing unit.

Components 420 and media access controller 410 are connected to each other by a single data line 430 and by a single clock line 440.

The power consumption associated with data transfer over data line 430 is responsive to the clock frequency of the clock signal provided over clock line 440.

Typically, as well as the media access controller 410, each component includes some portion (such as the interface shown in FIGS. 3-5) supplied by a clock signal provided through the clock line 440. The power consumption of this portion can be reduced by providing a low frequency clock signal through the clock line or by not providing a clock signal through the clock line 440. Selective provision of the clock signal is also known as clock gating.

In accordance with an embodiment of the invention, other portions of components 420 may operate in various power modes regardless of or in response to a clock signal provided through clock line 440. Conveniently, each component receives clock signals from two or more sources, one of which is clock line 440.

Media access controller 410 may operate during low power modes when not providing a clock signal over clock line 440. For example, the data line 430 can be monitored to determine if one or more of the plurality of components 420 requests to transmit information over the data bus 430. In addition, media access controller 410 may determine to initiate a transmission sequence while media access controller 410 transmits information to one or more components 420.

Conveniently, media access controller 410 can access a set of instructions that are at least partially stored within computer readable medium 800, such as a memory unit. The memory unit may or may not be an internal memory unit, an external memory unit, a cache memory.

In accordance with an embodiment of the invention, media access controller 410 operates as a clock signal generator. 3 illustrates a clock signal generator 415 included in the media access controller 410. Note that this is not necessarily the case and the media access controller 410 can control another component (such as a remote clock signal generator) that selectively provides a clock signal.

Media access controller 410 may receive a clock signal from another source and optionally provide this clock signal to clock line 440. This configuration is shown in FIG.

Conveniently, the media access controller 410 monitors the data line 430 while (i) maintaining at least the clock line in a low power mode, and (ii) at least one of the plurality of components 420. Detect at least one media access request generated by (iii) and (iii) in response to the determination to transmit information by the media access controller itself or in response to the at least one detected media access request, at least the clock line is low power. It is configured to exit the mode and start the contention prevention period.

If the media access controller 410 determines that one of the components 420 should access the data line 430, this generates at least one media access grant.

Conveniently, the media access controller 410 or clock signal provider controlled by the media access controller 410 provides a clock to provide a high frequency clock signal over the data line, and prior to transmission completion and in response to the transmitted information. And when to reduce the rate substantially.

For convenience of description, each of the devices 400 and 400 ′ is referred to as a device 400. Those skilled in the art will appreciate that the communication protocol may be different (eg, the amount of media access request and authorization periods may vary due to different amounts of components in each device). Each of the methods 10, 100, 300 may be conveniently executed by any one of the devices 400, 400 ′.

Conveniently the device 400 has frame synchronization capabilities. Device 400 includes a clock signal provider 415 and a plurality of components 421-427, denoted 420, in connection. The plurality of components 420 are connected to the data line 430. Clock signal provider 415 is configured to provide a high frequency clock signal over clock line 440 during transmission of information over the data line. At least one of the plurality of components 420 is configured to process at least one signal transmitted over the data line for a short synchronization period to determine the presence of a synchronization error. In addition, device 400 is configured to maintain at least one clock line in a low power mode when the data line is in a substantially idle state.

Conveniently, media access controller 410 is configured to selectively provide high frequency clock signals via a clock line and to selectively grant access to the data line. At least one of the components 420 is configured to perform frame synchronization for a short synchronization period in response to the received short synchronization sequence.

Conveniently, information is transmitted over a single data line 440 at a transmission rate that can range from very low frequencies to high frequencies of tens of Mhz.

3 illustrates data line interfaces 460 and 465, in accordance with an embodiment of the invention.

Data interfaces 460 and 465 are connected to data line 430. Although interface 460 belongs to the master component and interface 465 belongs to the slave component, both are bidirectional.

Interface 460 includes an input buffer 462 and an output buffer 464. Output buffer 464 may receive data (“data-in”) from another portion of the master component and provide data to data line 430 (“data-out”). Output buffer 464 is controlled by a tri-state signal and by a read / write signal. The tri-state signal may cause the output buffer 464 to enter a high impedance state. An input of the input buffer 462 is also connected to the data line 430. The read / write control signal activates the input buffer 462 or output buffer 464.

The output of the output buffer 464 and the input of the input buffer 462 define the output nodes of the component.

Interface 465 includes an input buffer 466 and an output buffer 468. Output buffer 468 may receive data (“data-in”) from another circuit of the slave component and provide data to data line 430 (“data-out”). This is controlled by a tri-state signal and by a read / write signal. The tri-state signal may cause the output buffer 468 to enter a high impedance state. In addition, an input of the input buffer 466 is connected to the data line 430. The read / write control signal activates the input buffer 466 or output buffer 468.

4 illustrates a data line interface 460 'of the media access controller 410, in accordance with an embodiment of the invention.

The data line interface 460 'differs from the data line interface 460 by having a pull down resistor 461 connected to the output node of the media access controller 410. Pull down resistor 461 may be included in media access controller 410, but this is not necessarily the case.

According to other embodiments of the invention, at least one other of the components 420 is connected to (or includes) a pull down resistor.

According to another embodiment of the invention, at least one other component of the components 420 and / or the media access controller 410 are connected to a pull up circuit, instead of the pull up resistor 461. In this case, the component may provide a low level signal to indicate a request to transmit on the data line.

5 illustrates clock line interfaces 470 and 475 in accordance with an embodiment of the invention.

Clock interface 470 belongs to media access controller 410 and may include an output buffer 474 or a combination of input and output buffers 472 and 474, as shown in FIG. The input buffer 472 is conveniently connected to the clock signal generator 415, not through the clock line 440, to receive the clock signal (“clock-in”). Media access controller 410 optionally provides this signal to clock line 440. The output buffer 474 receives a clock-out signal that can be derived from the clock-in signal.

Conveniently, other components have an interface 475 that includes only an input buffer 476.

6 illustrates an information frame 500, in accordance with an embodiment of the invention.

Conveniently, once the transmission of the information frame 500 is finished, the media access controller 410 stops providing clock signals through the clock line 440 and accordingly clock circuits and circuits that are clocked by the clock lines. To enter low power mode.

The information frame 500 includes many parts. For convenience of description, the following description associates lengths (clock cycles, amount of bits) to each part. These lengths are non-limiting.

Information frame 500 begins with contention prevention bit 502 while media access controller 410 enters a high impedance state.

Referring to the example disclosed in FIG. 4, the output buffer 464 of the media access controller 410 enters a high impedance state and the pull down resistor 461 provides a pull down path to the data line 430.

Conveniently, if one of the components 420 asserts the data line 430 to indicate that it requests to access the data line 430, the media access controller 410 is still This request can be detected. Accordingly, the contention prevention bit 502 prevents simultaneous transmission by the media access controller 410 and one of the components 420.

Thus, during the contention protection period defined by the contention prevention bit, the data line carries a low value ("0") signal (data line 430 is successfully pulled by pull down resistor 461). If down), it may convey a high value (“1”) signal (if one of the components 420 indicates that it requests to access the data line 430).

If the pull down resistor 461 pulls down the data line 430 and one of the components 430 asserts the initial access request signal, the data line may enter an undefined state. Typically, this undefined condition can be eliminated by carefully selecting the value of the pull down resistor and the current of the initial access request signal.

The length of the contention free period is conveniently long enough to allow media access requests to be received by the media access controller 410 before beginning to transmit information over the data line 430.

Requests may be received during this contention prevention period for a variety of reasons, including late recognition by the component that a clock signal is being provided over clock line 440.

Conveniently, a component that issues an initial media access request by asserting a signal over data line 430 once the data access controller 410 detects that it has begun providing a clock signal over clock line 440. Negate the signal via line 430. This component provides additional request signals during the media access request period assigned to this component. Note that initial and additional requests are also referred to as media access requests.

The contention prevention bit 502 is followed by two synchronization bits 504 and 506. The value of bit 504 is different from the value of bit 506.

Conveniently, components 421-427 count clock cycles to synchronize. Synchronization errors can occur as a result of missed clock cycles or other errors related to synchronization based on counts.

Two synchronization bits of different values are required when the value of the contention prevention bit 502 is not known in advance. Components 420 monitor data line 430 to detect a change between two synchronization bits 504, 506.

The sync bit 506 is followed by the media access request bits 510-516. Each bit is associated with a single component. Components 420 are configured to transmit a media access request over a data line for predefined media access request periods. Conveniently, the media access bits are ordered in response to the transmission priority of the components, but this is not necessarily the case.

Conveniently, if the plurality of components 420 include K components capable of accessing a data line, K media access bits are required. K is a positive integer. K is equal to 1 in the configuration shown in FIG. K is equal to 7 in the configuration shown in FIG.

In addition, in a configuration such as that shown in FIG. 1, the media access controller 410 determines whether to access the bus so that the first component 421 can access the bus.

Note that the media access period for which each component can signal a media access request can be longer than 1 bit. The length of the media access period typically responds to the propagation period of the request via data line 430.

The media access request bits 510-516 are followed by a media access control decision period in which the media access controller determines who can access the data line 430. This decision period is represented by decision bit 518.

For convenience, the output buffer 464 of the media access controller 410 enters a high impedance state during the determination period.

Media access controller 410 may use a variety of prior art media access control measures. Allocation may be based on fixed priorities assigned to components, such as in fairness based measures. Various versions of round robin arbitration schemes can be used. Conveniently, the media access control decision period is short, such as one clock cycle.

Media access controller 410 is shown as making media access control decisions in units of a single information frame, although this is not necessarily the case. In accordance with another embodiment of the invention, a media access method and device may perform a media access control sequence to determine access of one or more components to data line 430 during a plurality of transmission sessions.

Conveniently, the components are configured to also know their media access request period and media access grant period, and the timing at which they are allowed to transmit information over data line 430. The component needs to know that it should wait some time (in the order of the associated media access grant period) until it can begin transmitting. According to another embodiment of the invention, the component may search for the header termination sequence and immediately begin transmission. Bits of a sequence comprising a zero bit followed by at least one high level bit followed by one sequence of high level bits are used, especially if only one bit is high and others are low during the media access control grant bits. Can be.

Decision bit 518 is followed by media access control grant bits 520-526. If the media access controller 410 determines which of the components 420 should access the data line 430, it provides an grant signal for the corresponding media access control period.

The media access controller 410 may decide to block access to the data line 430 for its own use or in consideration of the system and in response does not send an acknowledgment signal to any of the components of 420.

The media access control grant bits 520-526 are followed by a header end bit 528.

In addition to the header end bit 528 or instead of the header end bit 528 according to an embodiment of the invention, an information frame end bit (or sequence) is transmitted.

The header is followed by at least one of command bits, address bits, and data bits. The order of the bits as well as the length of each bit sequence may vary. Some bit sequences may be transmitted during one transmission sequence and other bit sequences may be transmitted during other transmission sequences. For example, data bits can only be sent when certain commands are being executed.

According to various embodiments of the invention, some bit sequences may be transmitted by one component and other bit sequences may be transmitted by another component. For example, during the transmission sequence, the master component can access the data line 430 and then send a READ command to the slave component, which then sends the requested data to the master component. This may happen even if the media access controller 410 did not grant access to the slave component.

Header end bits 528 are followed by command type bits 530 and 532, destination address bits 550-556, additional command bits 534-540, and data bits 560-566. Is assumed.

Table 1 shows exemplary commands, in accordance with an embodiment of the invention. Note that many power management measures including multiple power modes can be applied by using the above mentioned device and information frames. For example, the amount of power modes can exceed two, and power management can respond to various parameters such as temperature, and the like.

Note that various commands, including the MODE command, can be defined by the user. The MODE command conveniently initiates execution of predefined instructions and / or initiates retrieval of predefined values. A single MODE command is conveniently associated with settings that would otherwise require many commands to be exchanged between the various components.

In Table 1, the row "AD" indicates whether the component sending the command also sends data.

The row "DT" in Table 1 indicates whether the component sending the command also sends the address of the destination component.

During supply voltage / clock frequency increase / decrease commands, the data (denoted Y *) may include the address of the register to be updated. The data update can be commanded.

Also note that some commands may be followed by a response (delivered via data line 430) that indicates whether the command is complete or the like.

Table 1

Command Sub-command Command type bit Additional command bit AD DT Reading 1 byte data read 00 000 Y N Reading 2-byte data read 00 001 Y N Reading 3-byte data read 00 010 Y N Reading 4-byte data read 00 011 Y N

entry Write 1 byte data 00 100 Y Y entry 2-byte data read 00 101 Y Y entry 3-byte data read 00 110 Y Y entry 4-byte data read 00 111 Y Y mode Standby mode-reduced power consumption 10 000 N N

mode Enter panic mode-increase voltage to high level 10 001 N N DVS Which voltage regulator is set to what value 11 0010 Supply voltage / clock frequency increase Increase the contents of any register to be a predefined voltage and / or supply clock increment 11 0011 Y Y * Supply voltage / clock frequency reduction Reduce the contents of any register to result in a predetermined voltage and / or supply clock reduction 11 0100 Y Y * Data identification Read the identification value of the component 11 1000 Y N

Link test Request to receive a predefined value to test the device 11 1110 synchronization synchronization 11 1111

7-8 and Table 2 illustrate execution sessions of data command identification, in accordance with an embodiment of the invention. The second component 422 requests access to the data line 430 to receive identification information ID3 of the third component 423. The second component 422 sends an initial media access request during the contention protection period. Note that the fifth component 425 also requests access to the data line 430 but has a lower priority than the second component 422. The fifth component 425 sends an initial media access request by the media access controller 410 to initiate the provision of clock cycles.

TABLE 2

Clock cycle Transmitted signal Send component CK0 Initial request to access media Second component 422 CK1-CK2 Sync bits MAC CK3 none The first component 421 does not request access to the data line. CK4 Media access request The second component 422 requests to access the data line.

CK5-CK6 none The third and fourth components 423, 424 do not request access to the data line. CK7 Media access request The fifth component 425 requests access to the data line. CK8-CK9 none The sixth to seventh components 426-427 do not request access to the data line. CK10 None (high impedance decision bit) The MAC makes media access control decisions. CK11 none The MAC does not grant access by the first component 421.

CK12 Media access authorization The MAC does not grant access to the second component 422. CK13-CK18 none The MAC does not grant access to the third to seventh components 423-427. CK19 Header Termination Bit (528) MAC CK20-CK21 Command Type Bits = 10 Second component 422 CK22-CK23 Address (ID3) of the third component Second component 422

CK24-CK27 Additional command bits = 0000 Second component 422 CK28 none Spacer bits CK29-CK36 ID3 The third component 423 provides its identification value ID3. CK37 No clock cycle The clock line is idle until the next transmit sequence

9, 10 and 11, it is noted that some of the following steps are optional and other steps may be added to the method, within the spirit of the invention. For ease of explanation, several steps have been illustrated in light of the examples shown in the previous figures. These descriptions are not intended to limit the scope of the illustrated method.

9 is a flowchart of a method 100 for media access control, in accordance with an embodiment of the invention.

According to an embodiment of the invention, the plurality of components are connected to the data line 430 and to the clock line 440 in addition to the media access controller 410. For simplicity of explanation, the following description refers to a plurality of component configurations.

The method 100 begins by associating media access priorities with at least one component connected to a data line. These associations can be performed in advance, can be fixed and / or can be changed dynamically.

Step 110 is followed by step 120 of allocating media access request periods to at least one component connected to the data line. The assignment allows the media access controller to determine which component issued the media access request.

Step 120 is followed by step 125 of assigning media access grant periods to components connected to the data line.

Step 125 is followed by a sequence of steps that are repeated during the operation of media access controller 410.

The sequence is adapted to maintain the data line 430 while maintaining at least the clock line in the low power mode to detect at least one initial media access request generated by the at least one component connected to the data line and the clock line. Begin by monitoring 130. Conveniently, no clock signal is provided over clock line 440 during step 130. Conveniently, the component is one of a plurality of components connected to the data line, in addition to the media access controller.

Following step 130, at least the clock line is brought out of the low power mode and in response to the at least one detected media access request or in response to the determination of the media access controller 410 transmitting information over the data line, Step 140 begins with the contention protection period.

Conveniently, the media access controller 410 or clock signal provider 415 controlled by the media access controller provides the clock signal during steps 140-210.

Conveniently, media access controller 410 does not transmit information during the contention protection period. In accordance with an embodiment of the invention, the output buffer 464 of the media access controller 410 enters a high impedance state and the pull down transistor 461 provides a pull down path to ground.

Conveniently, the contention protection period is one clock cycle long.

Once the contention protection period ends, the method enters a synchronization period that includes transmitting synchronization signals, as shown by step 160. Conveniently, the synchronization signals comprise at least one bit of the first value followed by at least one bit of another value.

Subsequent to step 160, the media access controller 410 receives 170 at least one media access request for a sequence of media access request periods. Conveniently, each media access request period is associated with a component connected to a data line. Note that steps 170 and 190 are not necessarily performed if the media access controller 410 decides to transmit data.

Subsequent to step 170, step 180 is followed by determining which component (or media access controller 410 itself) can access the data line 430. The determination typically responds to receipt of at least one media access request.

Following step 180, during the at least one media access grant period, a step 190 of sending at least one media access grant by the media access controller 410 is followed. Conveniently, each media access authorization period is associated with a component connected to a data line. If the media access controller 410 decides to access the data line 410, it does not provide any media access grant. Note that various media access authorization measures may be used. For example, media access controller 410 may transmit a coded number that indicates the number (identification) of the selected device during one or more media access grant periods. Referring to the example disclosed in FIG. 2, three bit codes may be used to identify any of the components 421-427.

Following step 190, in response to the media access grant, step 200 of transmitting information over the data line. The information may include data, commands, addresses, or a combination thereof. Typically, data bits precede command bits and address bits.

Conveniently, the transmitted information includes power control information. The power control information may include power control commands as well as power control data. The commands may include, for example, a request to increase (or reduce) the supplied power (and / or supply clock cycle rate), a request to read some value indicative of power consumption, and the like. These values may reflect the temperature of the components, the supply clock frequency supplied to the components 420, the voltage supplied to the components 420, and the like.

The supply clock signal is conveniently different from the clock signal supplied via the clock line 440. The supply clock signal typically clocks portions of components that are not involved in data exchange via data line 440.

Following step 200, step 210 of transmitting the end frame sequence is followed. Following step 210, step 130 follows. The end frame sequence may be transmitted instead of or in addition to the frame header end sequence.

10 is a flowchart of a method 300 of exchanging signals over a data line, in accordance with an embodiment of the invention.

The method 300 begins by granting 310 access to a data line shared by a plurality of components. Conveniently, step 310 includes monitoring the data line to detect one or more requests to access the data line, and in response, increasing the clock rate. Conveniently, step 310 may include one or more of steps 110-190 of method 100.

Step 310 is followed by steps 320 and 330. Step 320 includes transmitting information over the data line at a transmission rate responsive to the first clock rate.

Step 330 includes determining when to substantially reduce the clock rate prior to completion of the transmission and in response to the transmitted information.

Steps 320 and 330 are followed by step 340 of discontinuing the provision of clock signals via the clock line. Step 310 is followed by step 310.

11 is a flowchart of a method 10 for media access control, in accordance with an embodiment of the invention.

The method 10 begins by defining 20 a short synchronization period. Conveniently, a short synchronization period is defined in response to the maximum expected synchronization error. According to an embodiment of the invention, the maximum expected synchronization error is the length of N clock cycles and the short synchronization period does not exceed (N + 1) clock cycles.

Following step 20, steps 30 and 40 are followed. Step 30 includes providing a high frequency clock signal on the clock line during transmission of the information via the data line, which is conveniently connected to the media access controller and to the at least one other component. Step 30 is followed by step 70. Conveniently, high frequencies exceed 10Mhz. High frequencies can reach 25Mhz and above.

Step 40 includes processing at least one signal delivered over the data line for a short synchronization period to determine the presence of a synchronization error. At least one signal may define a synchronization sequence. Note that at least some of this sequence may be transmitted for a short synchronization period. Conveniently, the synchronization sequence comprises at least one bit of the first value followed by at least one bit of another value.

If a synchronization error is detected, then step 40 is followed by step 50 of correcting the detected synchronization error. Subsequent to step 50, step 60 is followed by transmitting information via the data line or receiving information via the data line.

Following step 60, step 70 is followed by maintaining at least the clock line in a low power mode when the data line is substantially idle.

12 is a flow diagram of a method 600 of exchanging signals over a data line in accordance with an embodiment of the invention.

The method 600 begins by granting access 610 to the data line 430 by the media access controller 410, where the data line 430 is shared by the plurality of components 420. do.

Step 610 is followed by steps 620 and 630. Step 620 includes transmitting information over the data line at a transmission rate in response to the clock signal rate, in response to the access grant.

Step 630 includes providing a clock signal over clock line 440 by media access controller 410.

Conveniently, step 610 includes monitoring the data line 430 to detect a request to access the data line 430 and to increase the clock signal rate in response.

13 is a flowchart of a method 700 for media access control, in accordance with an embodiment of the invention.

The method 700 may be used to authorize access to the data bus 430 shared by the plurality of components 420 and the media access controller 410.

The method 700 includes preliminary steps 120, 125. Step 120 includes assigning, by the media access controller, media access request periods to the plurality of components 420. Step 125 includes assigning, by the media access controller, media access authorization periods to the plurality of components 420.

Steps 120 and 125 are followed by a sequence of steps that can be repeated for each media access control cycle.

The sequence begins by detecting 710, by the media access controller, at least one initial media access request generated by at least one of the components 420. Step 710 may also include steps 130 and 140.

Step 710 is followed by monitoring 720 of data line 430 to detect media access requests that occurred during media access request periods.

Subsequent to step 720, step 180 is followed by determining which component (or media access controller 410 itself) can access the data line 430. These components are called selected components.

Subsequently, step 180 is followed by selectively issuing at least one grant signal 730 during the media access grant period associated with the selected component. The grant signal responds to the determination of step 180.

Conveniently, the media access request periods form a continuous sequence of media access request periods.

Conveniently, the media access grant periods form a continuous sequence of media access grant periods.

According to various embodiments of the invention, each of the above mentioned methods 10, 100, 300, 600, 700 executes a set of instructions stored by a device or in particular in computer readable medium 800. It can be executed by a media access controller. This medium is not necessarily an internal memory unit, as shown in FIG. This medium may include magnetic storage devices (such as magnetic tape, diskettes, disk drives), optical storage devices (such as DVD, CD), and the like. Media access controller 410 may execute the method in cooperation with other components such as storage units, buses, and the like.

Conveniently, a computer readable medium having a set of instructions stored thereon is provided. A set of instructions are shared by the media access controller and at least one other component such that when executed by the media access controller, the component transmits information over the data line at a transmission rate responsive to the first clock rate. Allow the media access controller to grant access to the data line to be established.

In addition, the set of instructions allows the media access controller to determine when to substantially reduce the clock rate before completion of the transmission and in response to the transmitted information.

Conveniently, a computer readable medium having a set of instructions stored thereon is provided. The set of instructions, when executed by the media access controller, cause the media access controller to generate at least one media access grant in response to the at least one media access request.

In addition, a set of instructions may cause media access while maintaining at least the clock line in a low power mode to detect at least one media access request generated by the at least one component connected to the data line and the clock line. Let the controller monitor the data line; When a media access controller or at least one component requests access to a data line, at least the clock line comes out of low power mode to start a contention prevention period.

Conveniently, a computer readable medium having a set of instructions stored thereon is provided. A set of instructions, when executed by the media access controller, provide the high frequency clock signal through the clock line during transmission of information through the data line coupled to the media access controller and the at least one component. Or control).

In addition, the set of instructions may include at least one signal transmitted over the data line for a short synchronization period to determine the presence of a synchronization error when the data line is substantially idle and to at least keep the clock line in a low power mode. The media access controller to process it.

Conveniently, the set of instructions causes the media access controller 410 to grant access to the data line 430 shared by the plurality of components 420 and at a transmission rate responsive to the clock signal rate. Provides a clock signal through clock line 440 during transmission of information over the data line.

Conveniently, the set of instructions causes the media access controller to determine which component to access the data line; Assign media access request periods to the plurality of components 420; Assign media access authorization periods to the plurality of components 420; Detect at least one initial media access request generated by at least one of the components 420; Monitor data line 430 to detect media access requests generated during media access request periods; Selectively issue at least one grant signal during a media access grant period associated with the selected component.

Variations, modifications, and other implementations of those described herein will occur to those skilled in the art within the spirit and scope of the claimed invention. Accordingly, the invention is defined not by the foregoing illustrated description, but by the spirit and scope of the following claims.

Claims (21)

A method (10) for frame synchronization comprising providing (30) a high frequency clock signal on a clock line during transmission of information via a data line coupled to a media access controller and at least one component. Defining a short synchronization period (20); Processing (40) at least one signal transmitted over the data line during the short synchronization period to determine the presence of a synchronization error; Maintaining (70) at least the clock line in a low power mode when the data line is in a substantially idle state. The method of claim 1, further comprising correcting (50) the detected synchronization error. 3. The method of claim 1 or 2, further comprising granting access to the data line. 4. The method of any one of claims 1 to 3, wherein a short synchronization period is defined in response to a maximum expected synchronization error. The method of claim 1, wherein the maximum expected synchronization error is a length of N clock cycles and the short synchronization period does not exceed (N + 1) clock cycles. 6. The method of claim 1, wherein at least one master component and at least one slave component are coupled to the data line. 7. The method of claim 1, wherein the at least one information frame comprises power control information. 8. The method of any of the preceding claims, wherein the high frequency is greater than 10 Mhz. The frame synchronization according to claim 1, wherein the synchronization sequence to be transmitted at least partially during the short synchronization period comprises at least one bit of the first value followed by at least one bit of another value. Way. A device 400 with frame synchronization capabilities, comprising a clock signal provider 415 configured to provide a high frequency clock signal via a clock line 440 during transmission of information via a data line 430. At least one configuration coupled to the clock line 440 and to the data line 430 and configured to process at least one signal transmitted through the data line for a short synchronization period to determine the presence of a synchronization error Further comprising an element, wherein the device is configured to maintain at least the clock line in a low power mode when the data line is in a substantially idle state. The device of claim 10, wherein the at least one component is further configured to correct the detected synchronization error. 12. The device of claim 10 or 11, wherein the device (400) is further configured to grant access to the data line. The device of claim 10, wherein the device defines the short synchronization period in response to a maximum expected synchronization error. The device of claim 10, wherein the maximum expected synchronization error is a length of N clock cycles and the short synchronization period does not exceed (N + 1) clock cycles. 15. The device of any one of claims 10-14, wherein the plurality of components (420) comprise at least one master component and at least one slave component. The device of claim 10, wherein the at least one information frame includes power control information. The device of claim 10, wherein the high frequency is greater than 10 MHz. A device 400 comprising a data line 430 and a clock line 440 coupled to a media access control device 410 and at least one other component, And further comprising a media access controller 410 configured to selectively provide high frequency clock signals on the clock line and to selectively grant access to the data line, wherein at least one component responds to a received short synchronization sequence. Wherein the device is configured to perform frame synchronization for a short synchronization period. 19. The device of claim 18, wherein the at least one component is further configured to correct the detected synchronization error. 20. The device of claim 18 or 19, wherein the device (400) is further configured to grant access to the data line. 21. The device of any of claims 18-20, wherein the device defines the short synchronization period in response to a maximum expected synchronization error.

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