KR20080020316A - Method for forming semiconductor memory device - Google Patents

Abstract

A method for forming a semiconductor memory device is provided to ensure a margin for mis-align between a ground selection line and a common source line by implementing apertures having a width using dry etching. Gate patterns are formed on a semiconductor substrate(100). A nitride layer(120) for covering the gate patterns is formed. An oxide layer(130) for the nitride layer is formed. By executing dry etching, a first aperture for exposing the semiconductor substrate is formed between the gate patterns. By executing wet etching, a second aperture(160) larger than the first aperture is formed on the oxide layer.

Description

Method of forming a semiconductor memory device {METHOD FOR FORMING SEMICONDUCTOR MEMORY DEVICE}

1 is a plan view illustrating a part of a NAND flash memory device.

2 is a cross-sectional view taken along the line II ′ of FIG. 1 to explain a method of forming a semiconductor memory device according to the prior art.

3A to 3C are cross-sectional views taken along the line II ′ of FIG. 1 to explain a method of forming a semiconductor memory device according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

110: ground select line 120: nitride film

130: oxide film 140: photoresist pattern

150: first opening 160: second opening

170: common source line

The present invention relates to a method of forming a semiconductor memory device, and more particularly to a method of forming a semiconductor memory device having a common source line.

Generally, a semiconductor memory device is a volatile memory device in which stored information is lost as electricity is stopped, and a nonvolatile memory device that can maintain stored information even when electricity is cut off. Are distinguished. Flash memory devices are nonvolatile memory devices that combine the advantages of Programmable and Erasable Programmable Read Only Memory (EPROM) and Electrically Erasable Programmable Read Only Memory (EEPROM). It is a highly integrated device developed. Flash memory devices may be classified into a NOR type and a NAND type. The NAND type may be integrated into a plurality of memory cells and be controlled as a single string, which is advantageous for high integration.

1 is a plan view illustrating a part of a NAND flash memory device.

Referring to FIG. 1, active regions ACT are defined by an isolation layer provided on a semiconductor substrate. The NAND flash memory device includes a cell array consisting of a plurality of cell strings. Each cell string is composed of a ground select transistor connected in series between a source region and a drain region, a string select transistor, and a plurality of memory cells connected in series between the ground select transistor and the string select transistor. The cell array includes a plurality of ground select lines (GSL), string select lines (SSL), ground select lines (GSL) and a string select line across the active area ACT. Word lines WL between them. A common source line CSL is provided between the ground select lines GSL. The common source line CSL electrically connects the source regions. A bit line contact DC is provided between the string select lines SSL. The bit line contact connects a bit line with a drain region of the string select line SSL transistor.

2 is a cross-sectional view taken along the line II ′ of FIG. 1 to explain a method of forming a semiconductor memory device according to the prior art.

Referring to FIG. 2, ground select lines 20 are formed on a semiconductor substrate 10. The ground select lines 20 may include a tunnel oxide layer 22, a floating gate 24, an inter-gate insulating layer 26, a control gate 27, a hard mask layer 28, and a spacer 29. . A nitride film 30 is formed to cover the ground select lines 20. An oxide film 40 is formed to cover the nitride film 30. After the photoresist pattern 40 is formed on the oxide layer 40 to perform a dry etching process, a common source line 50 is formed between the ground select lines 20. As non-volatile memory devices are highly integrated, mis-alignment occurs between the common source line 50 and the ground select lines 20, thereby causing an electrical short. As a result, the reliability of the semiconductor memory device may be degraded.

An object of the present invention is to provide a method of forming a semiconductor memory device with improved reliability.

The method of forming the semiconductor memory device may include forming gate patterns on a semiconductor substrate, forming a nitride layer covering the gate patterns, forming an oxide layer covering the nitride layer, and performing a dry etching process. Forming a first opening exposing the semiconductor substrate therebetween and performing a wet etching process to form a second opening larger than the first opening in the oxide film.

The method of forming the semiconductor memory device may further include forming a spacer on sidewalls of the gate patterns before forming the nitride layer.

The first opening may be formed to have a width equal to or less than one third of the gate pattern interval.

The second opening may be formed to have a volume three times or more than that of the first opening.

The method of forming the semiconductor memory device may further include forming a buffer oxide film on the semiconductor substrate by performing a thermal oxidation process before forming the nitride film.

Forming the oxide film may include forming by chemical vapor deposition.

In the wet etching process, an etching rate of the oxide layer may be greater than an etching rate of the buffer oxide layer.

The gate patterns may include ground select lines.

The method of forming the semiconductor memory device may further include forming a common source line in the second opening between the ground selection lines after the wet etching process.

Hereinafter, a method of forming a semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art.

In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.

In the following embodiment, a ground selection line and a common source line of a nonvolatile memory device are described as an example. However, the technical idea of the present invention can be applied to other semiconductor memory devices.

3A to 3C are cross-sectional views taken along the line II ′ of FIG. 1 to explain a method of forming a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3A, ground select lines 110 are formed on the semiconductor substrate 100. The ground select lines 110 may include a tunnel oxide layer 112, a floating gate 114, an inter-gate insulating layer 116, a control gate 117, a hard mask layer 118, and a spacer 119. have. The tunnel oxide layer 112 may be formed by a thermal oxidation process. The floating gate 114 and the control gate 117 may include polysilicon formed by a chemical vapor deposition method. The inter-gate insulating layer 116 may include an oxide-nitride-oxide formed by a chemical vapor deposition method. The inter-gate insulating layer 116 has a butting contact 115 connecting the floating gate 114 and the control gate 117. The hard mask layer 118 may include a silicon nitride layer formed by a chemical vapor deposition method. The spacer 119 may be formed by depositing an insulating material and then performing a front anisotropic etching process.

The nitride film 120 is formed to cover the ground select lines 110. The nitride film 120 may be formed by a chemical vapor deposition method. Before the nitride layer 120 is formed, a thermal oxidation process may be performed to form a buffer oxide layer (not shown) on the semiconductor substrate 100. The buffer oxide layer (not shown) may be formed to reduce stress that may occur between the nitride layer 120 and the semiconductor substrate 100.

An oxide film 130 is formed to cover the nitride film 120. The oxide layer 130 may be formed by chemical vapor deposition. The oxide film 130 may be formed by depositing a silicon oxide film and then performing a planarization process. The photoresist pattern 140 is formed on the oxide film 130. The first opening 150 is formed by performing a dry etching process on the oxide layer 140 using the photoresist pattern 140 as a mask. The dry etching process may be performed to etch the semiconductor substrate 100 by about 10Å. The first opening 150 may have a width less than one third of the interval between the ground selection lines 110. Accordingly, a margin of misalignment that may occur between the ground select lines 110 and the common source line may be secured.

Referring to FIG. 3B, an ashing process is performed to remove the photoresist pattern 140. The second opening 160 is formed by performing a wet etching process on the oxide layer 140. The wet etching process may use a solution containing hydrofluoric acid (HF). The second opening 160 may have a volume of three times or more than the first opening 150. When the buffer oxide layer is formed, an etching rate of the oxide layer 140 formed by a chemical vapor deposition method may be greater than an etching rate of the buffer oxide layer formed by a thermal oxidation process.

Referring to FIG. 3C, a common source line 170 is formed in the second opening 160. The common source line 170 may be formed by depositing a conductive material in the second opening 160 and then performing a planarization process of exposing the oxide layer 140. The common source line 170 may be formed of tungsten (W) or polysilicon. Since the upper surface of the common source line 170 is wide due to the wet etching process, a metal contact formed in a subsequent process may be easily contacted with the common source line 170.

According to an embodiment of the present invention, a dry etching process is performed to form a first opening having a width less than one third of a ground selection line interval. Thus, a margin for misalignment between the ground select line and the common source line can be ensured.

Due to the wet etching process, the width of the upper surface of the common source line is large, so that the metal contact may be easily contacted with the common source line in a subsequent process.

Claims (9)

Forming gate patterns on the semiconductor substrate; Forming a nitride film covering the gate patterns; Forming an oxide film covering the nitride film; Performing a dry etching process to form a first opening exposing the semiconductor substrate between the gate patterns; And And forming a second opening larger than the first opening in the oxide layer by performing a wet etching process. The method according to claim 1, Before forming the nitride film, Forming a spacer on sidewalls of the gate patterns. The method according to claim 1, And the first opening is formed to have a width equal to or less than one third of the gate pattern interval. The method according to claim 2, And the second opening is formed to have a volume three times or more larger than that of the first opening. The method according to claim 1, Before forming the nitride film, Forming a buffer oxide film on the semiconductor substrate by performing a thermal oxidation process. The method according to claim 1, Forming the oxide film comprises forming by a chemical vapor deposition method. The method according to claim 5, In the wet etching process, the etching rate of the oxide layer is larger than the etching rate of the buffer oxide layer. The method according to claim 1, And the gate patterns comprise ground select lines. The method according to claim 8, After the wet etching process, And forming a common source line in the second opening between the ground select lines.

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