KR20080019656A - Technique for reducing silicide non-uniformities by adapting avertical dopant profile - Google Patents

Abstract

By modifying the vertical dopant concentration in deep drain and source regions, the reaction behavior during the formation of metal suicide regions 217 may be controlled. For this purpose, an increased dopant concentration is formed around a target depth (Xs) for the metal suicide interface, thereby reducing the reaction speeds and thus improving the uniformity of the resulting metal suicide interface. ® KIPO & WIPO 2008

Description

TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES BY ADAPTING AVERTICAL DOPANT PROFILE}

Overall, the present invention relates to the field of fabrication of integrated circuits, and more particularly to semiconductor devices having metal-silicide portions on a semiconductor to reduce the resistance of the semiconductor regions.

In modern ultra high-density circuits, device features continue to decrease to improve performance and functionality. Reducing feature sizes inevitably involves some problems that can in part attenuate the gain obtained by reduced sizes. Usually, for example, reducing the feature size of the transistor element can cause the channel resistance of the transistor element to be reduced, resulting in higher drive current capacity and increased switch speed of the transistor. In reducing the feature size of the transistor elements, increasing the electrical resistance of the conductive lines and the contact area of regions having peripheral transistor elements, such as drain and source regions, for example connecting the transistor regions, increases, Since the cross-sectional area of these lines and regions decreases as feature size decreases, it is a major issue. The cross-sectional area determines the resistance or contact area of each line according to the combination of physical properties of the material including conductive lines and contact areas.

The problems can be addressed for a critical feature size typical in this respect, such as an extension of the channel of the transistor's channel region formed under the gate electrode between the source and drain regions of the field effect transistor. It is also called Critical Dimension (CD). Reducing this channel's extension, commonly referred to as channel length, is related to the fall and rise times of the transistor element because the capacitance between the gate electrode and the channel is smaller and the resistance is reduced by the shorter channel. The performance of the device can be greatly improved. Reducing the channel length also involves reducing the size of the conductive lines, usually made of polysilicon, such as the gate electrode of the field effect transistor, and the contact regions that make electrical connections to the drain and source regions of the transistor, As a result, the possible cross-sectional area for charge carrier transfer is reduced. As a result, conductive lines and contact regions have higher resistance values unless the reduced cross-section is compensated for by increasing the electrical properties of the material forming the lines and contact regions, such as gate electrode and drain and source contact regions. Shows.

Therefore, it is very important to increase the physical properties of the conductive regions substantially comprising a semiconductor material such as silicon. For example, in modern integrated circuits, individual semiconductor devices such as field effect transistors, capacitors, and the like are primarily based on silicon, where the individual devices are connected by silicon lines and metal lines. The resistance of the metal lines can be improved by replacing commonly used aluminum with, for example, copper and copper alloys, which process engineers improve upon the electrical properties of silicon-containing semiconductor lines and when semiconductor contact areas are needed. Will face.

Referring to FIGS. 1A and 1B, an exemplary process for manufacturing an integrated circuit, including, for example, a plurality of MOS transistors, is described in detail below to illustrate problems associated with improving electrical properties of silicon-containing semiconductors. Will be.

In FIG. 1A, the semiconductor structure 100 includes a substrate 101, such as a silicon substrate, that forms a field effect transistor 110 of a particular conductivity type, such as, for example, an N-channel transistor or a P-channel transistor. It is configured to include. The transistor element 110 includes a isolation structure 113 formed of an insulating material, such as silicon dioxide, silicon nitride, and the like, and defines an active region 112 in the substrate 101. The gate electrode 115 is formed on the gate insulating layer 118 separating the gate electrode 115 from the active region 112. On both sides of the gate electrode 115, spacer elements 116 made of, for example, silicon dioxide or silicon nitride are positioned. In the active region 112, source and drain regions 114 including respective extensions 114a are formed and show appropriate side dopant profiles required for connection to the channel region 111. Applying an appropriate control voltage to 115 forms a conductive channel between the drain and source regions 114.

As mentioned above, the gate length of transistor element 110, denoted 115L, determines the length of the channel of transistor 110, and thus, as already pointed out, has a significant impact on the electrical properties of transistor element 110. Where the gate length is reduced and thus the overall size of the transistor 110 is reduced, the gate electrode 115 and the drain and source may be reduced as the area capable of charge carrier transfer is reduced, even if heavily doped. It will increase the resistance of the contact regions 114b of the regions 114.

The process for forming the general semiconductor structure 100 may include the following steps. After forming the isolation structure 113 using known photolithography etching and deposition techniques, an implant process is performed to create the vertical dopant profile required for the active region 112. Subsequently, a gate insulating layer 118 is formed according to the design of the device structure. The gate electrode 115 is then formed by, for example, patterning the polysilicon layer using complex photolithography and etching techniques. An additional implant step is then performed to form the source and drain extensions 114a in the source and drain regions 114, and the spacer elements 116 can be formed using deposition and anisotropic etching techniques. . The spacer element 116 can be used as an implant mask for the next implant process where the dopant is implanted into the active region 112 to form the source and drain regions 114, thereby providing the high dopant required for these regions. Form concentrations.

In Fig. 1A, it should be noted that the dopant concentration changes in the horizontal direction, i. Although the dopant profile of the source and drain regions 114 is shown as a region with sharp boudary, the dopant profile is actually a suitable non-localized characteristic in the depth direction x of the implant process, It is continuously changed by subsequent annealing steps that are done to activate the atoms and heal the crystalline damage caused by the implant step. Usually, the dopant profile should be selected in accordance with certain parameters that match the transistor element 110. For example, short gate lengths, and thus short channel lengths, usually require a "shallow" dopant profile to reduce the so-called "short channel effect". Thus, the highest concentration in the x direction may be located near the surface, i.e., in the contact region 114b, and may decrease significantly as it deepens.

FIG. 1B schematically illustrates the vertical dopant profile of the drain and source regions 114, as may be commonly seen in conventional transistor elements having a gate length 115L of about 100 nm and smaller. In FIG. 1B, the horizontal axis indicates an extension along the depth direction x, for example the depth x _s specified in FIG. 1A is shown in dashed lines. The vertical axis represents the dopant concentration on a logarithmic scale. The type of dopant in the drain and source regions 114 is determined by the type of transistor element represented by the transistor 100. Thus, as shown in FIG. 1B, very high concentrations of dopant may be present at or near the surface 114b and may decrease rapidly with depth, resulting in a concentration at a specific depth x _s This value can be very small.

As pointed out above, in complex applications, metal silicide in the source and drain regions 114 and the gate electrode, even though the dopant concentration is very high in the contact region 114b and in the gate electrode 115, is noted. It is common to further reduce the sheet resistance of these regions by forming.

1C illustrates a semiconductor structure 100 at a further stage of the manufacturing process. Here, metal silicide regions 117 are formed in the drain and source regions 114, and metal silicide regions 119 are formed in the gate electrode 115. Generally, the metal silicide regions 117 and 119 are formed of refractory metal, such as, for example, cobalt, nickel, titanium, platinum, or the like or combinations of two or more suitable metals. In order to form the metal silicide regions 117 and 119, at least one metal layer of a certain thickness is usually used for a suitable deposition technique, for example, physical vapor deposition, chemical vapor deposition, etc. The thickness of the initial layer can be chosen so as to conformally deposit it, for example to obtain a vertical extension in the silicide regions 117 as needed for the device. Although the high capacitance metal silicide of the gate electrode 115 may be considered desirable to reduce the resistance of the gate electrode 115, the regions 117 and 119 are formed during a common manufacturing process, The thickness of region 119 is related to the specific thickness of silicide region 117.

In another approach, a more complicated manufacturing process can be used to separate the forming steps of the regions 117 and 119. It can be estimated that the design thickness of the metal silicide region 117 can be given by the depth x _s . Based on the desired depth x _s and based on the known reaction behavior of the refractory metal or metal, as far as the underlying silicon is considered, the thickness or metal silicide region 117 finally obtained in principle is determined by the corresponding control process parameters. Can be controlled by parameters such as the thickness of the initial layer to initiate diffusion of the refractory metal or metals into silicon, the temperature, and the subsequent thermal process time, thereby producing a metal silicide compound.

In practice, the metal silicide regions 117 may have some roughness, shown as 117a, which characteristics may vary greatly depending on the device and process features. For example, in some process regimes, P-channel transistors having a structure similar to that of the transistor 110 are more noticeable in terms of roughness 117a for nickel silicide compared to those formed of N-channel transistors in the same semiconductor structure 100. Can show. In contrast, for nickel platinum silicide, the roughness 117a may be more pronounced for N-channel transistors than for P-channel transistors. Due to the non-uniformity of the metal silicide region 117, ie the roughness 117a-which can also be varied in other transistor types of the same structure-due to the significant parameter changes between the different elements, for example drain and source Due to the increased leakage currents in the region 114, it can be observed that the electrical parameters of the semiconductor structure 100 are lowered. In addition, as the size of semiconductor devices continues to decrease, the non-uniformity of the metal silicide regions 117 may negatively affect the performance of later generations of devices with much tighter set process tolerances.

In view of the situation as described above, there is a need for an improved technique that obviates or at least reduces the effects of one or more of the identified problems.

The following provides a brief summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not a very detailed overview of the invention. It is not intended to identify key words or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some simple concepts as a prerequisite before the detailed description that follows.

The present invention relates to a technique for forming metal silicide regions in heavily doped semiconductor regions including silicon, wherein the roughness of the metal silicide region is significantly reduced to provide a more precisely defined interface to the surrounding semiconductor regions. Can be. For this purpose, the vertical dopant concentration in the silicon-containing semiconductor region is adjusted to provide increased dopant concentration, compared to conventional source drain regions, at or near the depth at which the interface of the metal silicide region should be formed. Can be. The increased dopant concentration can significantly change the diffusion of the metal during the formation of the metal silicide region.

According to one embodiment of the present invention shown, one method comprises identifying a target depth of a metal silicide region formed in a silicon-containing semiconductor region formed over a substrate. The method further includes forming a dopant profile in the silicon-containing semiconductor region along the depth direction of the silicon-containing semiconductor region based on the target depth to obtain the highest value of the local dopant concentration around the target depth. Eventually the metal silicide region is formed based on the target depth.

According to another embodiment of the present invention, one method includes identifying a first target depth of a metal silicide region with respect to a drain and source region of a first specific transistor type formed in one or more substrates. The method further includes forming drain and source regions of a first specific transistor type in one or more substrates having a dopant profile based on a first target depth, wherein the dopant profile is adjusted with respect to the depth direction of the one or more substrates. When the first target depth is reached, to obtain a dopant concentration that increases as the depth increases. As a result, the metal silicide region is formed in the drain and source regions of the first specific transistor type based on the first target depth.

The invention will now be described with reference to the following figures, wherein like numerals represent like components.

1A is a schematic cross-sectional view of a conventional transistor prior to forming a metal silicide region.

1B is a graph schematically showing the dopant profile in the depth direction of the conventional transistor shown in FIG. 1A.

1C is a schematic cross-sectional view of the transistor of FIG. 1 after forming metal silicide regions in accordance with the prior art.

2A-2B are graphs (Fig. 2A) showing an example of the diffusion dependence of refractory metals with respect to penetration depth in the presence of exemplary conventional dopant concentrations, and dopants in accordance with the illustrated embodiment of the present invention. Graph showing an example of concentration.

2C-2F are schematic cross-sectional views of transistor elements during various fabrication process steps in accordance with an embodiment of the present invention.

3 is a schematic cross-sectional view of a semiconductor device including two transistor elements having different target depths to form metal silicide regions in accordance with an embodiment of the present invention.

4 is a schematic cross-sectional view of a transistor element during the fabrication process, wherein the dopant concentration may be adjusted in accordance with an embodiment of the present invention based on epitaxial silicon deposition.

The invention can be applied in various modifications and alternative forms, the specific embodiments of which are shown and described in detail by way of example in the drawings. The description of specific embodiments herein is not intended to limit the invention to the specific form disclosed, and on the contrary, it is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the claims. It should be understood that it is intended to be included.

Hereinafter, embodiments of the present invention will be described. In the interest of clarity, not all forms of actual embodiments are described in the detailed description. In the development of any such practical embodiment, the specifics of numerous embodiments must be determined in order to achieve the specific goals of the developers, for example system related or business related constraints, which may of course vary with each embodiment. Will be recognized. These development efforts are also complex and time consuming, but nevertheless, gaining from this disclosure will be a daily routine for those skilled in the art.

Hereinafter, the present invention will be described with reference to the drawings. Various structures, systems and elements are schematically depicted for purposes of illustration only and so as not to obscure the present invention with details known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative embodiments of the present invention. The terms and phrases used herein should be understood and interpreted to have a meaning consistent with the terms and phrases by those skilled in the art. The use of terms or phrases consistently herein is intended to avoid the definition of particular terms or phrases, that is, definitions that differ from the general and customary meanings understood by those skilled in the art. In order for a term or phrase to extend to a particular meaning, that is, to have a meaning different from that understood by one of ordinary skill in the art, such particular definition may be described and disclosed herein in a manner in which a particular definition is directly and explicitly provided for that term or division. will be.

In general, the present invention is based on the concept that the diffusion of refractory metal in the doped semiconductor region is affected by the dopant profile in the semiconductor region. Thus, by appropriately applying the dopant profile of the drain and source regions of the transistors formed based on silicon, the kinematic behavior during the chemical reaction to form metal silicide regions in the drain and source regions will be affected. More detailed defined interfaces can be obtained between the metal silicide region and the semiconductor region, thereby reducing any adverse effects that may be caused by the metal silicide interface roughness, as shown in FIG. 1C.

Without intending to limit the invention in the following description, the diffusion of refractory metal atoms in a substantially crystalline semiconductor region may show a similar diffusivity, particularly when the dopant and refractory metal atoms are contemplated within the semiconductor region under consideration. It is recognized that it is very influenced by the existence of. In this regard, the diffusivity can be transported by atoms during the formation of metal silicides in crystalline silicon regions where the reaction kinetics are very different depending on the specific temperature, for example the type of metal used and the temperature at which the chemical reaction starts. It should be understood as averaged random distance. In the case where additional dopants are present in the silicon region, the reaction rate to form metal silicides can be very affected by the additional dopants, which depends on a crystal-characteristic mechanism where the diffusion of dopants and refractory metal atoms is substantially the same. This is especially true when refractory metals and dopant materials can exhibit similar diffusion behavior in silicon.

In FIG. 2A, very quantitative to illustrate more clearly the mechanisms known to have a significant impact on the formation of metal silicide regions in silicon-containing semiconductor crystals, with respect to the dopant concentration in the silicon crystal and the degree of diffusion of the metal. And is shown in a simple manner. However, it should be understood that the present invention relates to various novel manufacturing methods for manufacturing semiconductor devices, regardless of the exact mechanism involved.

In FIG. 2A, curve A qualitatively displays typical conventional dopant concentrations along the depth direction, indicated as x and drawn as the horizontal axis. As can be clearly seen from FIG. 2A, the dopant concentration at depth zero, ie the concentration at the surface of the drain or source region, has a moderately high value, for example, on the order of 10 ¹⁹ atoms per cm ² , As will be greatly reduced, the corresponding dopant concentration at the specific depth x _s indicated by curve C will be several orders of magnitude smaller than the size at depth 0, for example 10 ¹⁴ -10 ¹⁵ . As such, the depth x _s may represent the target depth for the interface between the metal silicide and silicon in the drain or source region.

Curve B of FIG. 2A qualitatively displays the corresponding diffusivity of the refractory metal in silicon for a given process condition during the silicidation process. For example, curve B schematically shows the diffusion rate of nickel over a particular process temperature while forming nickel silicide regions in heavily doped source or drain regions. Since there is a large amount of dopant atoms at the surface, i.e., at a depth of zero, the initial diffusion of the metal atoms may be moderately low, where some fluctuations in the diffusion behavior of the metal atoms may be at depth zero, which is a surface irregularity. And the like. Because of the moderately low diffusion rate, the chemical reaction will also proceed at an appropriate rate and any fluctuations present at the beginning of the reaction front will be directed towards the material, ie along the depth direction x, at substantially the same appropriate reaction rate. . However, as the depth increases, the concentration of dopants can decrease significantly, resulting in a significant increase in the diffusion of the corresponding metal atoms, which means that any fluctuations initially present in the reaction plane are now “amplified because of the significantly increased reaction rate. "do. As a result, due to this "amplification effect" due to a significantly increased reaction rate, at depth x _s , the metal silicide face can have significant roughness. According to the present invention, the dopant concentration can be adjusted to increase the dopant concentration at or near the target depth x _{s as} compared to the dopant concentration shown in FIG. 2A and, accordingly, the reaction behavior during the silicidation process. The roughness of the metal silicide face is significantly reduced as a result.

FIG. 2B is a graph schematically illustrating the difference between the controlled dopant concentration in the silicon-containing semiconductor region with respect to the depth direction x and the diffusivity of the corresponding refractory metal obtainable by the controlled dopant concentration. Here, curve D represents the controlled dopant area of the drain or source area, with the increased dopant concentration concentrated near the target depth x _s . The expression “increased” in this respect means that at least near the portion of x _s , when the target depth x _s approaches from the left, that is, when the depth increases, at least the target so that the dopant concentration increases as the depth increases. It is to be understood that at depth xs, there is an increase in dopant concentration. In other words, a local maximum of dopant concentration for the depth direction x is at or near the target depth x _s . As such, the expression "near" or "close to" should be understood that the distance of the local maximum to the target depth x _s is less than the distance of the local maximum to the location represented by depth 0. Dopant concentrations will even apply to conventional devices. In some embodiments, the expression “close to” or “nearby” is intended to represent a depth of about 80-120% from being at a target depth of 100%, for example, in FIG. local maximum values are located at a shown by an arrow, the depth x _m, such a local maximum value is compared with the distance to the target depth x _s from the surface portion, that is, depth 0 to positions close to the target depth x _s This is because the distance of the local maximum to the target depth x _s is very small.

Curve E schematically shows the corresponding reaction rate for the dopant concentration as shown, for example, in curve D, where a qualitatively appropriate low reaction rate can be obtained, which decreases with each increase of each dopant concentration. This is because the diffusion of refractory metals is reduced. As a result, some initial variations in the metal silicide face may not be substantially "amplified" and may be reduced in accordance with the "smoothing effect" of the reduced reaction rate. Thus, the metal silicide facet can show a reduced roughness and thus a better defined interface to the remaining silicon region at the target depth x _s .

It will be appreciated that dopant concentrations and diffusivity D, E merely illustrate exemplary properties and that other dopant profiles may be made in accordance with the present invention. For example, curves G and H schematically illustrate corresponding dopant profiles in the depth direction that may be suitable for forming a metal silicide interface in a more localized manner. The dopant concentrations shown in FIG. 2B refer to a single dopant species having a particular conductivity type and its profile is substantially determined by this single dopant species. For example, an N-channel transistor can have high concentrations of N-doped drain and source regions, where the amount of counter dopants in the vicinity of target depth x _s is negligible, at least target depth x Near _s , effects on dopant profiles may also be neglected. In other embodiments, curves D, G, and H may be expressed as "accumulated" dopant concentrations that take into account two or more different ion types, and may include dopants of the same or different conductivity type. For example, high concentrations at the target depth x _s can be made by providing a certain amount of doping and doping the surrounding area of the target depth x _s with a counter conductive dopant to obtain an adequately low effective dopant concentration depending on the electrical behavior. It still has an increased dopant concentration with respect to the actual number of dopant atoms per unit volume and the effect on the diffusion of any metal used to form the metal silicide region. Thus, unless expressly indicated otherwise in the specification and claims, "Dopant concentration" should be understood in the latter sense.

2c, another embodiment according to the present invention will be described in detail below. 2C schematically depicts a semiconductor device 200 comprising a substrate 201, which represents any suitable substrate for forming silicon-based semiconductor elements. For example, the substrate 201 may represent a bulk silicon substrate having a crystalline silicon layer formed thereon. In other cases, the substrate may represent a silicon on insulator (SOI) type substrate on which a silicon-containing semiconductor layer is formed over an insulating layer. The semiconductor device 200 may further include a transistor element 210 including an isolation structure 213 to define an active region 212 in the substrate 201, ie in a silicon-containing semiconductor layer. . A gate electrode 215 is formed on the active region 212, and is separated from the active region 212 by the gate insulating layer 218. The channel region 211 is formed under the gate insulating layer 218. The semiconductor regions in which the deep drain and the source region are to be formed are separated from left to right. In addition, extension regions 214a may be formed adjacent to the gate electrode 215 and form offset spacers 216a on its sidewalls. Arrow x indicates depth direction x, which is substantially perpendicular to the initial surface of substrate 201. That is, the depth direction x is well defined for any surface topology formed on the substrate 201 during the process of fabricating the device 200, and as an example, the rear of the substrate 201 defines the verticality of the depth direction x. Can be used. For the sign of the depth direction x indicated by the arrow, it will be understood that increasing the depth starts from the surface portion, as the portion 214b has a value of zero and is directed towards the substrate 201. As a result, the target depth x _s can be defined as the distance between the initial surface 214b and the desired portion of the interface of the metal silicide region formed adjacent to the gate electrode 215. The " origin " in the depth direction x is located above the surface 214b, and when the semiconductor devices 200 are considered, it is necessary to form selectively epitaxially grown source and drain regions, then FIG. 4 It will be described in more detail with reference to.

As illustrated in FIG. 2C, a general process flowchart for forming the semiconductor device 200 may include the following processes. The transistor 210 to be formed therein on the active region 212 may be an N-channel transistor or P-, having specific transistor dimensions, such as gate length, gate width, and a specific thickness of the gate insulating layer 218. It can represent a specific transistor type, such as a channel transistor. Depending on the needs of the device of transistor 210, the target depth x _s may be selected to reduce the overall sheet resistance of surface portion 214b by the desired amount. The sheet resistance and the overall contact resistance of the drain and source regions to be formed in the transistor element 210 depend significantly on the type of refractory metal used to form the metal silicide region and the target depth x _s . The overall performance of the transistor 210 may vary substantially depending on the quality of the interface of the metal silicide region formed at the target depth x _s , forming the fabrication process of the device 200, in particular the drain and source region. The methods involved in applying are applied based on target depth x _s to obtain an adjusted dopant profile in depth direction x, as illustrated and described with respect to FIG. 2B. Thus, forming the device 200 may comprise any process of forming a gate electrode 215 comprising a isolation structure 213 and a gate insulating layer 218 and an offset spacer 216a according to established process techniques. Include them. Next, an ion implant process 220 may be performed to obtain the dopant concentration needed to form the extended region 214a. Next, in some embodiments, a rapid thermal anneal process may be performed to activate the dopants in the region 214a and to recrystallize the damage caused by the implant. In other embodiments, the annealing process may be performed in a step after forming the deep drain and source regions. Appropriate spacer elements can then be formed by established deposition and anisotropic etching techniques.

2D schematically illustrates the semiconductor device 200 after formation of the spacer elements 216, which are used as implant masks during the ion implant process 221 to form the deep drain and source regions 214. In one embodiment, the ion implant can be formed in a single implant step, and implant parameters, such as, for example, the implant energy and dose, can be controlled based on the target depth x _s . Thus, the average penetration depth of the ion implant 221 according to the dopant species used in this implant process can be determined such that an increased dopant concentration can be obtained near the target depth x _s . For this reason, the appropriate implant energy for dopant species can be readily determined based on established simulation calculations. In other embodiments, the implant process 221 may consist of two or more implant steps to create a vertical dopant profile in the manner described above. In one embodiment, additional implant steps designed to adjust the previous or next implant may be performed to form the deep drain and source regions 214, thus providing a desired increase at or near the target depth _xs. To form a dopant concentration. In other embodiments, additional implant steps may be performed based on different dopant species, compared to the dopant species used in the previous implant or subsequent implant steps to substantially define the drain and source regions 214. It may be of a type having the same or different electrical conductivity. For example, the dopant species may be used to form deep drain and source regions 214 that exhibit a very different diffusivity compared to refractory metal, which may be used substantially in the drain and source regions of the metal silicide regions. Thus, such dopant species may have a reduced effect on the diffusivity of refractory metals and a decrease in the "amplification effect" to some extent, where there is a deeper influence on the diffusivity of refractory metals, ie, having a diffusivity similar to that of refractory metals. Introducing the second dopant species may further enhance the smoothing effect of the diffused dopant concentration at or near the target depth x _s . In another embodiment, the second dopant species may differ in its conductivity type to act as a counter dopant, thus reducing the "electrically effective" dopant concentration, while acting as a substance that reduces the reaction. The actual dopant concentration is increased.

In some embodiments, the ion implant step 221 performed with a step comprising a single implant or two or more individual implant steps based on the same or different ionic species may result in a higher dopant concentration at or near the target depth x _s . It can be designed to achieve that, for a given silicided process and given refractory metal or metals used at a given process condition, the ion implant 221 is followed by the silicide following the "slow down" reaction surface. To be considered as a "barrier" implant for formation. After the ion implant process 221, the device 200 substantially activates the dopants entrained by the implant 220 and during the implant sequence 221 and is also generated by the implants 221, 220 described above. It can be annealed to cure damage to the crystals.

2E schematically illustrates a semiconductor device 200 in a further improved manufacturing stage. Here, the refractory metal 222 layer is formed conformally on the device 200. The refractory metal layer 222 may be made of one or more metals such as nickel, cobalt, titanium, platinum, tungsten, and the like, and the layer 222 may include two or more sub-layers to which different refractory metals are applied. The layer 222 may be provided in a single layer formed of a single refractory metal or a compound of two or more different refractory metals. The layer 222 may be formed based on established deposition techniques, such as sputter deposition or chemical vapor deposition, and the thickness of the layer 222 is controlled according to a target depth x _s . The thickness makes it possible to form metal silicides up to the target depth x _s . Corresponding data on silicon “consuption” during silicidation processes involving one or more refractory metals of interest can be obtained based on trial runs, experiments, and the like. The device 200 may then be thermally treated under certain conditions, i.e., at a specific temperature and duration, to diffuse and consequently refractory metal of the layer 222 to the regions 214 and the gate electrode 215. To initiate the reaction with silicon. In other embodiments, forming metal silicide at gate electrode 215 may be separate from the corresponding process of forming metal silicide in drain and source regions 214. For example, a cap layer (not shown) may be provided on top of the gate electrode 215 to protect the gate electrode 215 during subsequent silicidation processes. The cap layer may then be removed and an additional layer of refractory metal may be deposited and further chemical reactions be initiated, where the gate electrode 215 is substantially affected, wherein it is controlled with the previously formed metal silicide. Due to the dopant concentration, the reaction of the drain and source regions 214 can be substantially reduced and can greatly reduce further transmission beyond the target depth x _s in terms of metal silicide. Thus, the gate electrode 215 may obtain different metal silicides, the formation and thus the dimensions of each metal silicide may be substantially separated from the corresponding metal silicide regions in the drain and source regions 214. have.

Subsequently, it can be inferred that a silicided process is generally performed for the gate electrode 215 and the regions 214. It should also be considered that different process strategies are required depending on the metal used. For example, cobalt may require a two-step heat treatment with an intermediate selective etching step to remove unreacted cobalt to convert cobalt silicide from a high ohmic phase to a low ohmic state. . For other materials, a single heat treatment step may be appropriate, as in the case of nickel, nickel platinum, and the like. As already discussed with reference to FIG. 2B, during the chemical reaction, the metal from the layer 222 diffuses into the region 214, because of the dopant profile adjusted in the depth direction x, the improved uniformity of the silicided surface, Any roughness of the interface between the metal silicide and the semiconductor material can be formed to greatly reduce.

2F schematically illustrates the semiconductor device 200 after the continuation of the above-described process is completed. Thus, the device 200 includes metal silicide regions 219 formed on the gate electrode 215 and metal silicide regions 217 in the deep drain and source regions 214. In addition, the interface 217a is substantially positioned at or near the target depth x _s , where at least the corresponding roughness of the substantially horizontal portions is greatly reduced compared to the known art. As a result, unfavorable effects such as contact leakage currents, etc. can be reduced for a given transistor design, and the contact resistance of transistor 210 is not determined by the dopant concentration therein but rather the conductivity of metal silicide region 217. As substantially determined by, the adjustment of the dopant profile in the depth direction will not have an inherently adverse effect on the overall performance of the transistor 210, while the position of the PN junction 214c is affected by the adjustment of the dopant profile. Can remain virtually unsubscribed.

It should be considered that the adjustment of the dopant profile should be applied in accordance with the desired target depth x _s for the particular transistor type. For example, as described above, P-type and N-type transistors usually formed in CMOS devices may exhibit different behavior depending on the formation of the silicide region. Thus, the same target depth x _s can be selected for both transistor types, with each of the adjusted dopant profiles making it possible to form corresponding metal silicide regions with increased uniformity. In other embodiments, other target depths x _s or other transistor types may be considered as appropriate, and a continuous implant to form a controlled dopant profile may be performed differently for a variety of other transistor types. Will be explained.

3 schematically illustrates a semiconductor device 300 including two different transistors 310, 350 formed therein. In FIG. 3, the transistor 310 includes a deep drain and source region 314 and a corresponding extension region 314a. The dopant profile in the depth direction is described with reference to FIGS. 2B-2F. Adjusted together. That is, the dopant concentration of the drain and source regions 314 was increased at the target depth x _s . In addition, the transistor 310 during the implant process 324 configured to form deep drain and source regions corresponding to a transistor 350 having a dopant profile of increased dopant concentration at or near target depth y _s. To protect 310, it may be covered by a mask, such as resist mask 323. In the implant process 324, the same criteria may be applied as described above with reference to the implant 221 (FIG. 2D). After forming the deep drain and source regions in the transistor 350, the corresponding annealing cycles may be performed, and further processing may continue as described above with reference to FIG. 2E. That is, the refractory metal layer may be deposited to a sufficient thickness to consume silicon to at least the target depth y _s . Thus, the same silicideization process can be performed, where the controlled dopant profile of the transistor 310, in particular having a smaller target depth x, substantially maintains the silicide face at or near x _s , and the second transistor The silicide face at 350 may progress down to the target depth y _s .

As a result, when different types of transistors are needed, a higher degree of process flexibility in the formation of metal silicide regions for different transistor types, since the formation of resist mask 323 is a standard procedure in conventional process flows. It is provided without this complicated additional process.

4 schematically illustrates a semiconductor device 400 having a transistor element 410 formed thereon, at least a portion of which is introduced by deposition or diffusion. The transistor 410 includes a gate electrode 415 formed with spacer elements 416 adjacent to epitaxially grown silicon-containing semiconductor regions 424. Also shown is the target depth x, where an interface of the metal silicide region is formed there. It should be considered that the target depth x _s may of course be located in the active region 412 formed in the substrate 401 prior to the formation of the region 424. In principle, the transistor 410 may be formed according to the process technique described above with reference to FIGS. 1A and 2C-2F, prior to forming deep drain and source regions, where the region 424 is an established select epi. It may be formed using tactical growth techniques, where specific dopant species may be added to the deposition environment to provide the regions 424 to the doped regions. Depending on the process parameters that control the deposition environment of the selective epitaxial growth process, the desired vertical dopant profile may be adjusted. For example, the addition ratio of the dopant precursor can be controlled based on the target depth x _s because the deposition ratio is very well known for a given deposition method. For example, very localized concentration peaks can be made using specific dopant species at target depth x _s . For this purpose, when the target depth x _s is reached, a corresponding burst of the dopant precursor can be made in the deposition environment of the selective epitaxial growth process. If very localized concentration peaks are needed, the process parameters may be correspondingly adjusted to appropriately lower the deposition rate, while depositing the material at least "near" of the target depth x _s . In other embodiments, as described above in FIG. 2D with reference to the ion implant 221, a substantially uniform dopant concentration may be created in the epitaxial growth regions 424 and may be required in the depth direction. Controlling the dopant profile can be obtained by specially designed ion implant processes. In yet other embodiments, the exact location of the increased dopant concentration, ie the exact location of the target depth x _s , must be formed in the active region 412. In this case, region 412 may be recessed adjacent spacer element 416 by any suitable technique, such as isotropic or anisotropic etching. In one embodiment, the oxidation process can be formed in a very controllable manner, and silicon dioxide can be removed using established highly selective and easily controllable wet chemical etching techniques, thereby recessing in a very controllable manner. 424a is formed. Then, an epitaxial growth process for forming the region 424 can be performed in the manner as described above, and now the target depth x _s can be located in the recess 424a, whereby the desired dopant The species can be used to obtain very local dopant concentration picks.

After the selective epitaxial growth process to obtain the region 424 is completed, an optional additional implant process may be performed to form deep drain and source regions with vertical extensions in the device as needed. An annealing process may be performed to activate the dopant introduced by the optional ion implant step. Additional implant processes for forming deep drain and source regions can be omitted when the recesses 424a are formed, and the dopant profile can be made substantially secure by controlling the dopant precursor concentrations in the selective epitaxial deposition environment. . In this case, the annealing process can be omitted because dopant atoms are generally located at the lattice positions. The spacer 416 may then be removed by established highly selective etching techniques and then that successive implant may be performed to form extension regions adjacent to the gate electrode 415. Next, additional spacer elements, such as the spacers 416, may be formed, and metal silicide regions may be formed in a similar manner as described above with reference to FIG. 2F.

During the silicidation process, the increased dopant concentration highly localized at or near the target depth x _s provides improved “localization” of the metal silicide interface, thereby improving the overall properties of the transistor 9410. In addition, because very high and very localized suitable dopant species can be located at or near the target depth x _s , the "barrier" effect of the concentration peak is substantially without seriously affecting the overall "electrical" dopant profile. Adjusted to be very noticeable.

As a result, the present invention provides an improved technique for forming metal silicides having reduced non-uniformity at the interface in the remaining semiconductor regions, thereby improving the performance of transistor elements. Enhanced metal silicide properties can be obtained by adjusting the vertical dopant profile in the deep drain and source regions, where the increased dopant concentration is made at or near the target depth for the metal silicide interface and forms a "barrier" dopant concentration. do. The barrier concentration can greatly influence the diffusivity and thus the reaction rate during the metal silicide formation process. The barrier dopant concentration may be formed by the introduction of dopants based on a continuous implant, and / or epitaxial deposition process, including one or more implant steps, which are specifically designed. Regardless of how the increased dopant concentration is made, other dopant species having the same or different conductivity types may be used. If those with other conductivity types are used, the dopant concentrations that affect the metal diffusivity can be separated, at least to some extent, from the electrically affecting dopant concentrations, thereby substantially affecting the electrical transistor performance. Provides increased flexibility in designing barrier concentrations that do not suffer.

The specific embodiments disclosed above are merely exemplary, and the present invention may be modified and practiced otherwise in equivalent ways in a manner apparent to those skilled in the art to have the advantages shown herein. For example, the process steps described above may be performed in a different order. Moreover, no limitations are intended as to the details of construction or design shown herein and are not intended to be contrary to what is stated in the claims. Accordingly, it is to be understood that the specific embodiments disclosed herein may be changed and modified and that all such changes may be considered within the scope and principles of the invention. Therefore, the protection scope intended to be pursued herein will be shown in the claims.

Claims (13)

Determining a target depth X _s of the metal silicide region formed in the silicon-containing semiconductor region 212 formed on the substrate 201; Forming a dopant profile for containing semiconductor region, the target depth (X _s) to get the local peak dopant concentration near the silicon with respect to the target depth (X _s) - - wherein in accordance with the depth of the contained semiconductor region of silicon; And Forming a metal silicide region (217) according to the target depth (X _s ). The method of claim 1, Forming the dopant profile comprises performing an ion implant process, wherein the implant dose and energy are controlled to substantially produce the dopant profile. The method of claim 2, Wherein the ion implant process is at least one first implant step using first dopant species having a first conductivity type. The method of claim 3, The dopant profile is substantially determined by the first dopant species. The method of claim 3, The ion implant process includes at least one implant step using the first dopant species and other second dopant species, wherein the first and second dopant species substantially determine the local maximum. . The method of claim 1, Forming the dopant profile is introducing the dopant species in at least one of deposition and diffusion. The method of claim 1, And wherein said silicon-containing semiconductor region (212) comprising said dopant profile represents at least one of a drain region (214) and a source region (214) of a field effect transistor (200). The method of claim 1, Forming the metal silicide region 217 may include depositing a refractory metal layer 222 on the silicon-containing semiconductor region 212 and forming the substrate 201 to form the metal silicide 217. Method comprising the step of heat treatment. The method of claim 8, At least one of a thickness of the refractory metal layer (222), a temperature of the heat treatment, and a duration of the heat treatment are controlled to substantially stop the growth of the silicide at the target depth (X _s ). Identifying a first target depth X _s for the metal silicide region for forming the drain and source of the first specific transistor type 310 formed in the one or more substrates 301; As the depth increases when the first target depth X _s is reached, in relation to the depth direction of the one or more substrates, according to the first target depth X _s to obtain an increasing dopant concentration, Forming drain and source regions of the first specific transistor type on one or more substrates having a dopant profile; And Forming the metal silicide in the drain source regions of the first specific transistor type (310) according to the first target depth (X _s ). The method of claim 10, The forming of the metal silicide region may include depositing a refractory metal layer 222 on the silicon-containing semiconductor region formed on the one or more substrates to form the metal silicide and heat treating the one or more substrates. How to feature. The method of claim 11, At least one of a thickness of the refractory metal layer (222), a temperature of the heat treatment, and a duration of the heat treatment is controlled to substantially stop the growth of the silicide at the first target depth. The method of claim 10, Determining a second target depth Y _s for the drain and source regions of the second specific transistor type 350 formed in the one or more substrates; Upon reaching the second target depth, as the depth increases, with respect to the depth direction of the one or more substrates, in accordance with the second target depth Y _s to obtain an increasing second dopant concentration, Forming the drain and source regions of the second specific transistor type (350) having a dopant profile; And Forming the second metal silicide region in the drain and source regions of the second specific transistor type 350 to stop growth of the metal silicide substantially at the second target depth Y _s . Characterized in that.

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