KR20080014386A - Thin film transistor array panel and method for manufacturing the same - Google Patents

Abstract

A TFT(Thin Film Transistor) substrate and a method for manufacturing the same are provided to define a hydrophobic area and a hydrophilic area even without separately performing a surface reforming process, thereby simplifying the manufacturing process. A data line(171) is formed on a substrate(110). A gate line(121) having a gate electrode(124) cross the data line. A source electrode(133) is connected to the data line. A drain electrode(135) is disposed to face the source electrode. An organic semiconductor(154) is contacted with the source electrode and the drain electrode. A partition wall defines the organic semiconductor, wherein the partition wall is formed of acryl-based photosensitive resin containing fluorine-containing compound.

Description

Thin film transistor array panel and manufacturing method therefor {THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME}

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II.

3, 5, 7, 9, 11, and 13 are layout views sequentially illustrating a method of manufacturing the thin film transistor array panel of FIGS. 1 and 2 according to an embodiment of the present invention;

4 is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along the line IV-IV.

FIG. 6 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI.

FIG. 8 is a cross-sectional view of the thin film transistor array panel of FIG. 7 taken along the line VIII-VIII.

FIG. 10 is a cross-sectional view of the thin film transistor array panel of FIG. 9 taken along the line X-X.

FIG. 12 is a cross-sectional view of the thin film transistor array panel of FIG. 11 taken along the line XII-XII.

14 is a cross-sectional view of the thin film transistor array panel of FIG. 13 taken along the line XIV-XIV.

 <Description of Drawing>

110: insulating substrate 121: gate line

124: gate electrode 129: end of gate line

133: source electrode 135: drain electrode

136: electrode portion 137: capacitive portion

145, 162, 163, 185: contact hole

144: gate insulator 146: opening

154: organic semiconductor 140, 160: interlayer insulating film

171: data line 172: sustain electrode line

173: protrusion 174 of the data line: light blocking film

177: sustain electrode 179: end of data line

81, 82: contact auxiliary member 191: pixel electrode

The present invention relates to a thin film transistor array panel and a method of manufacturing the same.

In general, flat panel displays such as a liquid crystal display (LCD), an organic light emitting diode display (OLED display), an electrophoretic display, and the like are provided with a plurality of pairs of electric field generating electrodes. And an electro-optical active layer interposed therebetween. The liquid crystal display device includes a liquid crystal layer as the electro-optical active layer, and the organic light emitting display device includes an organic light emitting layer as the electro-optical active layer.

One of the pair of field generating electrodes is typically connected to a switching element to receive an electrical signal, and the electro-optical active layer converts the electrical signal into an optical signal to display an image.

In the flat panel display device, a thin film transistor (TFT), which is a three-terminal element, is used as a switching element. A data line to be transmitted is provided in the flat panel display.

Among these thin film transistors, studies on organic thin film transistors (OTFTs) including organic semiconductors instead of inorganic semiconductors such as silicon (Si) have been actively conducted.

The organic thin film transistor is attracting attention as a core element of a flexible display device because the organic thin film transistor may be formed in a fiber or film form due to the nature of the organic material.

In addition, the organic thin film transistor may be manufactured by a solution process such as an ink-jet printing method, and thus may be easily applied to a large area flat panel display device having only a limited deposition process.

The inkjet printing method is a method of injecting an organic solution into a predetermined region defined by a partition while moving an inkjet head provided with a nozzle, and can easily form an organic thin film such as an organic semiconductor or an insulator.

In this case, when the barrier rib has a surface property different from that of the organic solution, the barrier layer may prevent the solution from flowing over the barrier rib and form the organic thin film only at a desired position. For example, when the organic solution has hydrophilicity, the partition surface may be surface treated to have hydrophobicity, and when the organic solution has hydrophobicity, the partition surface may be surface treated to have hydrophilicity.

Such surface treatment requires a separate process using plasma.

However, the surface treatment using plasma does not last long, and the organic solution may be formed to have a non-uniform thickness because the plasma treatment is performed not only on the partition surface but also at the position where the organic thin film is to be formed.

Therefore, the technical problem to be achieved by the present invention is to solve this problem is to modify the surface of the partition wall without a separate plasma process.

A thin film transistor array panel according to an exemplary embodiment of the present invention includes a substrate, a data line formed on the substrate, a gate line crossing the data line and including a gate electrode, a source electrode connected to the data line, and facing the source electrode. A drain electrode, an organic semiconductor in contact with the source electrode and the drain electrode, and a partition including an acrylic photosensitive resin defining the organic semiconductor and containing a fluorine-containing compound.

The photosensitive resin may have thermal crosslinkability.

The fluorine-containing compound may include at least one selected from fluorine-based surfactants, fluorine-based nanoparticles, and fluorine-based polymer nanobeads.

The fluorine-containing compound may be included in an amount of 1 to 40 wt% based on the interlayer insulating film.

The organic semiconductor may have hydrophilicity.

A gate insulator may be further disposed between the organic semiconductor and the gate electrode, and at least one of the organic semiconductor and the gate insulator may include a soluble material.

The data line and the source electrode may include different materials, and the source electrode and the drain electrode may include ITO or IZO.

The light blocking layer may further include a light blocking layer under the organic semiconductor.

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention includes forming a data line on a substrate, forming a gate line intersecting the data line, a source electrode connected to the data line, and facing the source electrode. Forming a drain electrode, forming an organic semiconductor in contact with the source electrode and the drain electrode, and forming a partition defining the organic semiconductor, wherein forming the partition includes fluorine-containing. Forming an acrylic photosensitive resin film comprising a compound, and patterning the photosensitive resin film to form an opening.

Forming the photosensitive resin film includes applying a photosensitive resin, exposing and developing the photosensitive resin, and thermally crosslinking the photosensitive resin at 130 to 250 ° C.

The forming of the organic semiconductor may be performed by an inkjet printing method.

According to another exemplary embodiment of the present invention, a thin film transistor array panel may include forming a data line on a substrate, forming a first interlayer insulating layer on the data line, a source electrode connected to the data line on the first interlayer insulating layer, and Forming a drain electrode facing the source electrode, forming an acrylic photosensitive resin film containing a fluorine-containing compound on the source electrode and the drain electrode, and patterning the photosensitive resin film to form a second interlayer insulating film having an opening Forming an organic semiconductor in the opening; forming a gate insulator over the organic semiconductor; and forming a gate line over the gate insulator and the second interlayer insulating layer.

Forming the photosensitive resin film may include applying a photosensitive resin, exposing and developing the photosensitive resin, and thermally crosslinking the photosensitive resin at 130 to 250 ° C.

The forming of the organic semiconductor and the forming of the gate insulator may be formed by an inkjet printing method.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II.

A plurality of data lines 171, a plurality of storage electrode lines 172, and light on an insulating substrate 110 made of transparent glass, silicon, or plastic. The blocking film 174 is formed.

The data line 171 transmits a data signal and mainly extends in the vertical direction. Each data line 171 includes a plurality of projections 173 protruding sideways and a wide end portion 179 for connection with another layer or an external driving circuit. A data driving circuit (not shown) for generating a data signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, directly mounted on the substrate 110, or integrated in the substrate 110. Can be. When the data driving circuit is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The storage electrode line 172 receives a predetermined voltage and extends substantially in parallel with the data line 171. Each storage electrode line 172 is positioned between the two data lines 171 and is close to the right side of the two data lines 171. The storage electrode line 172 includes a storage electrode 177 which is divided laterally to form a circle. However, the shape and arrangement of the storage electrode line 172 may be modified in various ways.

The light blocking film 174 is separated from the data line 171 and the storage electrode line 172.

The data line 171, the storage electrode line 172, and the light blocking film 174 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, gold (Ag), gold alloy, or the like. Gold-based metals, copper-based metals such as copper (Cu) and copper alloys, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, and may be made of chromium (Cr), tantalum (Ta) and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. However, the data line 171 and the storage electrode line 172 may be made of various other metals or conductors.

The side surfaces of the data line 171, the storage electrode line 172, and the light blocking layer 174 may be inclined at an inclination angle of about 30 to 80 degrees with respect to the surface of the substrate 110.

A lower interlayer insulating layer 160 is formed on the data line 171, the storage electrode line 172, and the light blocking layer 174. The lower interlayer insulating layer 160 may be made of an inorganic insulator such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ), and may have a thickness of about 2,000 to 5,000 kPa.

The lower interlayer insulating layer 160 has a plurality of contact holes 163 and 162 exposing the protrusion 173 and the end portion 179 of the data line 171, respectively.

A plurality of source electrodes 133, a plurality of drain electrodes 135, and a plurality of contact assistants 82 are formed on the lower interlayer insulating layer 160.

The source electrode 133 may be island type and connected to the data line 171 through the contact hole 163.

The drain electrode 135 at least partially overlaps the portion of the light blocking layer 174 that faces the source electrode 133 (hereinafter, referred to as an “electrode portion”) and the storage electrode line 172 (hereinafter, the “capacitor portion”). 137). The electrode part 136 forms a part of a thin film transistor (TFT) facing the source electrode 133, and the capacitor part 137 overlaps the storage electrode line 172 to hold the electrode to strengthen the voltage holding capability. Form a storage capacitor.

The contact auxiliary member 82 is connected to the end portion 179 of the data line 171 through the contact hole 162, and the adhesion between the end portion 179 of the data line 171 and the external device is limited. Complement and protect them.

Since the source electrode 133 and the drain electrode 135 are in direct contact with the organic semiconductor, the source electrode 133 and the drain electrode 135 are made of a conductive material having a work function that is not significantly different from the energy level of the organic semiconductor. The Schottky barrier can be lowered to facilitate carrier injection and movement. Such materials include conductive oxides such as ITO or IZO. Their thickness may be about 300 to 1,000 mm 3.

An upper interlayer insulating layer 140 is formed on the entire surface of the substrate including the source electrode 133, the drain electrode 135, and the lower interlayer insulating layer 160.

The upper interlayer insulating layer 140 has a plurality of openings 146 and a plurality of contact holes 145. The opening 146 exposes the source electrode 133 and the drain electrode 135, and the lower interlayer insulating layer 160 therebetween, and the contact hole 145 exposes the drain electrode 135.

The upper interlayer insulating layer 140 may be made of an acrylic photosensitive organic material including a fluorine-containing compound and having thermal crosslinkability. The fluorine-containing compound may be a fluoro-surfactant, a fluoro-nanoparticle, or a fluoropolymer nanobead. Examples may include Zonyl ™ (manufactured by Dupont), Novec ™ (manufactured by 3M), Fluowet ™ (manufactured by Clariant), Lodyne ™ (manufactured by Ciba Specialty Chemicals), Megaface ™ (manufactured by DAINIPPON INK AND CHEMICALS), and the like. .

The fluorine-containing compound is preferably contained at about 1 to 40% by weight based on the total content of the photosensitive organic material. If the content is less than 1% by weight, the surface properties are hardly exhibited. If the content is more than 40% by weight, the surface tension of the upper interlayer insulating layer 140 may be too small, resulting in a non-uniform film formed thereon.

As such, by forming the upper interlayer insulating layer 140 using a photosensitive organic material including a fluorine-containing compound, the surface of the upper interlayer insulating layer 140 may have hydrophobicity without a separate surface modification process. On the other hand, the opening 146 and the contact hole 145 from which the upper interlayer insulating layer 140 is removed may have relatively hydrophilicity because there is no fluorine-containing compound.

A plurality of island type organic semiconductor islands 154 are formed in the opening 146 of the upper interlayer insulating layer 140. The organic semiconductor 154 is surrounded by the upper interlayer insulating layer 140, and the upper interlayer insulating layer 140 surrounding the organic semiconductor 154 is a partition defining an area of the organic semiconductor 154.

The organic semiconductor 154 is in contact with the source electrode 133 and the drain electrode 135, and the height of the organic semiconductor 154 is lower than that of the upper interlayer insulating layer 140, so that the organic semiconductor 154 is completely trapped by the upper interlayer insulating layer 140. As such, since the organic semiconductor 154 is completely trapped by the upper interlayer insulating layer 140 and the side surface is not exposed, it is possible to prevent the chemical liquid from penetrating into the side surface of the organic semiconductor 154 in a subsequent process.

The organic semiconductor 154 may have surface characteristics different from those of the upper interlayer insulating layer 140. For example, when the surface of the upper interlayer insulating layer 140 has hydrophobicity as described above, the organic semiconductor 154 is formed of a relatively hydrophilic material. In this case, the organic semiconductor 154 may be collected only at the openings 146 having the same surface characteristics without flowing over the upper interlayer insulating layer 140, so that the organic semiconductor may be formed only at a desired portion.

The organic semiconductor 154 is formed on the light blocking layer 174. The light blocking layer 174 prevents light supplied from the backlight from directly flowing into the organic semiconductor 154 to prevent a sudden increase in photoleakage current in the organic semiconductor 154.

The organic semiconductor 154 may include a high molecular compound or a low molecular compound dissolved in an aqueous solution or an organic solvent.

The organic semiconductor 154 includes pentacene and its precursors, tetrabenzoporphyrin and its derivatives, polyphenylenevinylene and its derivatives, polyfluorene and its derivatives, and polytinylene vinyl. Polythienylenevinylene and its derivatives, poly-3-hexylthiophene, polythiophene and its derivatives, polythienothiophene and its derivatives, polyarylamine Its derivatives, phthalocyanine and its derivatives, metallized phthalocyanine or halogenated derivatives thereof, perylenetetracarboxylic dianhydride (PTCDA), naphthalenetetracarboxylic dianhydride (NTCDA) ) Or derivatives containing imide derivatives thereof, perylene or coronene and their substituents It may include at least one selected.

The thickness of the organic semiconductor 154 may be about 300 to 3,000 mm 3.

The gate insulator 144 is formed on the organic semiconductor 154. The gate insulator 144 is formed in the opening 146 of the upper interlayer insulating layer 140, and the sum of the thicknesses of the organic semiconductor 154 and the gate insulator 144 is thinner than the thickness of the upper interlayer insulating layer 140.

The gate insulator 144 is made of polyacryl and its derivatives, polystyrene and its derivatives, benzocyclobutane (BCB), polyimide and its derivatives, polyvinyl alcohol and its derivatives. Derivatives, parylene and derivatives thereof, perfluorocyclobutane and derivatives thereof, and perfluorovinylether and derivatives thereof.

A plurality of gate lines 121 are formed on the gate insulator 144 and the upper interlayer insulating layer 140.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction to cross the data line 171 and the storage electrode line 172. Each gate line 121 includes a plurality of gate electrodes 124 protruding upwards and a wide end portion 129 for connection with another layer or an external driving circuit. A gate driving circuit (not shown) that generates a gate signal is mounted on a flexible printed circuit film (not shown) attached over the substrate 110, directly mounted on the substrate 110, or integrated into the substrate 110. Can be. When the gate driving circuit is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The gate electrode 124 overlaps the organic semiconductor 154 with the gate insulator 144 interposed therebetween, and is formed larger than the opening 146 to completely cover the organic semiconductor 154 and the gate insulator 144. have.

The gate line 121 may be made of the same material as the data line 171 and the storage electrode line 172.

The side surface of the gate line 121 is also inclined with respect to the surface of the substrate 110 and the inclination angle is preferably about 30 to about 80 degrees.

The passivation layer 180 is formed on the gate line 121. The passivation layer 180 is also formed on the end portion 129 of the gate line 121 to prevent the end portion 129 of the gate line 121 from being short-circuited with the end portion of the adjacent gate line.

The passivation layer 180 has contact holes 185 and 181.

The contact hole 185 is positioned above the contact hole 145 formed in the upper interlayer insulating layer 140 to expose the drain electrode 137, and the contact hole 181 is an end portion 129 of the gate line 121. Reveals.

The passivation layer 180 is to protect the organic thin film transistor and the gate line 121, and may be formed on a portion or the entire surface of the substrate and may be omitted in some cases.

The pixel electrode 191 and the contact auxiliary member 81 are formed on the passivation layer 180.

The pixel electrode 191 is connected to the drain electrode 135 through the contact holes 185 and 145.

The pixel electrode 191 may overlap the gate line 121 and / or the data line 171 to increase an aperture ratio.

The pixel electrode 191 generates an electric field together with a common electrode (not shown) of another display panel (not shown) that receives a data voltage from a thin film transistor and receives a common voltage. The direction of the liquid crystal molecules of the liquid crystal layer (not shown) in between is determined. The pixel electrode 191 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off.

The contact auxiliary member 81 is connected to the end portion 129 of the gate line 121 through the contact hole 181, and complements the adhesiveness between the end portion 129 of the gate line 121 and an external device. Protect them.

One gate electrode 124, one source electrode 133, and one drain electrode 135 form one thin film transistor together with the organic semiconductor 154, and a channel of the thin film transistor is a source electrode 133. ) And the drain electrode 135 are formed in the organic semiconductor 154.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 and 2 will be described in detail with reference to FIGS. 3 to 14.

3, 5, 7, 9, 11, and 13 are layout views at an intermediate stage of a method of manufacturing the organic thin film transistor array panel of FIGS. 1 and 2 according to an embodiment of the present invention, and FIG. 4. 3 is a cross-sectional view of the organic thin film transistor array panel of FIG. 3 taken along line IV-IV, and FIG. 6 is a cross-sectional view of the organic thin film transistor array panel of FIG. 5 taken along line VI-VI, and FIG. 10 is a cross-sectional view of the organic thin film transistor array panel cut along the line VIII-VIII, FIG. 10 is a cross-sectional view of the organic thin film transistor array panel shown in FIG. 9 along the line XX, and FIG. 12 is a XII view of the organic thin film transistor array panel of FIG. FIG. 14 is a cross-sectional view of the organic thin film transistor array panel of FIG. 13 taken along the line XIV-XIV.

First, as illustrated in FIGS. 3 and 4, a metal layer is stacked on the substrate 110 by sputtering and photo-etched to form a data line including a protrusion 173 and an end portion 179. 171, the storage electrode line 172 including the storage electrode 177, and the light blocking film 174 are formed.

Next, as shown in FIGS. 5 and 6, silicon nitride is chemical vapor deposited (CVD) to form a lower interlayer insulating layer 160, a photosensitive film is coated thereon, and photoetched to form contact holes 162. 163).

Next, as shown in FIGS. 7 and 8, after sputtering ITO or IZO, photo etching is performed to form a source electrode 133, a drain electrode 135, and a contact auxiliary member 82.

Next, as shown in FIGS. 9 and 10, a photosensitive resin is formed on the entire substrate. The photosensitive resin is formed by applying and developing an acrylic photosensitive solution and thermally crosslinking it at about 130 to 250 ° C.

Subsequently, the photosensitive resin is patterned to form an upper interlayer insulating film 140 having a plurality of openings 146 and a plurality of contact holes 145.

At this time, the acrylic photosensitive solution contains a fluorine-containing compound. The fluorine-containing compound may be a fluorine-based surfactant, fluorine-based nanoparticles, and fluorine-based polymer nanobeads. Examples may include Zonyl ™ (manufactured by Dupont), Novec ™ (manufactured by 3M), Fluowet ™ (manufactured by Clariant), Lodyne ™ (manufactured by Ciba Specialty Chemicals), Megaface ™ (manufactured by DAINIPPON INK AND CHEMICALS), and the like. . The fluorine-containing compound is preferably contained at about 1 to 40% by weight based on the total content of the acrylic photosensitive solution.

As such, by forming the upper interlayer insulating layer 140 using a photosensitive solution containing a fluorine-containing compound, the surface of the upper interlayer insulating layer 140 may have hydrophobicity.

Next, the organic semiconductor 154 is formed in the opening 146.

The organic semiconductor 154 sprays the organic semiconductor solution into the opening 146 according to an ink-jet printing method. In this case, the organic semiconductor solution includes a material having a surface property different from that of the upper interlayer insulating layer 140 described above. Accordingly, the organic semiconductor solution may be collected only in the opening 146 in which the upper interlayer insulating layer is removed without flowing over the upper interlayer insulating layer 140. Thus, the organic semiconductor solution can be collected in the openings 146 without a surface modification process using plasma.

Thereafter, the solvent is dried in the organic semiconductor solution.

Subsequently, a gate insulating member 146 is formed in the opening 146. The gate insulating member 146 also sprays an organic insulating solution onto the organic semiconductor 154 in the opening 146 according to the inkjet printing method. In this case, as described above, the solution is collected on the organic semiconductor 154 of the opening 146. Thereafter, the solvent in the organic insulating solution is dried.

Next, as shown in FIGS. 11 and 12, the metal layer is stacked and photo-etched by a method such as sputtering to form a gate line 121 including the gate electrode 124 and the end portion 129. In this case, the gate electrode 124 is formed to have a size that completely covers the opening 146.

Next, as shown in FIGS. 13 and 14, the passivation layer 180 is formed on the entire surface of the substrate and photo-etched to form contact holes 181 and 185.

Finally, as illustrated in FIGS. 1 and 2, the pixel electrode 191 and the contact auxiliary member 81 connected to the drain electrode 135 are formed through the contact holes 145 and 185.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

Hydrophobic and hydrophilic regions can be defined without a separate surface modification process using plasma, which reduces the process, prevents organic semiconductors, etc. from flowing over the interlayer insulating film and can be formed accurately only in desired portions.

Claims (14)

Board, A data line formed on the substrate, A gate line crossing the data line and including a gate electrode, A source electrode connected to the data line, A drain electrode facing the source electrode, An organic semiconductor in contact with the source electrode and the drain electrode, and A barrier rib including acrylic photosensitive resin defining the organic semiconductor and including a fluorine-containing compound. Thin film transistor array panel comprising a. In claim 1, The photosensitive resin has a thermal crosslinkability. In claim 2, The fluorine-containing compound includes at least one selected from fluorine-based surfactants, fluorine-based nanoparticles, and fluorine-based polymer nanobeads. In claim 3, The fluorine-containing compound is 1 to 40% by weight based on the interlayer insulating film. In claim 1, The organic semiconductor has a hydrophilic thin film transistor array panel. In claim 1, A gate insulator positioned between the organic semiconductor and the gate electrode; At least one of the organic semiconductor and the gate insulator comprises a soluble material. In claim 1, The data line and the source electrode include different materials; The thin film transistor array panel of which the source electrode and the drain electrode include ITO or IZO. In claim 1, A thin film transistor array panel further comprising a light blocking layer under the organic semiconductor. Forming a data line on the substrate, Forming a gate line crossing the data line; Forming a source electrode connected to the data line and a drain electrode facing the source electrode; Forming an organic semiconductor in contact with the source electrode and the drain electrode, and Forming a barrier rib defining the organic semiconductor Including; Forming the partition wall Forming an acrylic photosensitive resin film containing a fluorine-containing compound, and Patterning the photosensitive resin film to form an opening Method of manufacturing a thin film transistor array panel comprising a. In claim 9, Forming the photosensitive resin film Applying a photosensitive resin, Exposing and developing the photosensitive resin, and Thermally crosslinking the photosensitive resin at 130 to 250 ° C Method of manufacturing a thin film transistor array panel comprising a. In claim 10, The forming of the organic semiconductor may be performed by an inkjet printing method. Forming a data line on the substrate, Forming a first interlayer insulating film on the data line; Forming a source electrode connected to the data line and a drain electrode facing the source electrode on the first interlayer insulating layer; Forming an acrylic photosensitive resin film including a fluorine-containing compound on the source electrode and the drain electrode; Patterning the photosensitive resin film to form a second interlayer insulating film having an opening; Forming an organic semiconductor in the opening; Forming a gate insulator over the organic semiconductor, and Forming a gate line on the gate insulator and the second interlayer insulating layer Method of manufacturing a thin film transistor array panel comprising a. In claim 12, Forming the photosensitive resin film Applying a photosensitive resin, Exposing and developing the photosensitive resin, and Thermally crosslinking the photosensitive resin at 130 to 250 ° C Method of manufacturing a thin film transistor array panel comprising a. In claim 13, The forming of the organic semiconductor and the forming of the gate insulator are formed by an inkjet printing method.

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