KR20080012462A - Semiconductor device having guardring with pn diode and method of fabricating the same - Google Patents

Abstract

A semiconductor device having a guard ring with a PN diode is provided to discharge the charges accumulated by a charge-up phenomenon through an antenna diode in a chip region in an etch process using plasma while discharging the charges through a guard ring PN diode by forming a guard ring PN diode in a guard ring region. A semiconductor substrate with a chip region(CR1) and a guard ring region(GR1) surrounding the chip region is prepared. A p-well region(5) is disposed in the substrate in the chip region and the guard ring region. An n+ region(10b) is disposed on the p-well region in the guard ring region. A guard ring dam is formed on the substrate in the guard ring region and is electrically connected to the n+ region. The p-well region and the n+ region in the guard ring region constitute a guard ring PN diode(AD2). A gate is disposed on the substrate in the chip region. A first interlayer dielectric covers the gate. A direct contact penetrates the first interlayer dielectric. A bitline(30a) is disposed on the first interlayer dielectric and covers the direct contact. A second interlayer dielectric(35) covers the bitline. A metal contact(37a) penetrates the second interlayer dielectric. A first metal wiring(40a) is disposed on the second interlayer dielectric and covers the metal contact. A third interlayer dielectric(45) covers the first metal interconnection. A via contact(47a) penetrates the third interlayer dielectric. A second metal wiring(50a) is disposed on the third interlayer dielectric and covers the via contact.

Description

Semiconductor device having guard ring with PN diode and method for manufacturing the same

1 is a plan view illustrating a method of manufacturing a semiconductor device according to the prior art.

2 and 3 are cross-sectional views taken along the line II ′ of FIG. 1 to explain a method of manufacturing a semiconductor device according to the prior art.

4 is a plan view illustrating a method of manufacturing a semiconductor device in accordance with embodiments of the present invention.

5 through 8 are cross-sectional views taken along line II-II ′ of FIG. 4 to explain a method of manufacturing a semiconductor device according to example embodiments.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a guard ring including a PN diode and a method of manufacturing the same.

The semiconductor process includes a scribe process in which tens or hundreds of chips are formed on a wafer, and then the chips are individually cut. During the scribing process, external impact and moisture penetration may occur inside the completed chips. Accordingly, chip guarding is formed around each of the chips at the same time as the chip forming process in order to prevent external impact and moisture penetration phenomenon occurring during the scribing process.

In general, the chip guard ring is formed of conductive materials since the chip guard ring is formed at the same time when forming the contacts, the bit line and the metal wires inside the chip. In addition, the chip guard ring is formed to surround the chip has a structure to protect the chip from all directions.

Meanwhile, the semiconductor process includes forming a conductive film or a metal film to form the bit lines and metal wires, and then etching the conductive film or the metal film. In this case, plasma etching, which can accurately etch fine patterns, is mainly used. For example, the plasma etching may be a reactive ion etching (RIE) process. Plasma etching is performed by placing a wafer on which a predetermined film to be etched is formed in a flat etching chamber, and supplying high frequency energy while supplying an etchant including oxygen or fluorine atoms. A method of ionizing an etchant comprising an ion and reacting the ionized oxygen atom or fluorine atom with the film on the surface of the wafer to be etched will be well known to those skilled in the art. At this time, almost all reaction products are generated in the gas phase, which is easily removed by vacuum exhaust, and thus, the wafer after etching can be kept in a clean state.

However, in the etching process using plasma in the semiconductor device manufacturing process, reaction products including a large amount of charge accumulate on the exposed wafer surface. Such reaction products can be removed to some extent through vacuum exhaust. However, a large amount of charges in these reaction products are trapped in the vicinity of the conducting conductive pattern, the charge-up phenomenon that accumulates the charge occurs. In this case, the accumulated charge may be discharged to generate a plasma damage phenomenon that damages a thin oxide film such as a gate oxide film. Therefore, an antenna diode may be provided in the chip area to prevent the plasma damage phenomenon.

1 is a plan view illustrating a method of manufacturing a semiconductor device according to the prior art, and FIGS. 2 and 3 are cross-sectional views taken along the cutting line I-I 'of FIG. admit.

1 and 2, a semiconductor substrate 100 having a chip region CR0 and a guard ring region GR0 surrounding the chip region CR0 is prepared. A p well region 105 is formed in the semiconductor substrate 100 in the chip region CR0 and the guard ring region GR0. A p + region 115 is formed on the p well region 105 in the guard ring region GR0. In addition, an n + region 110 is formed on the p well region 105 in the chip region CR0 to form an antenna diode AD0.

Subsequently, gates 120 are formed on the semiconductor substrate 100 in the chip region CR0. The gates 120 may be formed of a gate insulating layer 120a and a gate electrode 120b that are sequentially stacked. A first interlayer insulating layer 125 covering the gates 120 is formed on the semiconductor substrate having the gates 120. Direct contacts 127a are formed through the first interlayer insulating layer 125 to contact the semiconductor substrate 100 and the gates 120 in the chip region CR0. At the same time, a first contact 127b is formed in contact with the p + region 115 of the guard ring region GR0.

A bit line 130a and a first conductive pattern 130b are formed on the first interlayer insulating layer 125 to cover the direct contacts 127a and the first contact 127b, respectively. Next, a second interlayer insulating layer 135 is formed to cover the bit line 130a and the first conductive pattern 130b. A metal contact 137a and a second contact 137b are formed through the second interlayer insulating layer 135 to contact the bit line 130a and the first conductive pattern 130b, respectively. A first metal wiring 140a and a second conductive pattern 140b are formed on the second interlayer insulating layer 135 to cover the metal contact 137a and the second contact 137b, respectively.

Next, a third interlayer insulating film 145 is formed to cover the first metal wiring 140a and the second conductive pattern 140b. A first via contact 147a and a third contact 147b are formed through the third interlayer insulating layer 145 to contact the first metal wiring 140a and the second conductive pattern 140b, respectively. A second metal wiring 150a and a third conductive pattern 150b may be formed on the third interlayer insulating layer 145 to cover the first via contact 147a and the third contact 147b, respectively.

In addition, a fourth interlayer insulating layer 155 is formed to cover the second metal wiring 150a and the third conductive pattern 150b. A second via contact 157a and a fourth contact 157b are formed through the fourth interlayer insulating layer 155 to contact the second metal wiring 150a and the third conductive pattern 150b, respectively. A metal layer 160 is formed on the fourth interlayer insulating layer 155 to cover the second via contact 157a and the fourth contact 157b. A mask pattern 163 is formed on the metal layer 160. Plasma etching of a reactive ion etching (RIE) process is performed using the mask pattern 163 as an etching mask. In this case, charges are charged-up to the surface of the semiconductor device by the plasma etching, and the charged-up charges may be discharged through the antenna diode AD0.

1 and 3, all of the metal layer 160 is etched to contact the second via contact 157a and the fourth contact 157b, respectively. The pattern 160b is formed. Next, the first mask pattern 163 is removed. The p + region 115, the first contact 127b, the first conductive pattern 130b, the second contact 137b, the second conductive pattern 140b and the third contact 147b in the guard ring region GR0. The third conductive pattern 150b, the fourth contact 157b, and the fourth conductive pattern 160b form the guard ring G0.

As described above, the charge-up charges during plasma etching may be discharged through the antenna diode AD0. However, as the semiconductor device is gradually reduced in size, there may occur a case where there is insufficient space for providing the antenna diode in the chip region. In addition, even if there is a space for the antenna diode in the chip area, the manufacturing process can be complicated by adding the antenna diode.

Therefore, there is an urgent need to develop a technology capable of preventing the plasma damage phenomenon even when the space for providing the antenna diode in the chip region is insufficient.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device having a guard ring including a PN diode capable of preventing plasma damage caused by charge accumulation in a plasma etching process of a metal film, and a method of manufacturing the same.

According to one aspect of the present invention, a semiconductor device having a guard ring having a PN diode is provided. The semiconductor device includes a semiconductor substrate having a chip region and a guarding region surrounding the chip region. A p well region is disposed in the semiconductor substrate in the chip region and the guard ring region. An n + region is disposed above the p well region of the guard ring region. A guard ring dam electrically connected to the n + region is disposed on the semiconductor substrate in the guard ring region. The p well region and the n + region in the guard ring region constitute a guard ring PN diode.

In some embodiments of the present invention, the semiconductor device may further include a gate disposed on the semiconductor substrate in the chip region. A first interlayer insulating film covering the gate, a direct contact penetrating the first interlayer insulating film, a bit line disposed on the first interlayer insulating film to cover the direct contact, a second interlayer insulating film covering the bit line, A metal contact penetrating the second interlayer insulating film, a first metal wiring disposed on the second interlayer insulating film to cover the metal contact, a third interlayer insulating film covering the first metal wiring, and a third interlayer insulating film The via contact may further include a second metal wire on the third interlayer insulating layer to cover the via contact.

In other embodiments, an antenna diode in contact with the direct contact may be disposed in the semiconductor substrate in the chip region.

In still other embodiments, the guard ring dam may include a first contact penetrating the first interlayer insulating layer and contacting the n + region, and a first conductive pattern disposed on the first interlayer insulating layer to cover the first contact. A second contact penetrating the second interlayer insulating layer covering the first conductive pattern to contact the first conductive pattern; a second conductive pattern disposed on the second interlayer insulating layer to cover the second contact; A third contact penetrating the third interlayer insulating film covering the second conductive pattern and contacting the second conductive pattern; and a third conductive pattern disposed on the third interlayer insulating film to cover the third contact. Can be.

In still other embodiments, any one of the first metal wire and the second metal wire may be electrically connected to the guard ring dam. When the wire electrically connected to the guard ring dam is the first metal wire, the first metal wire may be connected to the second conductive pattern. When the wire electrically connected to the guard ring dam is the second metal wire, the second metal wire may be connected to the third conductive pattern.

In still other embodiments, the first, second and third contacts may be the same material layer as the direct contact, the metal contact, and the via contact, respectively.

In example embodiments, the first, second and third conductive patterns may be formed of the same material layer as the bit line, the first metal wiring, and the second metal wiring, respectively.

According to another aspect of the present invention, a method of manufacturing a semiconductor device having a guard ring having a PN diode is provided. The method includes preparing a semiconductor substrate having a chip region and a guardring region surrounding the chip region. A p well region is formed in the semiconductor substrate of the chip region and the guard ring region. A n + region is formed over the p well region in the guard ring region to form a guard ring PN diode. A guard ring dam electrically connected to the n + region is formed on the semiconductor substrate in the guard ring region.

In some embodiments of the present disclosure, the forming of the guard ring dam may include forming a first interlayer insulating film on the semiconductor substrate having the n + region and penetrating the first interlayer insulating film to contact the n + region. Forming a contact, forming a first conductive pattern covering the first contact on the first interlayer insulating film, forming a second interlayer insulating film covering the first conductive pattern, and penetrating the second interlayer insulating film Forming a second contact in contact with the first conductive pattern, forming a second conductive pattern covering the second contact on the second interlayer insulating film, and forming a third interlayer insulating film covering the second conductive pattern, And forming a third contact penetrating the third interlayer insulating layer to contact the second conductive pattern, and forming a third conductive pattern covering the third contact on the third interlayer insulating layer. .

In other embodiments, the first contact, the first conductive pattern, the second contact, the second conductive pattern, the third contact, and the third conductive pattern may be formed in the chip region, respectively, during the direct contact, the bit line, The metal contact, the first metal wire, the via contact, and the second metal wire may be simultaneously formed.

In other embodiments, a gate may be formed on the semiconductor substrate in the chip region before forming the first interlayer insulating layer.

In still other embodiments, the antenna PN diode may be formed by forming a chip n + region in a portion of the chip region while forming the n + region in the guard ring region.

In still other embodiments, any one of the first metal wire and the second metal wire may be formed to be electrically connected to the guard ring dam. When the wire electrically connected to the guard ring dam is the first metal wire, the first metal wire may be connected to the second conductive pattern. When the wire electrically connected to the guard ring dam is the second metal wire, the second metal wire may be connected to the third conductive pattern.

In other embodiments, the first, second and third contacts may be formed of the same material layer as the direct contact, the metal contact, and the via contact, respectively.

In other embodiments, the first, second and third conductive patterns may be formed of the same material layer as the bit line, the first metal wiring, and the second metal wiring, respectively.

In still other embodiments, the forming of the first, second and third conductive patterns, the bit line, the first metal wiring and the second metal wiring may include forming a metal film on the interlayer insulating film, The metal layer may be etched by a reactive ion etching (RIE) process. In this case, electrons generated during the RIE process may be discharged through the guard ring PN diode and the antenna PN diode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

4 is a plan view illustrating a method of manufacturing a semiconductor device in accordance with embodiments of the present invention, and FIGS. 5 to 8 are cut views of FIG. 4 to explain a method of manufacturing a semiconductor device in accordance with embodiments of the present invention. Sections along the line II-II '. Reference numerals' V 'and' H 'denote cross-sectional views in the vertical and horizontal directions, respectively, at the cutting line II-II' of FIG. 4.

4 and 5, a semiconductor substrate 1 having a chip region CR1 and a provisional ring region GR1 surrounding the chip region CR1 is prepared. A p well region 5 is formed in the semiconductor substrate 1 in the chip region CR1 and the guard ring region GR1. The n + region 10b is formed on the p well region 5 in the guard ring region GR1 to form the guard ring PN diode AD2. In addition, the n + region 10b may be formed, and the chip n + region 10a may also be formed on the p well region 5 in the chip region CR1. As a result, the antenna PN diode AD0 can be formed. In the case of the antenna PN diode AD0, when the space of the chip region CR1 is insufficient, the antenna PN diode AD0 may be omitted.

Subsequently, gates 20 may be formed on the semiconductor substrate 1 of the chip region CR1. The gates 20 may be formed of a gate insulating film 20a and a gate electrode 20b that are sequentially stacked. A first interlayer insulating layer 25 may be formed on the semiconductor substrate having the gates 20 to cover the gates 20. Direct contacts 27a may be formed through the first interlayer insulating layer 25 to contact the semiconductor substrate 11 and the gates 20 of the chip region CR1. At the same time, a first contact 27b may be formed in contact with the n + region 10b of the guard ring region GR1.

Subsequently, a first metal layer 130 covering the direct contacts 27a and the first contact 27b may be formed on the first interlayer insulating layer 25. A first mask pattern 32 is formed on the first metal layer 130. Plasma etching of a reactive ion etching (RIE) process may be performed using the first mask pattern 32 as an etching mask. At this time, charges are charged-up to the surface of the semiconductor device by the plasma etching, and these charge-up charges are discharged through the antenna diode AD1 and the guard ring PN diode AD2. Can be charged (D1, D2). Alternatively, when the antenna diode AD1 is omitted, it may be discharged D2 only through the guard ring PN diode AD2. Therefore, even when there is not enough space in the chip region CR1 to form the antenna diode AD1 as the semiconductor device is reduced in size, the plasma damage phenomenon occurs by discharging the charge D2 through the guard ring PN diode AD2. Can be prevented.

4 and 6, all of the first metal layer 130 is etched to contact the direct contacts 27a and the first contact 27b, respectively. 30b) is formed. Next, the first mask pattern 32 is removed.

4 and 7, a second interlayer insulating layer 35 covering the bit line 30a and the first conductive pattern 30b is formed. A metal contact 37a and a second contact 37b are formed through the second interlayer insulating layer 35 to contact the bit line 30a and the first conductive pattern 30b, respectively. A first metal wire 40a and a second conductive pattern 40b are formed on the second interlayer insulating layer 35 to cover the metal contact 37a and the second contact 37b, respectively. The method of forming the first metal wire 40a and the second conductive pattern 40b is the same as the method of forming the bit line 30a and the first conductive pattern 30b described with reference to FIGS. 5 and 6. Can be formed.

Next, a third interlayer insulating layer 45 is formed to cover the first metal wiring 40a and the second conductive pattern 40b. The first via contact 47a and the third contact 47b are formed through the third interlayer insulating layer 45 to contact the first metal wiring 40a and the second conductive pattern 40b, respectively. A second metal wiring 50a and a third conductive pattern 50b may be formed on the third interlayer insulating layer 45 to cover the first via contact 47a and the third contact 47b, respectively. The method of forming the second metal wiring 50a and the third conductive pattern 50b is the same as the method of forming the bit line 30a and the first conductive pattern 30b described with reference to FIGS. 5 and 6. Can be formed.

In addition, a fourth interlayer insulating film 55 is formed to cover the second metal wiring 50a and the third conductive pattern 50b. A second via contact 57a and a fourth contact 57b are formed through the fourth interlayer insulating layer 55 to contact the second metal wiring 50a and the third conductive pattern 50b, respectively. A second metal layer 60 is formed on the fourth interlayer insulating layer 55 to cover the second via contact 57a and the fourth contact 57b. A second mask pattern 63 is formed on the second metal layer 60.

Plasma etching of a reactive ion etching (RIE) process may be performed using the second mask pattern 63 as an etching mask. In this case, charges are charged-up to the surface of the semiconductor device by the plasma etching, and the charged-up charges are discharged through the antenna diode AD1 and the guarding PN diode AD2. (D1, D2) can be. Alternatively, when the antenna diode AD1 is omitted, it may be discharged D2 only through the guard ring PN diode AD2. Therefore, even when there is not enough space in the chip region CR1 to form the antenna diode AD1 as the semiconductor device is reduced in size, the plasma damage phenomenon occurs by discharging the charge D2 through the guard ring PN diode AD2. Can be prevented.

4 and 8, the second metal layer 60 is etched to form a third metal wire 60a in contact with the second via contact 57a and the fourth contact 57b. Can be. In this case, the third metal wire 60a may extend to the guard ring GR1 region. Next, the second mask pattern 32 is removed. The first contact 27b, the first conductive pattern 30b, the second contact 37b, the second conductive pattern 40b, the third contact 47b, and the third conductive pattern in the guard ring region GR1 50b), the fourth contact 57b and the third metal wiring 60a may constitute the guard ring dam G1. In addition, the guard ring dam G1 and the guard ring PN diode AD2 may constitute a guard ring G2.

The guard ring G2 is in a state of being electrically connected to the third metal wiring 60a. Therefore, when a voltage of VDD or Vpp is applied to the third metal wire 60a, the same guard voltage G2 is also applied. As a result, the guard ring PN diode AD2 is subjected to reverse bias. Alternatively, instead of the third metal wire 60a, any one of the second metal wire 50a, the first metal wire 40a and the bit line 30a may extend to the guard ring region GR1. It may be formed by.

Referring to FIGS. 4 and 8 again, a semiconductor device according to example embodiments will be described. Reference numerals' V 'and' H 'denote cross-sectional views in the vertical direction and the horizontal direction, respectively, at the cutting line II-II' of FIG. 4.

4 and 8, the semiconductor device includes a semiconductor substrate 1 having a chip region CR1 and a guard ring region GR1 surrounding the chip region CR1. The p well region 5 is disposed in the semiconductor substrate 1 in the chip region CR1 and the guard ring region GR1. An n + region 10b is disposed above the p well region 5 in the guard ring region GR1. The p well region 5 and the n + region 10b in the guard ring region GR1 may constitute a guard ring PN diode AD2. In addition, a chip n + region 10a may be disposed on the p well region 5 in the chip region CR1. The p well region 5 and the chip n + region 10a in the chip region CR1 may constitute an antenna PN diode AD0. The antenna PN diode AD0 may be omitted.

Gates 20 may be disposed on the semiconductor substrate 1 of the chip region CR1. The gates 20 may be a gate insulating film 20a and a gate electrode 20b that are sequentially stacked. A first interlayer insulating layer 25 covering the gates 20 may be disposed on the semiconductor substrate having the gates 20. Direct contacts 27a may be disposed through the first interlayer insulating layer 25 to contact the semiconductor substrate 11 and the gates 20 of the chip region CR1. The first contact 27b may be disposed to contact the n + region 10b of the guard ring region GR1. A bit line 30a and a first conductive pattern 30b may be disposed on the first interlayer insulating layer 25 to cover the direct contacts 27a and the first contact 27b, respectively.

A second interlayer insulating layer 35 may be disposed to cover the bit line 30a and the first conductive pattern 30b. A metal contact 37a and a second contact 37b may be disposed through the second interlayer insulating layer 35 to contact the bit line 30a and the first conductive pattern 30b, respectively. A first metal wire 40a and a second conductive pattern 40b may be disposed on the second interlayer insulating layer 35 to cover the metal contact 37a and the second contact 37b, respectively.

A third interlayer insulating layer 45 may be disposed to cover the first metal wire 40a and the second conductive pattern 40b. First via contact 47a and third contact 47b may be disposed to penetrate the third interlayer insulating layer 45 to contact the first metal wire 40a and the second conductive pattern 40b, respectively. have. A second metal wiring 50a and a third conductive pattern 50b may be disposed on the third interlayer insulating layer 45 to cover the first via contact 47a and the third contact 47b, respectively.

A fourth interlayer insulating layer 55 may be disposed to cover the second metal wiring 50a and the third conductive pattern 50b. A second via contact 57a and a fourth contact 57b may be disposed to penetrate the fourth interlayer insulating layer 55 and contact the second metal wiring 50a and the third conductive pattern 50b, respectively. . A third metal wire 60a may be disposed on the fourth interlayer insulating layer 55 to cover the second via contact 57a and the fourth contact 57b, respectively. The third metal wire 60a may extend to the guard ring region GR1.

The first contact 27b, the first conductive pattern 30b, the second contact 37b, the second conductive pattern 40b, the third contact 47b, and the third conductive pattern in the guard ring region GR1 50b), the fourth contact 57b and the third metal wiring 60a may constitute the guard ring dam G1. In addition, the guard ring dam G1 and the PN diode AD2 may constitute a guard ring G2.

The guard ring G2 is electrically connected to the third metal wire 60a of the chip region CR1. Therefore, when a voltage of VDD or Vpp is applied to the third metal wire 60a, the same guard voltage G2 is also applied. As a result, the guard ring PN diode AD2 is subjected to reverse bias. Alternatively, one of the second metal wiring 50a, the first metal wiring 40a, and the bit line 30a may extend to the guard ring region GR1 instead of the third metal wiring 60a. It may be arranged.

As described above, according to the present invention, a guard ring PN diode is formed in a guard ring region of a semiconductor device, and the capacitor is charged by a charge-up phenomenon in an etching process using a plasma during the manufacturing process of the semiconductor device. The charge can be discharged through the antenna diode in the chip region and simultaneously discharged through the guard ring PN diode. Alternatively, there is not enough space to form an antenna diode in the chip region as the semiconductor element is reduced, and even when the antenna diode is omitted, the charge is discharged through the guard ring PN diode, thereby preventing plasma damage. You can do it. In addition, by electrically connecting the guard ring to any one of the bit lines and the metal wires of the chip region, current flow can be prevented by applying a reverse bias to the guard ring PN diode.

Claims (20)

A semiconductor substrate having a chip region and a guardring region surrounding the chip region; A p well region disposed in the semiconductor substrate in the chip region and the guard ring region; An n + region disposed above the p well region of the guard ring region; And a guard ring dam electrically connected to the n + region on the semiconductor substrate in the guard ring region, wherein the p well region and the n + region in the guard ring region constitute a guard ring PN diode. The method of claim 1, A gate disposed on the semiconductor substrate in the chip region; A first interlayer insulating film covering the gate; A direct contact penetrating the first interlayer insulating film; A bit line disposed on the first interlayer insulating layer to cover the direct contact; A second interlayer insulating film covering the bit line; A metal contact penetrating the second interlayer insulating film; A first metal wire disposed on the second interlayer insulating film to cover the metal contact; A third interlayer insulating film covering the first metal wiring; A via contact penetrating through the third interlayer insulating film; And And a second metal wiring disposed on the third interlayer insulating layer to cover the via contact. The method of claim 2, And an antenna diode in contact with the direct contact in the semiconductor substrate in the chip region. The method of claim 2, The guard ring dam A first contact penetrating the first interlayer insulating film to contact the n + region; A first conductive pattern disposed on the first interlayer insulating layer to cover the first contact; A second contact penetrating the second interlayer insulating layer covering the first conductive pattern to contact the first conductive pattern; A second conductive pattern disposed on the second interlayer insulating layer to cover the second contact; A third contact penetrating the third interlayer insulating layer covering the second conductive pattern to contact the second conductive pattern; And And a third conductive pattern disposed on the third interlayer insulating film to cover the third contact. The method of claim 4, wherein Any one of the first metal wiring and the second metal wiring is electrically connected to the guard ring dam. The method of claim 5, wherein And the first metal wire is connected to the second conductive pattern when the wire electrically connected to the guard ring dam is the first metal wire. The method of claim 5, wherein And the second metal wiring is connected to the third conductive pattern when the wiring electrically connected to the guard ring dam is the second metal wiring. The method of claim 4, wherein And the first, second and third contacts are the same material layer as the direct contact, the metal contact and the via contact, respectively. The method of claim 4, wherein The first, second and third conductive patterns are the same material layer as the bit line, the first metal wiring and the second metal wiring, respectively. Preparing a semiconductor substrate having a chip region and a guardring region surrounding the chip region, Forming a p well region in the semiconductor substrate of the chip region and the guard ring region, A n + region is formed on the p well region in the guard ring region to form a guard ring PN diode; And forming a guard ring dam electrically connected to the n + region on the semiconductor substrate in the guard ring region. The method of claim 10, Forming the guard ring dam Forming a first interlayer insulating film on the semiconductor substrate having the n + region, Forming a first contact penetrating the first interlayer insulating film and in contact with the n + region; Forming a first conductive pattern covering the first contact on the first interlayer insulating film; Forming a second interlayer insulating film covering the first conductive pattern, Forming a second contact penetrating the second interlayer insulating film to contact the first conductive pattern; Forming a second conductive pattern on the second interlayer insulating film to cover the second contact; Forming a third interlayer insulating film covering the second conductive pattern; Forming a third contact penetrating the third interlayer insulating film to contact the second conductive pattern; And forming a third conductive pattern covering the third contact on the third interlayer insulating film. The method of claim 11, While forming the first contact, the first conductive pattern, the second contact, the second conductive pattern, the third contact, and the third conductive pattern, a direct contact, a bit line, a metal contact, and a first metal wiring in the chip region. And a via contact and a second metal wiring are formed at the same time. The method of claim 12, And forming a gate on the semiconductor substrate in the chip region before forming the first interlayer insulating film. The method of claim 12, While the n + region is formed in the guard ring region, a chip n + region is formed in a partial region of the chip region to form an antenna PN diode. The method of claim 12, The method of manufacturing a semiconductor device, wherein any one of the first metal wiring and the second metal wiring is formed to be electrically connected to the guard ring dam. The method of claim 15, And the first metal wire is connected to the second conductive pattern when the wire electrically connected to the guard ring dam is the first metal wire. The method of claim 15, And the second metal wiring is connected to the third conductive pattern when the wiring electrically connected to the guard ring dam is the second metal wiring. The method of claim 12, And the first, second and third contacts are formed of the same material film as the direct contact, the metal contact and the via contact, respectively. The method of claim 12, The first, second and third conductive patterns are formed of the same material film as the bit line, the first metal wiring and the second metal wiring, respectively. The method of claim 12, Forming the first, second and third conductive patterns, the bit line, the first metal wiring and the second metal wiring Forming a metal film on the interlayer insulating film, Etching the metal layer by a reactive ion etching (RIE) process, wherein electrons generated during the RIE process are discharged through the guard ring PN diode and the antenna PN diode. Is a method of manufacturing a semiconductor device.

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