KR20080012088A - Method of performing log base 2 operation in k-bit microprocessor, scale factor decoding method using the same, record media recored program for realizing the same, and apparatus for performing log base 2 operation - Google Patents

Abstract

A method for performing a log base 2 operation in a K-bit microprocessor, a scale factor decoding method using the same, a recording medium storing a program for the same, and a log base 2 operation device are provided to reduce operation quantity for the log base 2 operation largely through a CLZ(Count Leading Zero) operation by requiring a specific number of clock cycles irrespective of an input value. A CLZ processor(710) calculates a CLZ value by performing the CLZ operation for a K-bit binary input value. An operator(720) outputs a difference value between 'K-1' and the CLZ value as a log base 2 operation result value for the K-bit binary input value. The CLZ processor outputs the number of zeros between the MSB(Most Significant Bit) to a first effective number bit of the K-bit binary input value wherein the first effective number bit represents a bit having '1' at first. An adder(730) adds one to the log base 2 operation result value for the K-bit binary input value when a binary value stored in a predetermined flag bit has a predetermined binary value. The K-bit microprocessor is a 32-bit RISC(Reduced Instruction Set Computer).

Description

A method of performing log base 2 operation in a K-bit microprocessor, a scale factor decoding method using log base 2 operation, a recording medium and a log base 2 operation device having a program for implementing the same K-BIT MICROPROCESSOR, SCALE FACTOR DECODING METHOD USING THE SAME, RECORD MEDIA RECORED PROGRAM FOR REALIZING THE SAME, AND APPARATUS FOR PERFORMING LOG BASE 2 OPERATION}

1 is a flowchart illustrating a log base 2 calculation method in processing a general digital signal.

FIG. 2 is a diagram showing the values of CLZ and code expressed in binary to input integer values in 32-bit RISC.

3 is a flowchart illustrating a log base 2 calculation method when processing a digital signal according to an embodiment of the present invention.

4 is a flowchart illustrating a log base 2 calculation method when rounding is applied according to another embodiment of the present invention.

FIG. 5 is a diagram comparing clock cycles required when the conventional log base 2 operation method is processed in the 32-bit RISC and the log base 2 operation method according to the present invention.

6 is a block diagram illustrating an apparatus for calculating a log base 2 in a K-bit RISC according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

610: CLZ processing unit 620: arithmetic unit

The present invention relates to a method of performing a log base 2 operation in a K-bit (K is a natural number) microprocessor. More particularly, the present invention relates to a K-bit (K is a natural number), which can reduce a clock cycle required in processing a log base 2 operation. A method for performing log base 2 operations in a microprocessor.

In the field of digital signal processing, mathematical modeling and other transcendental functions (log, exp, cos, sin, etc.) are often used. Among them, log base 2 (log ₂ ), which is one of logarithmic methods, is used in scale factor decoding and the like in the field of digital signal processing.

The log base 2 operation is used in case of scaling factor decoding, for example, in MPEG1 audio layer-3 (MP3) file decoding or window media audio (WMA) decoding.

The scale factor processing process is performed at every decoding process and occupies a large share of about 15% in the computational amount.

In general digital signal processing, to program log base 2 (log ₂ ), programming is usually done using the following C source code.

[Source code 1]

int LOG2_Floor (int i)

{

     int iLog2 = 0; Initial value setting

      while (((int) i >> iLog2)> 1); >> means ÷ 2 as right shift

          iLog2 ++; iLog2 increased by 1

      return iLog2; Returns iLog2 Value

}

[Source code 2]

  int LOG2_Ceil (int i)

{

      int iLog2 = 0;

      while (((int) 1 << iLog2)> i); << means × 2 left shift

          iLog2 ++;

      return iLog2;

}

For example, if you want to compute log ₂ 3, you can put input i = 3 (decimal) = 0b11 (binary), and the output value iLog2 will be the value of log ₂ 3 if you use LOG2_Floor () in source code 1. 1 is obtained by truncating the decimal point value from (1.584…), and the output value iLog2 is rounded up if the value of log ₂ 3 (1.584…) has a decimal point when LOG2_Ceil () of source code 2 is used. Obtained.

Also, if the input i = 536870912 (decimal) = 0x20000000 (hexadecimal) = 0b100000000000000000000000000000 (binary), the output value iLog2 uses LOG2_Floor () in source code 1 and LOG2_Ceil () in source code 2 All 29 are the same.

Also, if input i = 536871912 (decimal) = 0x 200003E8 (hexadecimal) = 0b100000000000000000001111101000 (binary), the output value is 29 when using LOG2_Floor () in source code 1, and LOG2_Ceil () in source code 2 30 is used.

If source code 1 and source code 2 were actually run on ARM9E, a 32-bit Reduced Instruction Set Computer (RISC), they are compiled into assemblers of source code 3 and source 4, respectively. Source code 3 and 4 below is the code analyzed by CROSS-ASM in the ARMULATOR.

[Source code 3]

[LOG2_Floor () behavior]

    a1) MOV r1, r0; load input i

    b1) MOV r0, # 0; load 0

Go_to

    c1) MOV r2, r1, ASR r0; i >> iLog2

    d1) CMP r2, # 1; if ((i >> iLog2)> 1) (compare)

    e1) ADDGT r0, r0, # 1; iLog2 ++

    f1) BGT Go_to; jump to Go_to (branch)

    g1) BX r14; return iLog2

[Source code 4]

[LOG2_Ceil () behavior]

    a2) MOV r2, r0; load input i

    b2) MOV r0, # 0; load 0

    c2) MOV r1, # 1; load 1

Go_to

    d2) MOV r3, r1, LSL r0; 1 << iLog2

    e2) CMP r3, r2; if ((1 << iLog2) <i) (compare)

    f2) ADDLT r0, r0, # 1; iLog2 ++

    g2) BLT Go_to; jump to Go_to (branch)

    h2) BX r14; return iLog2

1 is a flowchart illustrating a log base 2 calculation method in processing a general digital signal. Initialization step 10 includes initializing an input value, including steps a1) and b1) of source code 3, and steps a2), b2) and c2) of source code 4. The comparing and branching step (step 12) includes steps c1), d1), e1) and f1) of source code 3 and includes steps d2), e2), f2) and g2) of source code 4. .

The number of cycles required when the above operations in the source codes 3 and 4 are performed in the ARM9E which is a 32-bit RISC is as follows.

First, using LOG2_Floor () shown in source code 3, where N represents the exponent N at 2 ^N , the following cycle takes.

Step 1) 7 cycles for input value and other initialization

Step2) 7 cycles required for comparison and branching

Step3) Final Cycle = 7 + 7 * (N + 1) (all cases)

Next, using LOG2_Ceil () shown in source code 4, where N means exponent N at 2 ^N , takes the following cycle.

Step1) Input cycles and other cycles required for initialization are 7 + 1 = 8 cycles (added by one cycle by the code "MOV r1, # 1" which rounds source code 4)

Step2) 7 cycles required for comparison and branching

Step3) Final Cycle = 8 + 7 * (N + 1) (when input value (i) is a power of 2)

       Last Cycle = 8 + 7 * (N + 2) (if input (i) is not a power of 2)

Since the number of comparisons and branches is proportional to N, the total number of cycles for comparisons and branches is proportional to N related to the magnitude of the input value.

Therefore, log base 2 operations are logged in proportion to the number of comparison and branch routines required when implemented using a compare / branch routine as disclosed in the professional version specification of a conventional Window Media Audio (WMA) decoder. The total number of cycles required for the base 2 operation is increased, and the total number of cycles required for the base value is greatly increased.

As a result, the WMA decoding or the MPEG1 Audio layer-3 (MP3) decoding, which performs the scale factor decoding operation using the log base 2 operation, increases the number of cycles required for the operation, thus increasing the computation time and thus preventing efficient decoding. There is a problem.

Accordingly, a first object of the present invention is to perform a log base 2 operation method in a K-bit microprocessor that can reduce the number of clock cycles required to perform log base 2 operation in a K-bit (K is a natural number) microprocessor, and to perform the same. It is to provide a recording medium in which a program is recorded.

A second object of the present invention is to provide a scale factor decoding method using the log base 2 calculation method and a recording medium on which a program for performing the same is recorded.

It is also a third object of the present invention to provide a log base 2 operation apparatus capable of reducing the number of clock cycles required to perform log base 2 operations in a K-bit (K is a natural number) microprocessor.

According to an aspect of the present invention for achieving the above-described first object of the present invention, a method for performing log-base 2 operation in a K-bit (K is a natural number) microprocessor may include a K-bit binary input value, wherein a binary input value. Calculating a preceding zero count operation value by performing a preceding zero count operation on a natural number; And outputting a difference value between one of K-1 and K and the preceding zero count operation value as a log base 2 operation result value for the K-bit binary input value. The log base 2 operation result value for the K-bit binary input value is a difference value between K-1 and the preceding zero count operation value when a binary value stored in a preset flag bit has a first binary value. Can be. The log base 2 operation result value for the K-bit binary input value may be a difference between K and the preceding zero count operation value when a binary value stored in a preset flag bit has a second binary value. have. The log base 2 operation performing method may be used for scale factor decoding when decoding MP3 (MPEG1 Audio layer-3). The log base 2 operation performing method may be used to decode the scale factor when decoding the WMA (Window Media Audio). The K-bit microprocessor may be a 32-bit reduced instruction set computer (RISC).

According to an aspect of the present invention for achieving a second object of the present invention, a scale factor decoding method using a log-base 2 operation in a K-bit (K is a natural number) microprocessor is a K-bit binary input value. Performing a leading zero count operation on the binary input value being a natural number to produce a leading zero count operation value; Outputting a difference value between one of K-1 and K and the preceding zero count operation value as a log base 2 operation result value for the K-bit binary input value; And performing scale factor decoding based on the log base 2 operation result value.

Log-base 2 computing device in the K-bit (K is a natural number) microprocessor according to an aspect of the present invention for achieving the third object of the present invention is a K-bit binary input value, where the binary input value is a natural number A leading zero count processor for performing a leading zero count operation on-to calculate a leading zero count operation value; And an operation unit for outputting a difference value between K-1 and the preceding zero count operation value as a log base 2 operation result value for the K-bit binary input value. The K-bit microprocessor may be a 32-bit reduced instruction set computer (RISC).

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

The present invention can be embodied as computer readable codes on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, and the like, and are also implemented in the form of a carrier wave (for example, transmission over the Internet). It also includes. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted.

Log base 2 (log ₂ ) operations in conventional digital signal processing require many clock cycles because they include a comparison routine and a branch routine. In the present invention, in order to efficiently reduce clock cycles required for log base 2 (log ₂ ) operations in digital signal processing, a leading counting zero (CLZ) operation is used. For example, the leading zero count (CLZ) operation can be implemented using the leading zero count (CLZ) instruction provided in ARMv5E, a 32-bit RISC of the ARM9 series.

The CLZ operation counts how many zeros are between the most significant bit of the first bit (that is, the first significant digit). For example, it works in the following manner.

PRE r1 = 0b 0000 0000 0000 0000 0000 0000 000 1 0000

CLZ r0, r1

POST r0 = 27

In the above example, since 0 is 27 times from the most significant bit and 1 is first, 27 is returned in the CLZ operation result r0. The CLZ operation counts the number of zeros before the first significant digit. The leading zero count instruction used in 32-bit RISC returns 32 if there is no bit before the first significant digit.

FIG. 2 is a diagram showing the values of CLZ and code expressed in binary to input integer values in 32-bit RISC. 'X' of FIG. 2 may have any value of either '1' or '0'.

The CLZ instruction is very useful for routines that need to normalize their numbers. When the first leading digit, the most significant bit of an integer, is at a known bit position, the integer is said to be "normalized." For example, the integer 9 can be represented as a binary value, which is 0b00001001, where the significant digit is 1001, and the leftmost 1 is the first leading digit.

Normalization is required to implement Newton-Raphson division or to convert to floating-point format. Normalization is also useful for priority decoders used in computing algorithms or in some scheduling routines. In such an application, both the normalization value and the shift value required to reach the normalization value must be known.

The CLZ value is used as the number of shifts when shifting left so that the first significant digit is located in the 31st bit in 32-bit RISC, such as ARMv5E.

3 is a flowchart illustrating a log base 2 calculation method when processing a digital signal according to an embodiment of the present invention, and FIG. 4 illustrates a log base 2 calculation method when rounding is applied according to another embodiment of the present invention. It is a flow chart. 3 and 4 illustrate a log base 2 operation method in digital signal processing using a K-bit reduced instruction set computer (RISC) as an example. Here, the K value may be 32, for example.

Referring to FIG. 3, the K-bit input value i is loaded (step 301).

The number of zeros between the first significant digit bit representing the first bit in the most significant bit of the input value i is counted (step 303).

Then, the difference between K-1 and the number of zeros is obtained (step 305). The difference between (K-1) and the number of zeros is the log ₂ i value for the input value (i).

Referring to FIG. 4, the first significant digit bit (leading one) indicating the first bit of the first bit of the most significant bit of the input value (i) is loaded (step 401). After counting the number of zeros (), the difference value between K and the number of zeros is calculated (step 405). FIG. 4 adds 1 by applying rounding when the log base 2 calculation result log ₂ i has a value below the decimal point. Therefore, instead of calculating the difference between (K-1) and the number of 0s, Find the difference between the numbers. That is, when the log base 2 calculation result log ₂ i has a value below the decimal point, a difference value between K and the number of 0 is a log ₂ i value obtained by applying rounding to the input value (i).

The log base 2 operation method using the preceding zero count of FIG. 3 may be implemented as an inline assembling function as follows.

[Source code 5]

__inline int LOG2_Floor (int i)

{

      int iLog2;

      __asm; Code contained in {} below asm means assembly code

      {

          CLZ iLog2, i

      }

      return (31-iLog2);

}

The logbase 2 operation method using the preceding zero count of FIG. 4 may be implemented as an inline assembling function as follows.

[Source code 6]

__inline int LOG2_Ceil (int i)

{

int iLog2;

      __asm; Code contained in {} below asm means assembly code

      {

          CLZ iLog2, i

      }

      return (32-iLog2);

}

Referring to the source codes 5 and 6, an input value i is input, and the number of zeros is stored in iLog2 through a preceding zero count (CLZ) process. If the result value (31-iLog2) is returned as shown in source code 5 using the preceding zero count (CLZ) value, the desired log base 2 operation result (log ₂ i) is obtained. In the source code 6, when the binary value stored in the predetermined flag bit instructs to execute the LOG2_Ceil () function, the result value (32-iLog2) is returned for rounding, and the rounded log base 2 operation result ( log ₂ i) For example, if the binary value of the flag bit preset by the user is 0, this indicates a case of executing the LOG2_Floor () function to handle the case where the log base 2 operation result log ₂ i does not have a decimal point value. When the binary value of the flag bit is 1, it may represent a case of executing the LOG2_Ceil () function for processing the case where the log base 2 operation result log ₂ i has a decimal point value.

According to the conventional log base 2 calculation method of FIG. 1, since the number of comparison / branches is proportional to the input value (i), it is proportionally [7 + 7 * (N + 1)] or [according to the input value (i). 8 + 7 * (N + 1)] or [8 + 7 * (N + 2)] cycles.

The log base 2 calculation method in the digital signal processing according to the embodiment of the present invention of FIGS. 3 and 4 is an iterative loop composed of a conventional comparison routine and a branch routine, compared to the conventional log base 2 calculation method of FIG. 1. ), And it can be computed directly without repetitive loops to calculate the log base 2 result.

When the log base 2 operation method according to the embodiments of the present invention is applied to a 32-bit RISC, the size of the input value is determined until the log base 2 operation result is obtained by eliminating the comparison / branching process using the CLZ operation. It takes 3 cycles no matter what. This is because it takes one cycle to load the input value, one clock cycle to execute the preceding zero count (CLZ) instruction, and one clock cycle to return the CLZ-processed result.

Therefore, when the log base 2 calculation method is applied to digital signal processing using 32-bit RISC or the like when the digital signal is processed according to an embodiment of the present invention, the number of clock cycles required for the log base 2 operation is the number of comparison routines and branches. It has a constant value regardless of the number of routines and the size of the input value. That is, the log base 2 calculation method in the digital signal processing according to the embodiments of the present invention does not take a clock cycle proportionally to a conventional input value, but takes a certain number of clock cycles regardless of any input value. As a result, it is possible to greatly reduce the amount of computation during logbase 2 computation.

FIG. 5 is a diagram comparing clock cycles required when the conventional log base 2 operation method is processed in the 32-bit RISC and the log base 2 operation method according to the present invention. 5 shows the number of clock cycles measured using the ARM946E-S, which is a type of 32-bit RISC. N means exponent ^N at 2 ^N. FIG. 6 is a chart comparing clock cycles required when the logbase 2 calculation method of the present invention is processed with the logbase 2 calculation method of the present invention when the LOG2_Ceil () function of FIG. 5 is applied.

As shown in Figs. 5 and 6, the conventional log base 2 operation increases the cycle in proportion to N, but the proposed operation takes 3 cycles irrespective of N.

FIG. 5 illustrates only the case where the input values i are all powers of two, and FIG. 6 illustrates both the case where the input values i are powers of two and non-power squares. Referring to FIG. 6, when the LOG2_Ceil () function is applied, the input value i is 1, 2, 4, 8, 16,... In the case of 2 power, such as 1024, the number of clock cycles required is (8 + 7 * (N + 1)), and the input value (i) is 3, 5, 6, 7, 9,... As shown in the following figure, the number of clock cycles required is not (8 + 7 * (N + 2)).

7 is a block diagram illustrating an apparatus for calculating a log base 2 in K-bit RISC according to an embodiment of the present invention.

Referring to FIG. 7, the log base 2 operation apparatus according to an embodiment of the present invention includes a CLZ processing unit 710 and an operation unit 720.

The CLZ processor 710 receives the K-bit input value i and performs a preceding zero count (CLZ) operation. Specifically, the CLZ processor 710 outputs the CLZ result value by counting the number of zeros between the first significant digit bit representing the first one of the most significant bits of the K-bit input value i. do.

The operation unit 720 receives the CLZ result value and calculates a difference value between the (K-1) and the CLZ result value. In other words, the CLZ result is input and the CLZ result is subtracted from (K-1). Alternatively, when the binary value stored in the flag bit preset by the user has a predetermined value, the operation unit 720 performs a CLZ result to apply rounding when the log base 2 calculation result log ₂ i has a decimal point or less. Get the value and find the difference between K and CLZ. For example, when the binary value stored in the flag bit is 1, the difference value between K and the CLZ result may be obtained by receiving the CLZ result value to apply the rounding.

The log base 2 computing device adds 1 to the difference between the above (K-1) and the CLZ result in order to apply rounding when the log base 2 calculation result log ₂ i has a decimal point value 730. ) May be further included.

The log base 2 operation according to the embodiments of the present invention may be used for scale factor decoding during MP3 (MPEG1 audio layer-3) decoding. The MP3 decoder includes a parser, a Huffman decoding unit, an inverse quantization unit, and an IMDCT. Specifically, the decoding process of the MP3 file first contains the MP3 format bitstream input from the outside into the input buffer, reads the scale factor value using the data of the input buffer, and uses Huffman by side information and the scale factor. Decode, dequantize, and transform from frequency domain to time domain (IMDCT), etc., and then generate final audio data.

In the MP3 method, the original audio signal is recovered by scaling the region data by dividing it into a frequency band called a scale factor band without performing quantization on the entire audio band. The scale factor is divided into bands. In the scale factor decoding unit, the scale of inverse quantization is decoded from the side information. In the inverse quantization process, a log factor 2 operation is applied as a preliminary procedure for decoding the scale factor, and a coefficient value of the scale factor is obtained, and a shifter stores a predetermined number of scale factors stored in the memory. Scale factor decoding is performed by shifting the left side by the number of times corresponding to the log base 2 operation result value (the coefficient value of the scale factor) to obtain a plurality of desired scale factors.

Source code 7 below represents a pseudo-code of a routine for obtaining a coefficient value of a scale factor used in a scale factor selection information (scfsi) processor in decoding MP3.

[Source code 7]

Int mp3_Scfsi (A, B, C)

{

    for i = 0 to A do; A is the number of Spectrum values

      xr_sum = pow (abs (xr (i))); Calculation of energy using Spectrum

    en_tot = log 2_floor (xr_sum); Find total energy

    for j = 0 to B do; B is the number of subband (sb) as input factors

      top = lbl (j) + bw (j) -1; To calculate by bandwidth

      for k = lbl (j) to top do

          energy = pow (abs (xr (i))); Calculation of energy for each bandwidth

      en (j) = log 2_floor (energy); Calculation of energy for each band

      xm (j) = log 2_floor (C (j)); Calculate the available distortion values for each band

}

The source code 7 is a step of obtaining dictionary information for scale factor decoding and may use log2_floor or log2_ceil by an algorithm change.

Alternatively, the log base 2 operation according to the embodiments of the present invention may be used in the scale factor decoding unit during WMA decoding. Source code 8 below shows a pseudo-code of a routine for obtaining a coefficient value of a scale factor in a scale factor processing unit during WMA decoding.

[Source Code 8]

Int PreScale Coeff (A, B, C, D)

{

    for i = 0 to A do; A is variable as input factor

       if (B == 1)

         maxQuantStep = m_qfltMaxQuantStep; Select maximum value of quantization step

         ctMaxVal >> = maxQuantStep; Determine maximum value affecting coefficient

cLeftShiftBits = C- LOG2_Ceil (ctMaxVal); ctMaxVal is an integer from 1 to 2 ³⁴ . LOG2_Ceil (ctMaxVal) The result range is 0 ~ 34. C is the maximum value of the coefficient that can be used as an input factor and is an integer from 1 to 30. cLeftShiftBits is a shift value that generates coefficients.

       if (cLeftShiftBits> 0); Handling when cLeftShiftBits is Positive

         for j = 0 to iHi do

           rgiCoefRecon [j] << = cLeftShiftBits; By using j cLeftShiftBits scale factor coefficients.

       else; Handling when cLeftShiftBits is Negative

         for j = 0 to iHi do

                     rgiCoefRecon [j] >> = -cLeftShiftBits;

}

Alternatively, the log base 2 operation according to the embodiments of the present invention may be used in packet header decoding during WMA decoding. Alternatively, the log base 2 operation according to the embodiments of the present invention may be used in a packet header decoding process in a parser during MP3 decoding.

A method of performing a log base 2 operation in the K-bit (K is a natural number) microprocessor, a scale factor decoding method using the log base 2 operation, and a log base 2 operation in a K-bit (K is a natural number) microprocessor. According to the apparatus, it is possible to calculate a log base 2 operation result value for an input value using a CLZ operation without using an iteration loop composed of a comparison routine and a branch routine used in the conventional log base 2 operation method. .

Therefore, the log base 2 operation method is derived using the CLZ operation without using an iterative loop composed of a comparison routine and a branch routine. Thus, the log base 2 operation method according to the embodiments of the present invention is applied to a 32-bit RISC or the like. When applied, the number of clock cycles required for logbase 2 operation is constant regardless of the number of comparison routines, number of branch routines, and size of input values.

Accordingly, the log base 2 calculation method according to the embodiments of the present invention does not require clock cycles in proportion to the conventional input value, but only a certain number of clock cycles are required regardless of the input value. Can greatly reduce the amount of computation. Particularly, when the log base 2 operation method according to the embodiments of the present invention is applied to scale factor decoding in window media audio (WMA) decoding and scale factor decoding in MPEG1 audio layer-3 (MP3) decoding, the calculation amount can be greatly reduced. have.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (20)

A method for performing log base 2 operation in a K-bit (K is a natural number) microprocessor, Performing a preceding zero count operation on the K-bit binary input value, where the binary input value is a natural number to produce a preceding zero count operation value; And And outputting a difference value between one of K-1 and K and the preceding zero count operation value as a log base 2 operation result value for the K-bit binary input value. To perform log base 2 operations on. 2. The method of claim 1, wherein performing a preceding zero count operation on the K-bit binary input value comprises: a first significant number representing a bit in which the binary number '1' first appears in the most significant bit of the K-bit binary input value; And outputting the number of '0's between bits as the preceding zero count operation value. The method of claim 1, wherein the log base 2 operation result value for the K-bit binary input value is K-1 and the preceding zero count operation when a binary value stored in a preset flag bit has a first binary value. A method of performing a log base 2 operation in a K-bit microprocessor, characterized in that it is a difference from a value. The method of claim 1, wherein the log base 2 operation result value for the K-bit binary input value is equal to K and the preceding zero count operation value when a binary value stored in a preset flag bit has a second binary value. The method of performing a log base 2 operation in a K-bit microprocessor, characterized in that the difference value of. The method of claim 1, wherein the log base 2 operation is used to decode the scale factor when decoding the MP3 (MPEG1 Audio layer-3). 2. The method of claim 1, wherein the method for performing log base 2 operation is used for scale factor decoding in window media audio (WMA) decoding. 2. The method of claim 1, further comprising loading the K-bit binary input value. The method of claim 1, wherein the K-bit microprocessor is a 32-bit reduced instruction set computer (RISC). In the scale factor decoding method using log-base 2 operation in a K-bit (K is a natural number) microprocessor, Performing a preceding zero count operation on the K-bit binary input value, where the binary input value is a natural number to produce a preceding zero count operation value; Outputting a difference value between one of K-1 and K and the preceding zero count operation value as a log base 2 operation result value for the K-bit binary input value; And And performing scale factor decoding on the basis of the log base 2 operation result value. 10. The method of claim 9, wherein performing a preceding zero count operation on the K-bit binary input value comprises: a first significant digit bit representing a bit in which the binary number '1' first appears in the most significant bit of the K-bit binary input value; And a step of outputting the number of '0's as the preceding zero count operation value. 10. The method of claim 9, wherein the log base 2 operation result value for the K-bit binary input value is K-1 and the preceding zero count operation when a binary value stored in a preset flag bit has a first binary value. A scale factor decoding method using log-based two operations in a K-bit microprocessor, characterized in that it is a difference from a value. 10. The method of claim 9, wherein the log base 2 operation result value for the K-bit binary input value is equal to K and the preceding zero count operation value when a binary value stored in a preset flag bit has a second binary value. A scale factor decoding method using a log base 2 operation in a K-bit microprocessor, characterized in that the difference value of. 10. The method of claim 9, wherein the scale factor decoding method is used to decode the scale factor when decoding MP3 (MPEG1 audio layer-3). 10. The method of claim 9, wherein the scale factor decoding method is used to decode the scale factor during WMA (Window Media Audio) decoding. A program in which a program of instructions that can be executed by a K-bit microprocessor is tangibly implemented to perform a log base 2 operation, and a recording medium having recorded thereon a program that can be read by the K-bit (K is a natural number) microprocessor. To Performing a preceding zero count operation on the K-bit binary input value, where the binary input value is a natural number to produce a preceding zero count operation value; And And recording a difference value between one of K-1 and K and the preceding zero count operation value as a log base 2 operation result value for the K-bit binary input value. A program of instructions that can be executed by a K-bit (K is a natural number) microprocessor is tangibly implemented to perform a scale factor decoding method using a log base 2 operation, and can be read by the K-bit microprocessor. In the recording medium on which a program is recorded, Performing a preceding zero count operation on the K-bit binary input value, where the binary input value is a natural number to produce a preceding zero count operation value; Outputting a difference value between one of K-1 and K and the preceding zero count operation value as a log base 2 operation result value for the K-bit binary input value; And And a program for performing scale factor decoding based on the log base 2 operation result value. A log base 2 computing device in a K-bit (K is a natural number) microprocessor, A leading zero count processor for performing a leading zero count operation on the K-bit binary input value, where the binary input value is a natural number; And And a calculation unit for outputting a difference value between K-1 and the preceding zero count operation value as a log base 2 operation result value for the K-bit binary input value. 2 computing devices. 18. The method of claim 17, wherein the preceding zero count processor counts the number of '0's between the first significant digit bits representing the first bit of the binary number' 1 'from the most significant bit of the K-bit binary input value. Log base 2 computing device in the K-bit microprocessor characterized in that the output as an operation value. 18. The apparatus of claim 17, wherein the log base 2 computing device is And an adder for adding 1 to a log base 2 operation result value for the K-bit binary input value when the binary value stored in a preset flag bit has a predetermined binary value. Log base 2 computing unit in a bit microprocessor. 18. The apparatus of claim 17, wherein the K-bit microprocessor is a 32-bit reduced instruction set computer (RISC).

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