KR20080010928A - Method of forming contacthole and method of fabricating dram using the same - Google Patents

Abstract

A method for forming a contact hole and a method for fabricating a DRAM(Dynamic Random Access Memory) using the same are provided not to extend a contact plug downward but to contact the contact plug with a bit line even though the contact-hole is inclined to one side. A method for forming a contact hole includes the steps of: forming a conductive film pattern on a substrate(100); forming a first interlayer insulating film(125) covering the conductive film pattern; removing the first interlayer insulating film selectively to expose the conductive film pattern; forming a buffer spacer(126) for covering both side walls of the conductive pattern; forming a second interlayer insulating film for covering the conductive film pattern having the buffer spacer; and forming the contact hole to expose the conductive film pattern by etching the second insulation film. The buffer spacer is made of an insulation film having etch selectivity to the second interlayer insulation film.

Description

Method of forming a contact hole and manufacturing method of DRAM (DRM) using the same

1 is a cross-sectional view illustrating a method for forming a contact hole in a DRAM device according to the prior art.

2 to 8 are cross-sectional views illustrating a DRAM forming method according to an embodiment of the present invention.

The present invention relates to a method of forming a contact hole and a method of manufacturing a DRAM using the same, and more particularly, to a method of forming a contact hole capable of preventing contact failure and a method of manufacturing a DRAM using the same.

Semiconductor devices, such as dynamic random access memory (DRAM), have transistors, capacitors, load resistors, and interconnects. The interconnections include contact plugs for electrically connecting conductive structures. The contact plug may be formed in a contact hole that penetrates the interlayer insulating layer. As the semiconductor device is highly integrated, researches for reducing the two-dimensional size of the components and stacking them in a plurality of layers have been actively conducted. Accordingly, the aspect ratio of the contact hole increases, and the alignment margin of the patterning process decreases. That is, it is increasingly difficult to form the contact hole having a fine size at a desired position.

1 is a cross-sectional view illustrating a method for forming a contact hole in a DRAM device according to the prior art.

Referring to FIG. 1, the device isolation layer 12 may be formed in a predetermined region of the substrate 10. The lower conductive structure 20 including the oxide layer 21, the first conductive layer pattern 22, the hard mask 23, and the spacers 24 may be formed on the substrate 10 having the device isolation layer 12. Can be. An insulating layer 25 may be formed on the substrate 10 having the lower conductive structure 20. An upper conductive structure 30 including a second conductive layer pattern 31, a hard mask layer pattern 32, and a spacer 33 may be formed on the insulating layer 25. The upper conductive structure 30 may partially overlap the lower conductive structure 20. The lower interlayer insulating layer 35 and the upper interlayer insulating layer 40 may be sequentially formed on the substrate 10 having the upper conductive structure 30.

Subsequently, the contact hole 42 penetrating the interlayer insulating layers 35 and 40 may be formed using a patterning process. The patterning process may form a mask pattern (not shown), such as a photoresist pattern, on the upper interlayer insulating layer 40, and use the mask pattern as an etching mask to form the interlayer insulating layers 35 and 40 and the hard mask. Anisotropic etching of the film pattern 32 may be included in sequence. The contact hole 42 may be formed to sequentially pass through the upper interlayer insulating layer 40 and the lower interlayer insulating layer 35 to expose the second conductive layer pattern 31.

As shown in the figure, the patterning process may have an alignment error during the formation of the contact hole 42. That is, the contact hole 42 may be formed to be shifted by the arrow M due to the alignment error. In this case, the contact hole 42 may be biased toward one side of the second conductive layer pattern 31. Accordingly, a hole 42M extending in one side of the second conductive pattern 31 may be formed. The extended hole 42M may expose sidewalls of the second conductive pattern 31 and may partially expose the first conductive layer pattern 22 through the lower interlayer insulating layer 35.

Thereafter, a conductive film may be formed to fill the contact hole 42. Here, the first conductive layer pattern 22 and the second conductive layer pattern 32 should be insulated by the lower interlayer insulating layer 35. However, the inside of the extended hole 42M may also be filled with the conductive layer. That is, the second conductive layer pattern 31 may be electrically connected to the first conductive layer pattern 22 by the conductive layer filling the inside of the extended hole 42M. As a result, the elongated hole 42M causes contact failure.

An object of the present invention is to provide a method for forming a contact hole capable of preventing contact failure and a DRAM manufacturing method using the same.

According to an aspect of the present invention for achieving the above technical problem, a method for forming a contact hole is provided. The contact hole forming method includes forming a conductive film pattern on a substrate. A first interlayer insulating film covering the conductive film pattern is formed. The first interlayer insulating layer is selectively removed to expose the conductive layer pattern. Subsequently, a buffer spacer covering both sidewalls of the conductive film pattern is formed. A second interlayer insulating film covering the conductive film pattern having the buffer spacer is formed. The second interlayer insulating layer is etched to form a contact hole exposing the conductive layer pattern. The buffer spacer is formed of an insulating film having an etch selectivity with respect to the second interlayer insulating film.

In some embodiments of the present invention, the buffer spacer may be formed of a polysilicon film or a silicon nitride film.

In example embodiments, the forming of the buffer spacer may include conformally depositing a buffer spacer layer on the entire surface of the substrate having the conductive layer patterns, and anisotropically etching the buffer spacer layer. The buffer spacer layer may be formed to a thickness of 0.2 to 0.45 times the gap between the conductive patterns.

In another embodiment, before forming the conductive layer pattern, the method may further include forming an etch stop layer covering the entire surface of the substrate under the conductive layer pattern. The etch stop layer may be formed of a silicon nitride layer or an aluminum oxide layer.

According to another aspect of the present invention for achieving the above technical problem, there is provided a DRAM manufacturing method. The DRAM manufacturing method includes forming a bit line on a substrate having a cell region and a core / peripheral region. A first interlayer insulating film is formed on the substrate having the bit line. The first interlayer insulating layer of the core / peripheral region is selectively removed to expose the bit line of the core / peripheral region. Subsequently, both sidewalls of the bit line of the core / peripheral region form buffer spacers. A second interlayer insulating film covering the bit line having the buffer spacer is formed. Next, a cell capacitor is formed on the first interlayer insulating layer of the cell region, the cell capacitor being electrically connected to the substrate. An upper interlayer insulating film is formed on the entire surface of the substrate having the cell capacitor. The upper interlayer insulating layer and the second interlayer insulating layer are etched to form contact holes exposing bit lines of the core / peripheral region. The buffer spacer is formed of an insulating film having an etch selectivity with respect to the second interlayer insulating film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. Also, an element or layer is referred to as "on" or "on" of another element or layer by interposing another layer or other element in the middle as well as directly above the other element or layer. Include all cases.

Referring to Figures 2 to 8, it will be described in the DRAM manufacturing method according to an embodiment of the present invention. Cross-sectional views illustrating a DRAM forming method according to an embodiment of the present invention.

Referring to FIG. 2, a substrate 100 having a cell region A and a core / periphery region B is prepared.

An isolation layer 102 may be formed in the substrate 100. The device isolation layer 102 may be formed of a silicon oxide layer. Gate patterns 110 may be formed on the substrate 100 in the cell region A. The gate pattern 110 may be formed to include a gate dielectric layer 111, a gate electrode 112, a hard mask 113, and a spacer 114. In the gate pattern 110, the gate dielectric layer 111, the gate electrode 112, and the hard mask 113 may be sequentially stacked on the substrate 100. The spacer 114 may be formed on sidewalls of the gate electrode 112 and the hard mask 113. Source / drain regions 104 may be formed in the substrate 100 at both sides of the gate pattern 110. Landing pads 116 and 117 may be formed on the source / drain regions 104. The landing pads 116 and 117 may be classified into a bit line landing pad 116 and a storage landing pad 117. A lower interlayer insulating layer 115 may be formed on the substrate 100 having the gate pattern 110 and the landing pads 116 and 117. The lower interlayer insulating film 115 may be formed of a silicon oxide film, a silicon nitride film, or a combination thereof.

An etch stop layer 118 covering the entire surface of the substrate 100 may be formed on the lower interlayer insulating layer 115. The etch stop layer 118 may be formed of a silicon nitride layer or an aluminum oxide layer. A bit line contact plug 119 may be formed in the lower interlayer insulating layer 115 and the etch stop layer 118 to contact the bit line landing pad 116.

 Subsequently, bit line patterns 120 are formed on the etch stop layer 118. The bit line patterns 120 may be formed in the cell area A and the core / peripheral area B, respectively. The bit line patterns 120 may include a bit line 121, a hard mask pattern 122, and a spacer 123, respectively. The bit line patterns 120 may be formed by sequentially stacking the bit line 121 and the hard mask layer pattern 122, respectively. The spacer 123 may be formed on sidewalls of each of the bit line 121 and the hard mask layer pattern 122. The bit lines 121 may be formed of a polysilicon film, a tungsten (W) film, or a metal silicide film. In addition, the hard mask layer patterns 122 may be formed of a silicon nitride layer. The bit lines 121 may be in contact with the bit line contact plug 119, respectively. The bit line patterns 120 may be electrically connected to the bit line landing pads 116 by the bit line contact plugs 119, respectively. That is, the bit line patterns 120 may be electrically connected to the source / drain region 104 through the bit line contact plug 118 and the bit line landing pad 116, respectively.

The first interlayer insulating layer 125 is formed on the substrate 100 having the bit line patterns 120. The first interlayer insulating layer 125 may include a high density plasma oxide (HDP oxide) film, a BPSG (Bornon Phosporous Silicate Glass) film, a PE-TEOS (Plasma Enhanced Tetra Ethyl Ortho Silcate) film, a silicon oxynitride film, or a combination thereof. It can be formed into a film.

Referring to FIG. 3, the bit line patterns 120 of the core / peripheral region B may be removed by selectively removing the first interlayer insulating layer 125 of the core / peripheral region B by a patterning process. Expose The patterning process may be performed by using a mask pattern such as a photoresist pattern exposing the first interlayer insulating layer 125 of the core / ferri region B to form the first interlayer insulating layer 125 of the core / ferri region B. Etching may be included. In this case, the etching of the first interlayer insulating layer 125 may be terminated by the etch stop layer 118 in order to prevent overetching under the first interlayer insulating layer 125.

Next, the buffer spacer layer 126 may be conformally deposited on the entire surface of the substrate 100 having the bit line patterns 120. In this case, the first interlayer insulating layer 125 may prevent the buffer spacer layer 126 from being deposited on the bit line patterns 120 of the cell region A. FIG. The buffer spacer layer 126 may have an etching selectivity (etch rate of the buffer spacer / the second layer) with respect to a second interlayer insulating layer (see 128 in FIG. 4) that is subsequently formed in the core / peripheral region B. It may be an insulating film having an etch rate of the interlayer insulating film). For example, the buffer spacer layer 126 may be formed of a polysilicon layer or a silicon nitride layer. In addition, in order to secure an alignment margin in a process of forming a subsequent contact hole (146 of FIG. 7), the buffer spacer layer 126 may have a width w of 0.2 between the bit line patterns 120. It may be formed to have a thickness (t) of the fold to 0.45 times.

Referring to FIG. 4, the buffer spacer layer 126 is anisotropically etched to form buffer spacers 127 on both sidewalls of the bit line patterns 120 of the core / peripheral region B. Referring to FIG. When the buffer spacer 127 is formed of a silicon nitride film, a capping film (not shown) may be formed on the first interlayer insulating layer 125 of the cell region A to prevent the buffer spacer 127 from being etched under the first interlayer insulating layer 125. This can be formed. In the exemplary embodiment of the present invention, the buffer spacer is formed on both sidewalls of the bit line patterns 120 having the hard mask patterns 122 and the spacers 123. However, depending on the process conditions, the hard mask pattern and the spacer may be omitted to form the buffer spacer on both sidewalls of the bit line.

Next, a second interlayer insulating layer 128 covering the bit line pattern 120 having the buffer spacer 127 is formed. After depositing an insulating film (not shown) on the entire surface of the substrate 100 having the buffer spacer 127, the insulating film (not shown) using a chemical mechanical polishing (CMP) process or an etch back process (not shown) The second interlayer insulating film 128 is formed by planarizing the upper surface of the substrate. In this case, the second interlayer insulating layer 128 may be formed to have an upper surface substantially the same level as the upper surface of the first interlayer insulating layer 125. The second interlayer insulating layer 128 may be formed of a high density plasma oxide (HDP oxide) film, a BPS film, a PE-TEOS film, a silicon oxynitride film, or a combination thereof. Subsequently, a buried contact plug 129 may be formed to penetrate through the second interlayer insulating layer 128, the etch stop layer 118, and the lower interlayer insulating layer 115 to contact the storage landing pad 117. have.

Referring to FIG. 5, a storage pad 132 may be formed on the second interlayer insulating layer 128. The storage pad 132 may include a polysilicon film, a tungsten (W) film, an aluminum (Al) film, and the like. It may be formed of one selected from the group consisting of a copper (Cu) film. The storage pad 132 may be electrically connected to the storage landing pad 117 by the buried contact plug 129 penetrating through the second interlayer insulating layer 128 and the lower interlayer insulating layer 115. That is, the storage pad 132 may be electrically connected to the source / drain area 104 through the buried contact plug 129 and the storage landing pad 117.

Subsequently, a buffer layer 134 may be formed on the substrate 100 having the storage pad 132. The buffer layer 134 may be formed of a high density plasma oxide layer, a BP layer, a PE-TEOS layer, a silicon oxynitride layer, or a combination thereof.

Referring to FIG. 6, a cell capacitor 140 penetrating the buffer layer 134 on the substrate 100 of the cell region A and contacting the storage pad 132 is formed. The cell capacitor 140 may include a storage node 141, a capacitor dielectric layer 142, and a plate electrode 143. The storage node 141, the capacitor dielectric layer 142, and the plate electrode 143 may be sequentially stacked. The storage node 141 is connected to the storage pad 132 and may be formed of a conductive film such as polysilicon. The capacitor dielectric layer 142 may be formed of a silicon oxide layer or high-k dielectrics. The plate electrode 143 may be formed to cover the substrate 100 in the cell region C. The plate electrode 143 may be formed of one selected from the group consisting of a polysilicon film, a tungsten (W) film, an aluminum (Al) film, and a copper (Cu) film.

Referring to FIG. 7, an upper interlayer insulating layer 144 is formed on the substrate 100 having the cell capacitor 140. The upper interlayer insulating layer 140 may be formed of a high density plasma oxide (HDP oxide) film, a BPS film, a PE-TEOS film, a silicon oxynitride film, or a combination thereof. Subsequently, the upper surface of the upper interlayer insulating layer 144 may be planarized using a chemical mechanical polishing process or an etch back process.

Subsequently, a first contact hole 145 and a second contact hole 146 are formed in the core / peripheral region B in the cell region A by a patterning process. In the patterning process, a mask pattern (not shown), such as a photoresist pattern, is formed on the upper interlayer insulating layer 144, and the interlayer insulating layers and the buffer layers 144, 125, And anisotropic etching of the hard mask layer patterns 122 and 134. The anisotropic etching may be performed using a fluorine-based etching gas, for example, C ₄ F ₆ . Accordingly, the first contact hole 145 may be formed to penetrate the upper interlayer insulating layer 144 and expose the plate electrode 143 in the cell region A. Referring to FIG. The bit lines may be formed in the core / peripheral region B through the upper interlayer insulating layer 144, the buffer layer 134, the second interlayer insulating layer 128, and the hard mask layer pattern 122. The second contact holes 146 through which the 121 is exposed may be formed. In this case, when the etching selectivity of the buffer spacer 127 to the second interlayer insulating layer 128 is different as described above, for example, much lower, the second interlayer insulating layer 128 may be etched in the etching process of the second interlayer insulating layer 128. Etching is not performed in the buffer spacer 127. Although not shown, the second contact holes 146 are no longer formed due to the buffer spacer 127 even when the second contact holes 146 are formed to be biased toward one of the upper surfaces of the bit lines 121. Etching proceeds only at 122. Therefore, in forming the second contact holes 146, an alignment margin is secured.

Referring to FIG. 8, a first contact plug 150a may be formed in the first contact hole 145. At the same time, a second contact plug 150b may also be formed in the second contact holes 146.

In detail, the barrier metal layer 151 may be formed on inner walls of the first contact hole 145 and the second contact holes 146. A metal film 152 may be formed to completely fill the first contact hole 145 and the second contact holes 146. The barrier metal layer 151 and the metal layer 152 may also be stacked on the upper interlayer insulating layer 144. Subsequently, the metal layer 152 and the barrier metal layer 151 may be planarized to form the first contact plug 150a and the second contact plug 150b. For the planarization of the metal layer 152 and the barrier metal layer 151, a chemical mechanical polishing process or an etch back process using the upper interlayer insulating layer 144 as a stop layer may be applied. The barrier metal layer 151 may be formed of a titanium nitride layer TiN. The metal film 122 may be formed of a tungsten (W) film. The barrier metal layer 121 may be omitted. Afterwards, wires (not shown) connected to the first contact plug 150a and the second contact plug 150b may be formed on the upper interlayer insulating layer 144.

According to the DRAM manufacturing method of the present invention described above, the second contact plug 150b is in contact only with the bit lines 121, even if the second contact holes 146 are formed to be biased toward either side. The lower interlayer insulating layer 115 extends to prevent contact with the gate patterns 110. Therefore, contact failure can be prevented.

In an embodiment of the present invention, a DRAM semiconductor device is described as an example. However, the method for forming a contact hole according to an embodiment of the present invention is not limited thereto and may be applied to various semiconductor devices.

According to the present invention made as described above, the buffer spacer is formed on both sidewalls of the bit line pattern. As a result, in forming the contact hole, a process margin can be secured, thereby preventing contact failure. In addition, the contact plug is in contact with the bit line even when the contact hole is formed to be biased to one side, and does not extend downward.

Claims (12)

A conductive film pattern is formed on the substrate, Forming a first interlayer insulating film covering the conductive film pattern, Selectively removing the first interlayer insulating film so that the conductive film pattern is exposed, Forming a buffer spacer covering both sidewalls of the conductive layer pattern, Forming a second interlayer insulating film covering the conductive film pattern having the buffer spacer, Etching the second interlayer insulating layer to form a contact hole exposing the conductive layer pattern; And the buffer spacer is formed of an insulating film having an etch selectivity with respect to the second interlayer insulating film. The method of claim 1, And the buffer spacer is formed of a polysilicon film or a silicon nitride film. The method of claim 1, Forming the buffer spacer to conformally deposit a buffer spacer film on the entire surface of the substrate having the conductive film pattern, And anisotropically etching the buffer spacer layer. The method of claim 3, wherein And the buffer spacer layer is formed to have a thickness of 0.2 to 0.45 times a gap between adjacent conductive patterns. The method of claim 1, And forming an etch stop layer covering the entire surface of the substrate under the conductive film pattern before forming the conductive film pattern. The method of claim 5, The etching stop layer is a contact hole forming method, characterized in that formed of silicon nitride film or aluminum oxide film. Forming a bit line on a substrate having a cell region and a core / peripheral region, Forming a first interlayer insulating film on the substrate having the bit lines, Selectively removing the first interlayer insulating film of the core / peripheral region to expose a bit line of the core / peripheral region, Forming a buffer spacer covering both sidewalls of the bit line of the core / peripheral region, Forming a second interlayer insulating film covering said bit line with said buffer spacer, Forming a cell capacitor electrically connected to the substrate on the first interlayer insulating layer in the cell region, Forming an upper interlayer insulating film on the entire surface of the substrate having the cell capacitor, Etching the upper interlayer insulating layer and the second interlayer insulating layer to form a contact hole exposing the bit line of the core / peripheral region; And the buffer spacer is formed of an insulating film having an etch selectivity with respect to the second interlayer insulating film. The method of claim 7, wherein And the buffer spacer is formed of a polysilicon film or a silicon nitride film. The method of claim 7, wherein Forming the buffer spacers conformally deposits a buffer spacer film over the entire surface of the substrate having the bit lines, And anisotropically etching the buffer spacer layer. The method of claim 9, And the buffer spacer layer is formed to have a thickness of 0.2 to 0.45 times the gap between adjacent bit lines. The method of claim 7, wherein And forming an etch stop layer covering the entire surface of the substrate under the bit line before forming the bit line. The method of claim 11, The etching stop layer is a DRAM manufacturing method, characterized in that formed of silicon nitride film or aluminum oxide film.

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