KR20080008849A - Method and apparatus for receiving a broadcasting data in a dvb-h system - Google Patents

Abstract

An apparatus and a method for receiving broadcasting data in a DVB-H system are provided to receive and decode a continuous burst in the receiver of the DVB-H system, thereby preventing time delay in switching a channel and providing a PIP(Picture In Picture) function. A method for receiving broadcasting data in a DVB-H(Digital Video Broadcasting-Handheld) system comprises the following steps of: allocating a predetermined domain of a frame buffer and an erasure buffer to a burst received from a wireless network and buffering the burst(2102,2104); performing Reed-Solomon decoding for the burst when the buffering of the burst is completed in the frame buffer(2106); releasing the domain of the erasure buffer allocated to the burst after performing the Reed-Solomon decoding(2108); outputting the burst through an interface after releasing the allocation of the erasure buffer to the burst(2110); and releasing the domain of the frame buffer allocated to the burst after completing the output of the burst through the interface(2112).

Description

Apparatus and method for receiving broadcast data in digital video broadcasting system {METHOD AND APPARATUS FOR RECEIVING A BROADCASTING DATA IN A DVB-H SYSTEM}

1 is a diagram illustrating a data structure of a TS packet in a general DVB-H system.

2 is a block diagram showing an internal configuration of a transmitter in a typical DVB-H system;

3 is a block diagram showing an internal configuration of a receiver in a DVB-H system to which the present invention is applied;

4 is a flowchart conceptually illustrating a decoding method of an MPE-FEC frame according to FIG. 3;

5 is a block diagram showing an internal configuration of the MPE-FEC frame decoding apparatus of FIG. 3 according to the first embodiment of the present invention;

6 is a flowchart illustrating a method of decoding an MPE-FEC frame in a DVB-H receiver according to a first embodiment of the present invention;

7 is a configuration diagram of an MPE-FEC decoder according to a second embodiment of the present invention;

8 is an operation flowchart of an MPE PID and an MPE section detector of an MPE-FEC decoder according to a second embodiment of the present invention;

9 is a flowchart illustrating operations of a frame / eraser buffer and an RS decoder controller in an MPE-FEC decoder according to a second embodiment of the present invention;

FIG. 10 is a diagram illustrating the structure of a horizontal row searcher provided in a frame / erase buffer and an RS decoder controller according to a second embodiment of the present invention; FIG.

11 is a view illustrating an intermediate buffer according to a second embodiment of the present invention;

12A is a timing diagram when a burst is received in an MPE-FEC decoder according to a second embodiment of the present invention;

12B is a timing diagram when receiving consecutive bursts in the MPE-FEC decoder according to the second embodiment of the present invention;

13 is a configuration diagram of an MPE-FEC decoder according to a third embodiment of the present invention;

14 is a detailed block diagram of a main control unit according to a third embodiment of the present invention;

15 is a diagram illustrating a segmentation structure of a frame / erase buffer according to a third embodiment of the present invention;

16 is a diagram illustrating a structure in which a segment allocator divides a frame buffer and an erasure buffer into segments having a predetermined size according to a third embodiment of the present invention;

17 is a flowchart illustrating operations of a buffering controller according to a third embodiment of the present invention;

18 is a flowchart illustrating an operation of an R-S decoder controller according to a third embodiment of the present invention;

19 is a flowchart illustrating operations of a serial output controller according to a third embodiment of the present invention;

20 is a timing diagram of an MPE-FEC decoder according to a third embodiment of the present invention;

21 is a flowchart of operation of the main control unit according to the third embodiment of the present invention;

The present invention relates to a method and apparatus for receiving data in a Digital Video Broadcasting-Handheld (DVB-H) system, and particularly to a multiprotocol encapsulation-forward error in a DVB-H system. Correction: MPE-FEC) Decoding method and apparatus for decoding a frame.

Recently, with the development of data compression technologies such as audio and video and communication technologies, digital broadcasting, which can provide high quality voice and video services anywhere through a fixed or mobile terminal, has been realized. In general, digital broadcasting refers to a broadcasting service that provides a high quality service and a high quality service of CD level to a user in place of a conventional analog broadcasting. Digital broadcasting has been developed in two forms, terrestrial broadcasting and satellite broadcasting. Here, terrestrial broadcasting refers to a service capable of receiving a broadcast through a terrestrial repeater. Satellite broadcasting, on the other hand, refers to a method of receiving digital broadcasting using an artificial satellite as a repeater.

Examples of such digital broadcasting systems include digital audio broadcasting (DAB), digital radio broadcasting (DRS), digital audio radio system, and audio, video, and data services. So-called digital multimedia broadcasting (DMB) systems. In addition, the DVB-H system, which enhances the mobility and portability of the European digital audio broadcasting system Eureka 147 (European Research Coordination Agency project-147) system and the DVB-T (Terrestrial) system, which is one of the digital broadcasting standards, has recently received attention. have.

The physical layer standard of the DVB-H system follows most of the specifications of the existing DVB-T system and is characterized by supporting an additional error correction coding technique such as MPE-FEC to ensure stable reception on the move. In the DVB-H system, broadcast data is generated as an IP datagram, and an MPE-FEC frame is generated by RS (Reed-Solomon) encoding of the IP datagram. Accordingly, the MPE-FEC frame includes an MPE section carrying an IP datagram and an MPE-FEC section carrying parity data according to RS encoding. The MPE section and the MPE-FEC section are carried in a payload of a transport stream (TS) packet, which is a transport unit of a DVB-H system, and transmitted through a physical layer.

In FIG. 1, reference numeral 100 shows an IP datagram on which broadcast data is carried. The datagram refers to a packet including an address of a network end to which data is transmitted. Reference numeral 102 shows an MPE section carrying the IP datagram 100 or an MPE-FEC section carrying parity data of the IP datagrams 100. Reference numeral 104 shows a TS packet carrying an MPE section or an MPE-FEC section 102. Here, one TS packet 104 may include multiple MPE sections or MPE-FEC sections 102, or one MPE section or MPE-FEC sections 102 may be transmitted through multiple TS packets 104. .

As a result of the MPE-FEC process, IP datagrams are RS encoded to form an MPE-FEC frame. Data constituting the MPE-FEC frame is reconstructed in a transmission unit called a section, and the IP datagram 100 is reconstructed into an MPE section by adding 32 bits of a section header and a cyclic redundancy check (CRC) to perform RS encoding. Parity data generated through the addition of the section header and CRC 32 bit is added to reconstruct the MPE-FEC section. The section header contains information required for MPE-FEC processing and time slicing, and is located at the beginning of the section. CRC 32 bits are located later in the section. These sections are finally carried in the payload portion of the TS packet 104 and transmitted over the physical layer.

Hereinafter, a transmission process of an MPE-FEC frame will be described with reference to FIG. 2.

FIG. 2 is a block diagram illustrating an internal configuration of a transmitter in a general DVB-H system. The characteristic of the DVB-H system shown in FIG. 1 is to transmit IP data as broadcast data to a plurality of users, RS parity data is also sent for error correction.

In FIG. 2, the MPE-FEC encoder 201 generates an MPE section including an IP datagram to transmit an IP datagram transmitted as broadcast data in section units, and forward error correction (FEC) of the MPE section. Create an MPE-FEC section containing parity data for correction. The parity data is generated through RS encoding, which is a well-known external encoding technique. The output of the MPE-FEC encoder 201 is delivered to a time slicing processor 203 to perform time division processing for transmitting broadcast data in bursts. One MPE-FEC frame is transmitted through one burst period. On the other hand, IP datagrams that have undergone time slicing are processed through HP (High Priority) streams, and then serialized / parallel according to the modulation order and the hierarchical or non-hierarchical transmission mode. The signal may be converted into a signal.

In FIG. 2, the bit interleaver 205 and the symbol interleaver 207 perform interleaving in units of bits and interleaving in units of symbols for distributing transmission errors, respectively. The interleaved signal is symbol-mapped through a symbol mapper 209 according to a predetermined modulation scheme such as QPSK, 16 QAM, or 64 QAM, and transferred to the inverse fast fourier transform (IFFT) 211. The IFFT 211 converts a signal in a frequency domain into a signal in a time domain, and outputs the IFFT processed signal into a baseband OFDM symbol signal by inserting a guard interval through a guard interval inserter (not shown). Is generated. The OFDM symbol is pulse-formed by the digital baseband filter, modulated by the RF modulator 213, and finally transmitted through the antenna 215 as a TS packet, which is a DVB-H signal.

Meanwhile, the receiver of the DVB-H system should restore the IP datagram including the broadcast data by receiving the TS packet through the physical layer. Therefore, a MPE-FEC decoding technique of a DVB-H receiver which extracts an MPE section and an MPE-FEC section from a TS packet and configures the extracted data into MPE-FEC frames to restore an IP datagram is required. However, at present, a specific standard for the transmission technology of the DVB-H system has been prepared, but no specific method has been prepared for the reception technology such as the MPE-FEC decoding technology.

The present invention provides a method and apparatus for decoding an MPE-FEC frame that receives a TS packet in a DVB-H system and restores an IP datagram as broadcast data.

 The present invention provides a method and apparatus for reducing the R-S decoding time for a frame buffer in a receiver of a DVB-H system.

A method for decoding a multi-protocol encapsulated forward error correction (MPE-FEC) frame in a receiver of a digital broadcasting system according to the present invention comprises assigning a predetermined area to a frame buffer and an erasure buffer for a burst received from a wireless network. Buffering, performing a read-solomon decoding on the burst when buffering of the burst is completed in the frame buffer, and an area of the erasure buffer allocated for the burst after performing the read-solomon decoding. Releasing a buffer, a buffer buffered in the frame buffer after the allocation of the erasure buffer region to the burst is released through an interface, and outputting the burst to the burst after the output of the burst is completed through the interface. Freeing the area of the frame buffer allocated for The.

An apparatus for decoding a multi-protocol encapsulated forward error correction (MPE-FEC) frame in a receiver of a digital broadcasting system according to the present invention includes a frame buffer for buffering section data of a burst received from a wireless network, and the received burst. An erasure buffer for buffering reliability information of the buffer, a reed-solomon decoder for performing Reed-Solomon decoding on the burst when the burst is completed in the frame buffer, and a predetermined area is allocated to the frame buffer. Control to buffer the received burst, allocate a predetermined area to the eraser buffer to buffer the reliability information of the burst, and after the Reed-Solomon decoding is completed, the buffer of the eraser allocated for the burst Releases the region and returns the eraser buffer for A main control unit for outputting a burst buffered in the frame buffer through an interface after the reverse allocation is released, and releasing the area of the frame buffer allocated for the burst after the output of the burst through the interface is completed; Include.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the same components in the figures represent the same numerals wherever possible. Specific details are set forth below, which are provided to aid a more general understanding of the present invention. In describing the present invention, when it is determined that description of related known functions or configurations may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

3 is a block diagram showing an internal configuration of a receiver in a DVB-H system to which the present invention is applied.

In FIG. 3, the TS packets received from the wireless network are received by the RF demodulator 303 through the antenna 301, and the OFDM symbols of the TS packets which are frequency down-converted and converted into digital signals through the RF demodulator 303 are FFT ( Fast Fourier Transform (305) is converted into a signal in the frequency domain. The symbol demapper 307 symbol demaps the received signal according to a predetermined modulation scheme such as QPSK, 16 QAM, or 64 QAM, and the symbol deinterleaver 309 and the bit deinterleaver 311 are deinterleaved in symbol units. Each bit is deinterleaved to restore the original signal.

In FIG. 3, if the packet identifier (PID) is detected from the header information of the TS packet by performing the packet identifier filtering, the MPE-FEC decoder 315 performs an MPE section or an MPE-FEC section. Is regarded as received, and if no PID is detected, time slicing and MPE are performed using program specific information and service information (PSI / SI) (hereinafter referred to as "broadcast service information") from the TS packet. -Receive service information related to broadcast reception such as whether FEC is applied or not. Meanwhile, the MPE-FEC decoder 315 receiving the broadcast service information (PSI / SI) distinguishes the IP datagram of the MPE section constituting the MPE-FEC frame from the received TS packet and the parity data of the MPE-FEC section. The data is stored in the data area and the parity area of the internal buffer, and RS decoding is performed to restore the original broadcast data. In addition, the delta-t information 700 included in each MPE section and the MPE-FEC section is extracted and transmitted to the time slicing processor 313.

The time slicing processor 313 repeats the switching of the entire receiver blocks 300 to receive the TS packet including the MPE-FEC frame for each predetermined burst period. Here, the burst section may be included in the header of each MPE section and the MPE-FEC section to receive delta t information indicating the start time of the next burst section.

4 is a flowchart conceptually illustrating a decoding method of an MPE-FEC frame according to FIG. 3, and each process of FIG. 4 is performed by the MPE-FEC decoder 315 of FIG. 3.

In step 401 of FIG. 4, the MPE-FEC decoder 315 performs PID filtering on a TS packet transmitted from a physical layer demodulator to detect a TS packet including an MPE section or an MPE-FEC section and broadcast other packets. It is regarded as a packet including service information (PSI / SI) and checks whether time slicing and MPE-FEC are applied. Since the present invention proposes a decoding method of the MPE-FEC frame, the MPE-FEC is considered to be applied in the following description. When the MPE-FEC decoder 315 receives the TS packet including the MPE-PID in the header information in step 401 using the broadcast service information (PSI / SI), the MPE section or MPE Consider it a FEC section.

In step 403, the MPE-FEC decoder 315 checks a table ID (table_id) from the header information of the section data extracted from the TS packet, so that the parity data of the IP datagram indicates whether the section data is an MPE section including the IP datagram. Determine if it is an included MPE-FEC section. If the data received in step 403 is identified as an MPE section, the MPE-FEC decoder 315 proceeds to step 405 and frame buffers the IP datagram of the MPE section in the data area of the internal buffer. On the other hand, if the received data is not the MPE section in step 403, the MPE-FEC decoder 315 checks whether the MPE-FEC section is received in step 407. If the received data is found to be the MPE-FEC section as a result of the check in step 407, the MPE-FEC decoder 315 proceeds to step 409 to frame buffer parity data of the corresponding MPE-FEC section in the parity region of the internal buffer. do.

Thereafter, in step 411, the MPE-FEC decoder 315 checks a real time parameter from the header information of the MPE-FEC section, so that the currently received MPE-FEC section forms the last MPE-FEC frame. Make sure it is an FEC section. If the check result of step 411 is not the last MPE-FEC section, the MPE-FEC decoder 315 proceeds to step 403 and continuously receives and buffers an MPE section or an MPE-FEC section constituting a frame. Repeatedly, if it is confirmed as the last MPE-FEC section, RS decoding is performed to correct an error of the IP datagram using parity data stored in an internal buffer.

In step 415, the MPE-FEC decoder 315 outputs an IP datagram in which an error is corrected to a higher layer, and the IP datagram is displayed as broadcast data through a user terminal.

FIG. 5 is a block diagram showing the internal configuration of the MPE-FEC frame decoding apparatus of FIG. 3 according to the first embodiment of the present invention, which shows the configuration of the MPE-FEC decoder 315 of FIG.

The apparatus of FIG. 5 includes a buffer 510 for temporarily storing the IP datagram of the MPE section and the parity data of the MPE-FEC section extracted from the received TS packet, and correcting an error of the IP datagram using the parity data. It analyzes the RS decoder 530 and the broadcast service information (PSI / SI) transmitted from the transmitter through the physical layer to check whether the MPE-FEC is applied, as well as the MPE section and the MPE-FEC section. Extracts the IP datagram and the parity data from each other and stores the IP datagram and parity data in the buffer 510, and counts the maximum burst section to be described later by the burst section timer 570 based on delta t information indicating a time point at which the next burst section starts. A controller 550 for controlling a time point for performing RS decoding and controlling overall operation of RS decoding the IP datagram through the RS decoder 530; It is composed.

In FIG. 5, the buffer 510 distinguishes between a circular buffer 511 for performing CRC on an MPE section and an MPE-FEC section, and an IP datagram of an MPE section and parity data of an MPE-FEC section. And a frame buffer 513 for storing and performing RS decoding, and an erasure buffer 515 for marking reliability information according to the CRC result.

When the controller 550 receives the TS packet, the controller 550 first analyzes broadcast service information (PSI / SI) information to determine whether the MPE-FEC is applied and then removes the header information from the received TS packet. A FEC section is stored in the circular buffer 511 to perform CRC.

If the CRC result is 'GOOD', the controller 550 checks header information of the corresponding section data, and the payload (IP datagram) of the MPE section is stored in the broadcast data table area of the frame buffer 513, and the MPE- The payload (parity data) of the FEC section is stored in the RS data table area of the frame buffer 513. In addition, the controller 550 marks whether the IP datagram and the parity data are normally received according to the CRC result as reliability information in the erasure buffer 515, and the reception error is generated through the RS decoder 530. The RS is decoded using the parity data, and the error is corrected and output to the upper layer.

The controller 550 omits the RS decoding operation when reliability information is marked on all regions of the erasure buffer 515 (that is, when all IP datagrams of the MPE-FEC frame are normally received).

In addition, the controller of the time slicing processor 313 (not shown) controls the burst interval timer 570 to count the burst interval timer based on the detected burst boundary, and when the burst interval timer 570 counts the burst interval. The controller 550 performs the RS decoding. At this time, the controller of the time slicing processor 313 transmits to the burst interval timer 570 the start time of the next burst interval based on the delta t information of the real time parameter described above, and the burst interval timer 570 may transmit the delta. Based on the t information, it is possible to know when to count a predetermined time.

In addition, the controller 550 periodically measures whether the burst duration timer 570 counts the maximum burst duration included in the maximum burst duration information max_burst_duration included in the broadcast service information, thereby determining whether the burst duration has ended. It can be seen.

Accordingly, the controller 550 transmits the received IP datagram to the upper layer at the time of controlling the RS decoder for RS decoding based on the value.

Here, the maximum burst duration information means the maximum size of the burst duration transmitted when the MPE-FEC frame is transmitted by the time slicing scheme in the DVB-H system, and the burst duration timer 570 is the time slicing processor in the previous burst duration. The maximum burst period max_burst_duration is counted from the burst period start time indicated by the delta t information received from the controller 313.

The burst duration timer 570 is provided in the time slicing processor 313 and is a timer that operates only during the burst period in which the transmitting end of the DVB-H system transmits the MPE-FEC frame. That is, as described above, the burst period timer 570 starts to receive the MPE-FEC frame transmitted from the transmitting end under the control of the controller of the time slicing processor 313 and simultaneously counts the burst period. The controller 550 of the MPE-FEC decoder 315 may be notified of the end time of the burst period, and the controller 550 examines the time point at which the count of the burst period timer 570 is terminated. Know when to end.

When the burst duration timer 570 counts a predetermined time, the controller 550 may know when to decode the RS or when to transmit the received IP datagram to the higher layer based on the burst duration timer 570.

If the last section is properly received and the frame boundary value field is set to '1', the controller 550 causes the RS decoder 530 to perform RS decoding at the same time that frame buffering is terminated in the frame buffer 513. If not, the RS decoder 530 starts the RS decoding by considering that the reception of the MPE-FEC frame is completed at the moment when the burst duration timer 570 counts the time of the burst duration and outputs "0". Control or transmit the received MPE section to a higher layer.

6A to 6B are flowcharts showing in detail a method of decoding an MPE-FEC frame in a DVB-H receiver according to a first embodiment of the present invention.

First, in step 600, the controller 550 of FIG. 5 receives a TS packet from a physical layer, and performs PID filtering on the received TS packet in step 602. If the PID filtering result indicates that the MPE PID of the TS packet including the MPE section or the MPE-FEC section is not detected, the controller 550 transmits broadcast service information (PSI / SI) to the corresponding TS packet in step 604. The packet is regarded as a packet, and the broadcast service information (PSI / SI) is analyzed to determine whether time slicing and MPE-FEC are applied. In step 600, the controller 550 receives the next TS packet. When the MPE-PID is detected from the received TS packet, the controller 550 regards the TS packet as a TS packet including an MPE section or an MPE-FEC section. Proceed to step 606.

In step 606, the controller 550 removes the 4-byte header portion from the TS packet and determines the 184-byte payload portion when it is determined that MPE-FEC is applied using the analysis result of the broadcast service information (PSI / SI) in step 604. Are stored sequentially in byte units in the circular buffer 511 of FIG. The purpose of the circular buffering is to perform CRC on the currently received MPE section or MPE-FEC section and receive until the payload of the section consisting of IP datagram or parity data is delivered to the frame buffer 513. Is to store the data. When the last address of the circular buffer 511 is filled with data, the next storage location is address 0.

In addition, in step 606, the controller 550 checks the start and end of the MPE section or the MPE-FEC section transmitted in the payload of the TS packet, and performs RS decoding on the MPE-FEC frames configured by the sections. In order to obtain reliability information, a CRC check is performed each time a table ID (table_id) to be described later is detected. This process will be referred to as section detection. The MPE section or the entire MPE-FEC section is transmitted, for example, with 32 bits of CRC data appended to the end of each section. In the present invention, when the CRC 'GOOD' occurs, the controller 550 considers that at least one MPE section or MPE-FEC section exists in the test section that generated the CRC 'GOOD' and the MPE-FEC frame from the header information of the section. Extract information needed for decoding.

Table 1 below shows information required in a decoding process of an MPE-FEC frame among header information extracted from an MPE section or an MPE-FEC section.

Header information Contents table_id  Indicates the type of MPE section or MPE-FEC section section_length  Indicates the section length in bytes from the fourth byte of the section to the end of the section containing CRC 32 bits. padding_columns  Indicates the number of zero-padded columns in the broadcast data table area of the MPE-FEC frame (has a value between 0 and 190) table_boundary  Indicates that the current section is the last section in the broadcast data table area or R-S data table area of the MPE-FEC frame (when set to '1'). address  Indicates the byte position occupied by the first byte of the payload of the currently received section in each region of the MPE-FEC frame.

The controller 550 includes at least one CRC checker (not shown) to perform such a CRC check. The controller 550 may assign a new CRC checker every time a table ID (table_id) is detected until the CRC check is 'GOOD', thereby performing multiple CRC checks. After extracting the header information of the section data detected in step 606, the controller 550 extracts a CRC test section of the CRC checker that generates the CRC 'GOOD' and a section length (section_length) of the header information of the <Table 1>. In comparison, when the section length and the CRC test interval coincide with each other, the terminal finally confirms that the received section is normal. This operation is to perform section detection more accurately and may be selectively performed.

When section detection is completed according to step 606, the controller 550 reads the table ID table_id of Table 1 from the header information of the section detected in step 608, so that the detected section is an MPE section or an MPE-FEC. Check which section it is. If the MPE section is determined in step 608, the controller 550 removes the header information and the CRC bits from the MPE section in step 612, and then the IP datagram of the corresponding MPE section in the broadcast data table area of the frame buffer 513. Buffer the frame. Since the IP datagram frame-buffered in step 610 is reliable data that has undergone CRC checking, the controller 550 marks reliability information on bytes of the corresponding IP datagram in the erasure buffer 515 in step 614. Marking).

On the other hand, in step 608 the controller 550 inquires the table ID (table_id) of the <Table 1> from the header information of the section and if the section detected in step 606 corresponds to the MPE-FEC section proceeds to step 610 MPE The padding column number information (padding_columns) is queried from the header information of the -FEC section to identify a portion in which the '0' is filled in the broadcast data table region instead of the data. That is, the broadcast data table area of the two areas of the MPE-FEC frame may be transmitted without being filled with all IP datagrams at the transmitting side. In this case, the unfilled broadcast data table area is RS coded instead of filled with '0' bytes (hereinafter referred to as "zero padding"), and no actual transmission is performed.

Therefore, in order to correctly perform decoding of the MPE-FEC frame at the receiver, zero padding of a non-transmitted padding column portion must be performed before RS decoding. The number of zero padded portions is indicated in units of columns, and the controller 550 inquires the padding column number information padding_columns and performs zero padding. This information can be known during the header information extraction process, and zero padding must be performed for the corresponding number of columns before RS decoding is performed. This process is called padding column processing 610.

In the padding column process 610, the controller 550 is divided into two cases. The first is a case where the IP datagram of the last MPE section transmitted by the sender is properly received, and the second is a case where the IP datagram of the last MPE section is not properly received.

In the first case, the controller 550 zero-pads the remaining area of the broadcast data table area after the last MPE section and marks reliability information at the position of the corresponding erasure buffer 515. On the other hand, in the second case, since the last MPE section is not properly received, it is not possible to know exactly which byte to start with zero padding. Thus, the controller 50 has no padding column information (padding_columns) except for an untrusted part. Only the bytes corresponding to the indicated padding column number are zero padded, and the zero padded portion is marked with reliability information.

Meanwhile, after marking reliability information on the erasure buffer 515 in step 614, the controller 550 checks whether the received MPE-FEC section is the last section in step 616. At this time, the controller 550 queries the table boundary information (table_boundary) to determine whether the corresponding MPE-FEC section is the last MPE-FEC section that fills the R-S data table. If the MPE-FEC section is the last section, in step 618, the reliability information of the erasure buffer 515 is inquired to check whether the reliability information is marked for all IP datagrams in the received application data table. do.

If the reliability information is marked for all IP datagrams as a result of the check in step 618, all IP datagrams in the broadcast data table area are normally received. In this case, the controller 550 proceeds to step 624 to correct errors. RS decoding is omitted, and IP datagrams of the frame buffer 513 are output to the upper layer as they are. On the other hand, if the reliability information is not marked even in at least one IP datagram in the broadcast data table region as a result of step 618, the process proceeds to step 620 to determine whether the burst duration timer 570 counts a predetermined time "0". Check it. The burst start / end signal may be generated by the time slicing processor 313 or the burst period timer 570, and the frame / erase buffer controller 550b is input to perform the above-described operation.

If the controller 550 checks that the burst duration timer 570 has counted a predetermined time in step 620, the controller 550 RS decodes the MPE section received through the RS decoder 530 in step 622. In operation 624, the IP datagram is transmitted to the upper layer.

On the other hand, if the burst interval timer 570 does not count the predetermined time as a result of the check in step 620, the controller 550 proceeds to step 626 to check whether the end of the MPE section is consistent with the end of the TS packet. If the end of the MPE section coincides with the end of the TS packet as a result of step 626, the controller 550 proceeds to step 600 to receive the next TS packet, and if it does not match, proceeds to step 606 to receive the current. The next MPE section or MPE-FEC section from the detected TS packet.

The receiver of the DVB-H system as described above must detect a section in the TS packet in order to recover the pure IP datagram from the TS packet received through the physical layer. The payloads of each section must be reconstructed into MPE-FEC frames and can be restored to an IP datagram when the R-S decoding process is performed. In the receiver of the DVB-H system according to the first embodiment of the present invention described with reference to FIGS. 3 to 6, the MPE or MPE-FEC section is detected from the TS packet, and the receiver reconstructs the entire MPE-FEC frame with the detected section. A series of procedures were described. However, in order to implement the DVB-H receiver according to the first embodiment described with reference to FIGS. 3 to 6, some important points are omitted.

First, reliability information is updated to good only at sections and padding column positions detected through CRC checking according to the first embodiment, and all remaining positions are considered bad and erased when performing RS decoding. ) If the eraser is not normally input, the RS decoder 530 cannot perform decoding normally. Thus, the erasure buffers 515 must all be initialized with unreliable information. 3 to 6 described above, the initialization operation of the erasure buffer 515 is not described in the first embodiment.

In addition, in FIG. 6, when the controller 550 receives the MPE-FEC section, the controller 550 performs padding column processing before performing frame buffering and reliability information marking on the section each time. Padding column processing is to frame-buffer " 0 " values and mark reliability information for padding columns as mentioned above. This operation can take considerable time depending on the number of padding columns. Since the TS packet is continuously input to the MPE-FEC decoder 315 even after detecting the current MPE-FEC section, the DVB-H receiver according to the first embodiment of the present invention according to FIGS. It will cause problems to deal with.

In addition, RS decoding is performed in row units. However, in the DVB-H receiver according to the first embodiment of the present invention as shown in FIGS. 3 to 6 described above, there is no description on how to control the R-S decoder 530 and process the result.

Finally, the IP datagram should be output after RS decoding is performed on the entire frame buffer 513. However, the description of how the DVB-H receiver outputs the IP datagram according to the first embodiment. There was no.

Accordingly, a second embodiment of the present invention will be described with respect to the block configuration and method flow diagram of the MPE-FEC decoder in the DVB-H receiver to compensate for the problems in the first embodiment as described above.

7 is a configuration diagram of an MPE-FEC decoder 315 according to a second embodiment of the present invention. The MPE-FEC decoder 315 according to the second embodiment of the present invention is connected to a DVB-H physical layer receiver 700 and a local syncronous serial port 702.

The controller 550 of the MPE-FEC decoder 315 according to the second embodiment of the present invention includes an MPE PID and an MPE section detector 550a, a frame / eraser buffer, and an RS decoder controller 550b. It consists of.

The MPE PID and MPE section detector 550a controls the circular buffer 511, and the frame / eraser buffer and RS decoder controller 550b is the frame buffer 513 and eraser buffer 515, and the RS decoder 530. ).

Basically, according to the second embodiment of the present invention, the operation performed by the MPE-FEC decoder 315 is similar to that of the first embodiment. However, in the second embodiment, the Local SSP block 702, the serial interface 704, and the bus interface controller 710 are added to output the IP packet more than the first embodiment.

The local synchronous serial port 702 added according to the second embodiment outputs the IP datagram in serial form directly to an application processor (not shown), and the bus interface controller 710 outputs the IP datagram in Advanced Peripheral (APB). Bus 706, such as Bus) or Advanced High-performance Bus (AHB), to the processor 708 in the DVB-H receiver.

When outputting an IP datagram to a processor 708 in a DVB-H receiver according to a second embodiment of the present invention, the frame / eraser buffer and RS decoder controller 550b may cause the processor 708 to perform an MPE for one burst. Generate an interrupt signal to the processor 708 so that the end point of FEC frame decoding is known.

In the second embodiment, the unreliable marking operation of the erasure buffer 513 is performed through buffer initialization. That is, when a section detected from the MPE PID and the MPE section detector 55a is input, the frame / eraser buffer and the RS decoder controller 550b are marked with reliable information at a corresponding position of the erasure buffer 513. Previously, make sure that the address is initialized as unreliable.

The initialization operation is performed at an idle time between the frame / erase buffer and the time when the RS decoder controller 550b enters the section. At this time, the section header and the CRC are excluded from the TS packet received when the section is detected.

Therefore, even if all data in the burst does not have a reception error, the section data is not continuously output in the burst, so there is an idle time for the section input. The frame erasure buffer and the RS decoder controller 550b of the present invention perform an initialization operation at the idle time so that RS decoding can be normally performed.

The initialization operation start time of the erasure buffer 515 is a time point at which the first TS packet of the burst is input. Frame / erase buffer and RS decoder controller 550b initiates frame buffering and R-S decoding operations for one burst by a burst start signal.

Since some time delay is required for MPE PID and MPE section detection, the frame / erase buffer and RS during the delay from the burst start signal to the input of the first section into the frame / eraser buffer and RS decoder controller 550b. The decoder controller 550b can initialize the erasure buffer 515.

The frame / erase buffer and RS decoder controller 550b also checks whether to use the serial interface 704 to send the IP datagram stored in the frame buffer 513 to an application processor (not shown). To output the IP datagram to the application processor via the serial interface 704, the frame / eraser buffer and RS decoder controller 550b controls the switch 740 to read the IP datagram from the frame buffer 513. The local SSP 702 transmits the serial interface. In this case, the result of the MPE-FEC frame decoding may be processed by the CPU 708 or output to a processor external to the DVB-H receiver through the serial interface 704. Whether the MPE-FEC frame decoding result is sent to an external processor via the CPU 708 or the serial interface 704 depends on how the DVB-H receiver is configured, and therefore from a vendor, such as a manufacturer, to register in advance. Set to use. That is, the user (mobile terminal manufacturer) decides in advance.

On the other hand, to transmit the IP datagram stored in the frame buffer 513 via the bus 706 to the processor 708 of the DVB-H receiver, the frame / eraser buffer and the RS decoder controller 550b may switch the switch 740. The control connects the frame buffer 513 and the bus interface 710. The frame / erase buffer and RS decoder controller 550b then generates an interrupt signal to the processor 708 to control the processor 708 to read the IP datagram from the frame buffer 513 via the bus 706. do. The switch 740 may change from time to time as necessary during operation, and is not fixed for each mode. That is, data of the frame buffer may be simultaneously output to the serial interface 704 and the bus 710 using a time multiplexing method.

The MPE_FEC_done interrupt signal, output from the frame / erasure buffer and RS decoder controller 550b, informs the CPU 708 that the decoding of the MPE-FEC frame for a burst has ended and indicates when data can be read at the same time. To perform. In addition, a burst interval timer 570 is provided in the time slicing processor 313 and controls the operation of the MPE-FEC decoder 315 based on the burst boundary information received from the MPE PID and the MPE section detector 550a. do. That is, when the frame / eraser buffer and the RS decoder controller 550b receives the burst period end signal from the time slicing processor 313, the reliability information marking and padding column of the erasure buffer 515 according to an embodiment of the present invention. The RS decoder 530 is controlled to perform processing and to perform RS decoding.

8 is a flowchart illustrating operations of the MPE PID and the MPE section detector 550a of the MPE-FEC decoder 315 according to the second embodiment of the present invention.

First, when the burst start signal is output from the time slicing processor 313 that receives the burst section information from the MPE-PID and the MPE section detector 550a in step 800, the MPE PID and the MPE section detector 550a output the DVB in step 802. In step 804, the TS packet is received from the physical layer receiver 700, and PID filtering is performed on the received TS packet. If it is determined that the MPE PID of the TS packet including the MPE section or the MPE-FEC section is not detected as the PID filtering result, the MPE PID and the MPE section detector 550a transmits the corresponding TS packet to the broadcast service information (PSI / It is regarded as a packet carrying SI, and the broadcast service information (PSI / SI) is analyzed to determine whether time slicing and MPE-FEC are applied. The MPE PID and MPE section detector 550a proceeds to step 802 to receive the next TS packet, and when the MPE-PID is detected from the received TS packet, the MPE PID or MPE-FEC section is loaded. The packet is regarded as a TS packet, and the flow proceeds to step 808.

In step 808, the MPE PID and MPE section detector 550a removes the 4-byte header part from the TS packet when it is determined that MPE-FEC is applied using the analysis result of the broadcast service information (PSI / SI) in step 604. The 184 byte payload portion is sequentially stored in the circular buffer 511 of FIG. 5 in units of bytes.

In addition, in step 808, the MPE PID and MPE section detector 550a checks the start and end of the MPE section or the MPE-FEC section transmitted in the payload of the TS packet, and RS for the MPE-FEC frame configured by these sections. In order to obtain reliability information for decoding, a CRC check is performed each time a table ID (table_id) to be described later is detected. That is, a section detection process is performed.

In operation 810, the MPE PID and the MPE section detector 550a output MPE section information and data to the frame / eraser buffer and the R-S decoder controller 550b. In step 812, the MPE PID and MPE section detector 550a checks whether the burst duration timer 570 of the time slicing processor 313 has counted a predetermined time "0".

In operation 812, when the MPE PID and the MPE section detector 550a check that the burst duration timer 570 has counted a predetermined time, in step 814, the MPE PID and MPE section detector 550a counts the burst end signal in the frame / eraser buffer and the RS decoder controller ( 550b), if the predetermined time is not counted, the process proceeds to step 816 and checks whether the end of the MPE section matches the end of the TS packet. If the end of the MPE section coincides with the end of the TS packet as a result of step 816, the MPE PID and the MPE section detector 550a proceed to step 802 to receive the next TS packet, and if it does not match, step 808. Proceed to detect the next MPE section or MPE-FEC section from the currently received TS packet.

9 is a flowchart illustrating operations of a frame / erase buffer and an RS decoder controller 550b in the MPE-FEC decoder 315 according to the second embodiment of the present invention.

When the burst start signal is received from the time slicing processor 313 in step 900, the frame / eraser buffer and the RS decoder controller 550b proceed to step 902 to check whether the section has started to be input. If the check result section of step 902 has been started, the flow proceeds to step 906 to store the section parameters. The section parameters mean the contents shown in Table 1, and are stored in the frame / erase buffer and the RS decoder controller 550b.

In step 908, the frame / erase buffer and RS decoder controller 550b removes the header information and the CRC bits from the MPE section, and then frame buffers the IP datagram of the corresponding MPE section in the broadcast data table region of the frame buffer 513. . Since the frame buffered IP datagram is CRC-tested reliable data, the frame / erase buffer and RS decoder controller 550b marks reliability information on the bytes of the corresponding IP datagram in the erasure buffer 515. (Marking)

In step 910, the frame / erase buffer and the RS decoder controller 550b checks whether the last MPE section has been received, and if the last MPE section is received, proceeds to step 912 to store the last address.

On the other hand, if the check result section of step 902 does not start, the frame / eraser buffer and RS decoder controller 550b proceeds to step 904 to initialize reliability information in the eraser buffer 515.

Since section data is continuously input within the burst, the frame / eraser buffer and RS decoder controller 550b must buffer the section data and mark reliability information before all the section data for one burst is input. Generally, there is a time interval after the end of one section until the next section is input. The frame / eraser buffer and the RS decoder controller 550b according to the second embodiment of the present invention have an erasure buffer 515 at the time interval. Initialize That is, initializing the reliability information in step 904 does not initialize the entire eraser buffer 515, but initializes the eraser buffer 515 at every intermediate time point at which the sections are received.

If the MPE section received as a result of the check in step 910 is not the last MPE section, the frame / erase buffer and RS decoder controller 550b checks whether the last MPE-FEC section is received in step 914.

If the last MPE-FEC section is received as a result of the checking in step 914, the frame / erase buffer and RS decoder controller 550b proceeds to step 918 and fails to complete initialization of the erasure buffer 515 in step 904. Reliability information initialization is performed for the area.

On the other hand, if the last MPE-FEC section has not been received as a result of the check in step 914, the frame / eraser buffer and RS decoder controller 550b proceeds to step 916 to check whether the burst has ended. In step 916, the frame / eraser buffer and the RS decoder controller 550b may recognize that the burst is terminated when the last MPE-FEC section is input or the burst end signal generated by the time slicing processor 313 is input. .

If the burst is terminated in step 916, the frame / erase buffer and RS decoder controller 550b proceeds to step 918 and initializes reliability information for the remaining areas in which the initialization of the eraser buffer 515 is not completed in step 904. Do this.

As described above, if the initialization of the erasure buffer 515 is not finished after the section data for the burst period is input in operation 918, the frame / eraser buffer and the RS decoder controller 550b do not initialize in operation 904. Initialization is performed on the remaining remaining regions, and the padding column processing is performed in operation 920 as in operation 610 of FIG. 6.

In step 920, the frame / eraser buffer and the RS decoder controller 550b performs the padding column processing to perform the "0" data buffering (zero padding) and the reliability information marking operation on the padding column area only once, thereby preventing timing problems. Can be avoided.

Thereafter, in step 922, the frame / eraser buffer and RS decoder controller 550b searches for a horizontal row to decode. A detailed process of searching for a horizontal line to be decoded by the frame / erase buffer and the RS decoder controller 550b in step 922 will be described with reference to FIG. 10 to be described later.

In step 924, the frame / eraser buffer and RS decoder controller 550b checks whether the decoding of all horizontal rows of the data stored in the erasure buffer 515 is finished. In step 924, the decoding operation is not performed, and only the horizontal coding of all horizontal lines is checked with the search result of step 922.

In step 924, if the frame / eraser buffer and RS decoder controller 550b has not finished decoding for every horizontal row as a result of the checking, in step 926, the frame / eraser buffer and RS decoder controller 550b Control RS decoder 530 to perform RS decoding on one row of frame buffer 513. Unlike step 924, in step 926, the RS decoder 530 is driven to perform R-S decoding on one horizontal line.

In step 926, the frame / erasure buffer and the RS decoder controller 550b store the error address (error occurrence position) and error weight (error size) which are the result of the decoding of the RS decoder 530.

In step 928, the frame / erasure buffer and RS decoder controller 550b checks whether an error needs to be corrected based on the RS decoding result of step 926, and if necessary, proceeds to step 930. Frame / erase buffer and RS decoder controller 550b corrects the values stored in frame buffer 513.

On the other hand, if the decoding is finished for all horizontal rows of values stored in the erasure buffer 515 as a result of step 924, the frame / eraser buffer and the RS decoder controller 550b proceed to step 932 and are not shown. The serial interface 704 is available to output the IP datagram stored in the frame buffer 513 to the application processor.

If the serial interface 704 is available in step 932, the frame / eraser buffer and RS decoder controller 550b controls the switch 740 to read the IP datagram from the frame buffer 513 in step 934. The local SSP 702 transmits the data to the application processor.

On the other hand, if the serial interface 704 is not available as a result of the check in step 932, the frame / eraser buffer and the RS decoder controller 550b in step 936 indicate that the processor 708 of the DVB-H receiver receives a frame buffer ( In order to be able to read the IP datagram of 513, it is checked whether an interrupt signal can be generated.

If the interrupt signal can be generated in step 936, the frame / eraser buffer and RS decoder controller 550b controls the switch 740 to connect the frame buffer 513 and the bus interface 710 in step 938. The processor 708 generates an interrupt signal.

10 illustrates a structure of a horizontal row searcher provided in the frame / erase buffer and the RS decoder controller 550b according to the second embodiment of the present invention.

In general, the RS decoder 530 performs RS decoding in units of horizontal rows. The RS decoder 530 for MPE-FEC is an eraser of (N = 255, k = 191, t = 32). If an array decoder satisfies 2V + P ≦ 64 (V: number of errors, P: number of erasures), the corresponding row may be decoded.

Channel decoders such as Viterbi decoders and turbo decoders, as well as RS decoders, have the ability to correct errors on their own with only received codeword data. Error correction of the RS decoder proceeds to the process of locating the error, finding the magnitude of the error, and finally correcting the error. The erasure RS decoder is a modified form of the RS decoder. If we know that is an error, the information to find the error location can be used in the process of determining the error size, thereby improving the error correction capability.

That is, the RS decoder 530 can use not only data stored in the frame buffer 513 but also erasure information, thereby improving error correction capability. RS code is a kind of block code. In the block code, an encoding / decoding process is performed in units of blocks. The size of the block is N, the length of information data is K, and t is an error correction capability. That is, if the number of erasures is 65 or more, it is out of the correction capability of the RS decoder 530, so it is not necessary to perform decoding. Since the erasure of the frame / erase buffer and the RS decoder controller 550b reads the contents of the erasure buffer 515, the erasure buffer is erased before the RS decoding is performed on all horizontal rows. The number of erasures is counted for each horizontal row of 515, and if the number is 65 or more, control is performed not to perform RS decoding for the corresponding horizontal row.

In general, the decoding time of the RS decoder 530 using a modified Euclidian (ME) algorithm having a systolic array structure is about 3N + (N-K) + a = 4N-K + a clock cycles. Here, the RS code is one kind of block code, and the block code is encoded / decoded in block units. The size of this block is N, the length of information data is K, and t represents error correction capability. The number of erasures for Z rows is shorter than 4N-K + a clock cycles, which are N clock cycles and R-S decoding time. However, the method of determining whether to decode by counting the number of erasers in each horizontal row, respectively, causes an increase in decoding time when the number of erasers is less than 65 for all horizontal rows.

Accordingly, the second embodiment of the present invention uses the horizontal line searcher 1000 as shown in FIG. 10 to reduce the time for deciding whether to decode or not.

Eraser buffer 515 is configured to read data for i horizontal lines 1002 simultaneously. When the horizontal line searcher 1000 searches the horizontal line, the data read from the erasure buffer 515 is input to i counters 1000a. When the horizontal line 1002 search is completed, the i counters 1000a stores the number of erasers for the i horizontal lines 1002. The number of erasers is input to each of the i comparators 1000b, and the comparator 1000b controls a flag 1000c for causing the RS decoder 530 to perform decoding when the number of erasers is less than 65. Is set to "1".

The frame / erase buffer and RS decoder controller 550b selects a flag having the smallest horizontal row index from the set of “1” among i flags 1000c, so that the horizontal corresponding to the index of the selected flag is selected. RS decoder 530 is controlled to perform RS decoding for a row. The index means the order, the horizontal line index refers to the horizontal line number (order), and the column index refers to the column number. Selecting a smaller horizontal row index means column-wise decoding sequentially from the horizontal row above the frame buffer 513 (or erasure buffer) 515.

The frame / erase buffer and RS decoder controller 550b sets (resets) the flag for that horizontal line back to " 0 " after RS decoding is complete. The horizontal line search is performed when all i flag values are "0" and there are remaining horizontal lines in the eraser buffer 515. The row search method according to the second embodiment of the present invention reduces the horizontal line search time to N / i compared to the first embodiment. As the value of i increases, the time required for horizontal line searching decreases, but the hardware size increases. Therefore, an appropriate value of i is selected according to resources such as the performance or size of the DVB-H receiver.

The frame / erase buffer and RS decoder controller 550b will correct the value stored in the frame buffer 513 with the decoding result after RS decoding for one horizontal row. In the first embodiment, the controller 550 includes an intermediate buffer of size Nx8, and reads data for a horizontal row from the frame buffer 513 again when the decoding result of the RS decoder 530 is output. After storing in the intermediate buffer in addition to the error weight output from the 530, if it is determined that error correction is possible after the end of decoding, a method of storing the value stored in the intermediate buffer back to the frame buffer 513 is used.

In this first embodiment, the above-described intermediate buffer is additionally required, and if error correction is possible, the RS decoding time for one horizontal row is increased to 5N-K + a.

The frame / erase buffer and RS decoder controller 550b according to the second embodiment of the present invention uses an intermediate buffer of (NK) x2x8 size instead of using an Nx8 sized intermediate buffer used in the first embodiment. . The intermediate buffer is used to store the error address and error weight output from the R-S decoder 530. Instead of storing all N weight data, the intermediate buffer stores only the error address and the error weight of the location where the error occurred. The intermediate buffer will be described with reference to FIG. 11 to be described later.

11 illustrates an intermediate buffer 1102 according to a second embodiment of the present invention. In the second embodiment of the present invention, instead of using a physically separated intermediate buffer, the frame buffer 513 is configured by increasing the vertical column of the frame buffer 513 from 255 bytes to 256 bytes. The last column 1100 having a size of 1 byte increased in the frame buffer 513 is used as the intermediate buffer 1102.

When storing the error address (error position) and error weight (error size) output from the RS decoder 530, the frame / eraser buffer and the RS decoder controller 550b need to access the frame buffer 530. Since the intermediate buffer 1102 and the frame buffer 513 use the same physical memory. If physically the same memory is used, the area overhead caused by the glue logic of the memory is reduced. Here, the glue logic refers to an address decoder, an I / O driver, a sense amp, a clock / address buffer, a control block, and the like except for a location (RAM core) for storing actual data in a memory.

According to the second embodiment of the present invention, if it is determined that error correction is possible at the end of decoding, the frame / erase buffer and the RS decoder controller 550b may determine the length of the frame buffer 513 designated by the error address stored in the intermediate buffer 1102. After reading data from the column, the error corrected data is stored in the corresponding column of the frame buffer 513 in addition to the error weight stored in the intermediate buffer. The time taken for the error correction operation is proportional to the number of errors and is a maximum of 3 * (N-K) clock cycles. Thus, the RS decoding time for one horizontal row is up to 4N-K + a + 3 (N-K) = 7N-4K + a clock cycles. In case of RS decoding for MPE-FEC of DVB-H, in the first embodiment, the R-S decoding time for one row is reduced from 1084 + a clock cycles to 1021 + a clock cycles. If the number of errors to correct is small, this time will be further reduced.

As described above, the DVB-H receiver has to detect a section in the TS packet in order to recover the pure IP datagram from the TS packet received through the physical layer. And payloads of each section should be reconstructed into MPE-FEC frame and can be restored to IP datagram when RS decoding process is performed. In the second embodiment of the present invention, the method and apparatus for reconstructing and decoding an MPE-FEC frame in a DVB-H receiver have been corrected / supplemented.

To increase user convenience, DVB-H receivers must provide shorter channel switching times or provide picture in picture (PIP) functionality. However, the DVB-H receiver mentioned in the above-described second embodiment cannot support a continuous reception mode or a parallel service for shortening a channel switching time or providing a PIP function.

In the DVB-H receiver according to the second embodiment, the frame / erase buffer and the RS decoder controller 550b are implemented as one finite state machine, so the frame / erase buffering operation according to the section data input is performed. The RS decoding operation and the IP datagram output operation are sequentially performed. Since DVB-H receivers of this structure cannot demodulate two bursts in time at the same time, they cannot provide PIP operation for two broadcast channels corresponding to two bursts, and cannot demodulate multiple bursts. Therefore, delay time occurs when switching channels.

The problem according to the second embodiment will be described with reference to FIG. 12.

12A is a timing diagram when a burst is received by the MPE-FEC decoder 315 according to the second embodiment of the present invention, and FIG. 12B is an MPE-FEC decoder according to the second embodiment of the present invention. 315 is a timing diagram when receiving consecutive bursts.

In FIG. 12A, it is assumed that the DVB-H receiver receives and demodulates only burst # 1 of N bursts.

Reference numeral 1202 denotes a time at which the frame / erase buffer and the RS decoder controller 530b receives the section data from the MPE PID and the MPE section detector 530a and buffers the frame data in the frame buffer 513. The time when the RS decoder 530 performs RS decoding on the section data buffered at 1202 by the erasure buffer and the control of the RS decoder controller 530b. Reference numeral 1206 denotes a time for outputting data of the burst # 1 RS decoded in 1204 through the serial interface 704, and reference numeral 1208 indicates that the frame buffer 513 is configured to perform operations 1202 to 1206. Indicates the time occupied.

As shown in FIG. 12A, it can be seen that the DVB-H receiver according to the embodiment of the present invention has no problem in receiving and demodulating one channel. However, when receiving multiple bursts, as shown in FIG. 12B, the bursts are decoded in the order of skipping at one burst (or more) interval (e.g., burst # 1, burst # 3, burst # 5 ..). It can be shown that it can not decode successive bursts.

Reference numeral 1250 denotes a time at which the frame / erase buffer and RS decoder controller 530b receives section data from the MPE PID and MPE section detector 530a, and reference numeral 1252 denotes a frame / erase buffer and RS decoder controller ( 530b indicates a time for buffering the burst inputted at reference numeral 1250 in the frame buffer 513.

Reference numeral 1254 denotes a time when the frame / erase buffer and the RS decoder controller 530b perform R-S decoding on the section data buffered at 1252. Reference numeral 1256 denotes a time for outputting burst burst data decoded through the serial interface 704 at 1254, and reference numeral 1258 is occupied by the frame buffer 513 to perform operations 1250 to 1256. It shows time to become.

An interval denoted by reference numeral 1260 is a time when the frame / erase buffer and the RS decoder controller 530b receive burst # 1 from the MPE PID and the MPE section detector 530a and buffer the burst # 1 in the frame buffer 513. In section 1262, frame / erase buffer and RS decoder controller 530b receives burst # 2 from MPE PID and MPE section detector 530a but frame buffer 513 is already allocated for processing burst # 1. Burst # 2 is discarded without being buffered.

Reference numeral 1264 denotes an interval for performing R-S decoding on the buffered burst # 1 in section 1260, and reference numeral 1266 denotes a time for outputting the R-S decoded burst # 1 to the serial interface 704 in 1264.

Reference numeral 1268 denotes a time allocated until the frame buffer 513 receives and buffers the frame / erase buffer and the RS decoder controller 530b after receiving burst # 1 and outputting the R-S decoding to the serial interface 704. That is, the section 1284 is a section allocated only to burst # 1, and is a section in which buffering and R-S decoding for burst # 2 are not performed.

Reference numeral 1270 denotes that burst # 1, followed by burst # 3 skipping burst # 2, is inputted from the frame / erasure buffer and RS decoder controller 530b from the MPE PID and MPE section detector 530a to the frame buffer 513. Indicates the time to buffer. Reference numeral 1272 denotes a time point at which the R-S decoding is performed when the frame buffer 513 is buffered at the time 1262, but does not actually occur. Therefore, it is indicated by a dotted line.

Reference number 1274 is a time point to be output to the serial interface 704 when burst # 2 is RS decoded at time 1272, but the operation does not actually occur because RS decoding for burst # 2 has not been performed in the section 1272. , And therefore indicated by a dashed line.

1276 is the time when burst # 3 is followed by burst # 4 when the frame / erase buffer and RS decoder controller 530b is received from the MPE PID and MPE section detector 530a, but already the frame buffer 513 is burst #. Since it is assigned to 3, it is only input, not buffered like a dashed line. That is, the data of burst # 4 is also lost.

Reference numeral 1278 denotes a time point for R-S decoding burst # 3 buffered in the 1270 section, and reference numeral 1280 indicates a time point for outputting the R-S decoded burst # 3 to the serial interface 704. Reference numeral 1282 shows that frame buffer 513 is allocated to burst # 3.

That is, in section 1286, buffering, R-S decoding, and output to the serial interface 704 are generated only for the burst # 3, and no operation can be performed for the burst # 4. The section 1288 is a time point when the burst # 4 is output to the RS decoding and the serial interface 704 when the burst # 4 is buffered in the frame buffer 513 in the section 1276. However, the burst operation is not buffered in the frame buffer 513. Is an unoccupied section.

As described above, according to the second embodiment of the present invention, when a plurality of bursts are continuously received, the frame buffering, RS, because the frame / erase buffer and the RS decoder controller 530b are constituted by only one finite state machine. Decoding, serial output, etc. were forced to operate in order for each time zone.

Thus, for multiple bursts received at the same time, it was difficult to process multiple bursts at the same time. As a result, it cannot provide PIP operation for two channels, cannot perform MPE-FEC frame decoding for consecutive bursts in continuous reception mode for channel switching, and in order of skipping one burst (or more). Burst can be decoded. In addition, the DVB-H receiver according to the second embodiment may not decode a parallel service case in which two or more PIDs are allocated to one burst to carry and transmit broadcast data of a plurality of channels.

Therefore, in the third embodiment of the present invention, a new embodiment for decoding the MPE-FEC frame by the DVB-H receiver will be described. In the third embodiment, a broadcast data decoding apparatus and method and a receiver structure capable of performing decoding in a parallel service case in a DVB-H receiver for a continuous reception mode for reducing channel switching time and a PIP mode will be proposed.

13 is a configuration diagram of an MPE-FEC decoder 315 according to a third embodiment of the present invention. First, prior to describing FIG. 13, the same reference numerals as used in FIG. 7 are used for blocks that play the same role as FIG. 7.

Controller 1300 of MPE-FEC decoding 315 includes an MPE PID and MPE section detector 1300a and a main control unit 1300b that includes a frame / eraser buffer controller, an RS decoder controller, and a serial output controller. .

The MPE PID and MPE section detector 1300a controls the circulating buffer 1314 to perform CRC on the MPE and MPE-FEC sections extracted from the received TS packets. Unlike the MPE PID and MPE section detector 700 in the second embodiment, a plurality of MPE PID and MPE section detector 1300a in the third embodiment may be provided to support parallel services, and each MPE PID may be provided. And the MPE section detector 1300a receives section data of at least two consecutive bursts and outputs section data of each burst to the main control unit 1300b.

The main control unit 1300b is implemented with a finite state machine each of a frame / erasure buffer controller, an RS decoder controller, and a serial output controller. A detailed configuration of the main control unit 1300b will be described in detail with reference to FIG. Let's explain.

In FIG. 13, the MPE PID and the MPE section detector 1300a receive both burst # 1 and burst # 2 and output the section data of burst # 1 and burst # 2 in which the CRC check resulted in 'Good', respectively, in the main control unit 1300b. Is showing the output.

The main control unit 1300b controls the frame buffer 1308, erasure buffer 1310, and R-S decoder 1312 via arbiter 1 1302 and arbiter 2 1304. Arbitrator 1 1302 and arbiter 2 1304 are frame buffer 1308 or erasure buffer 1310 when main control unit 1300b needs to perform read / write operations for buffering, RS decoding, or serial output. The role is to share the time of access. In addition, when the CPU 1320, which is a processor of the DVB-H receiver, approaches the frame buffer 1308 through the bus interface 1306, the CPU 1320 controls the collision of the access timing of the main control unit 1300b.

That is, the reason why the arbiters 1302 and 1304 are provided for each of the frame buffer 1308 and the erasure buffer 1310 is that the access to the frame buffer 1308 and the erasure buffer 1310 is the main control unit. It is because it is made by a plurality of controllers and the CPU 1320 in (1300b) it is necessary to control their access.

The frame buffer 1308 has a size twice as large as that of the second embodiment to simultaneously store IP datagrams and parity data of two or more received bursts, and buffers the IP datagrams and the parity data. Is described in detail in the operation of frame buffer 513 in FIG.

The erasure buffer 1310 includes the reliability of the section data marked by the main control unit 1300b when the main control unit 1300b receives section data from the MPE PID and the MPE section detector 1300a. Reliable) information is stored. The process of marking reliability information on the eraser buffer 1310 and the initialization operation are described in detail in the operation of the eraser buffer 515 of FIG. 7.

The RS decoder 1312 performs RS decoding using parity data on the IP datagrams buffered in the frame buffer 1308 by the control of the main control unit 1300b, and the decoding time of the RS decoder 1312 and The decoding operation is described in detail in FIGS. 5 and 7.

The output of the R-S decoded IP datagram is performed via the Local SSP 702 and the serial interface or Bus I / F 1306. Each of the Local SSP 702 and the Bus I / F 1306 may directly output an IP datagram in serial form or may output the IP datagram to the CPU 1320 of the DVB-H receiver via a bus (APB or AHB).

The MPE-FEC_done interrupt signal informs the CPU 1320 that the decoding of the MPE-FEC frame for one burst has ended and indicates the point at which data can be read at the same time.

14 is a detailed block diagram of the main control unit 1300b according to the third embodiment of the present invention, and FIG. 15 is a detailed block diagram of blocks around the main control unit 1300b according to the third embodiment of the present invention. . Hereinafter, an operation of decoding successive bursts to operate in the continuous reception mode and the PIP mode in the DVB-H receiver according to the third embodiment of the present invention will be described with reference to FIGS. 14 and 15.

Referring to FIG. 14, the main control unit 1300b according to the third embodiment of the present invention includes a segment allocator 1400, two buffering controllers 1402a and 1420b, and an RS queue 1404. ), An RS decoder controller 1406, a serial output queue (SOUT Queue) 1408, and a serial output controller 1410.

Two buffering controllers 1402a and 1402b receive burst information and section data 1450 to 1456 from two MPE PID and MPE section detectors 1300a, respectively. Buffering controller # 1 1402a performs a buffering operation and a reliability marking operation on burst # 1, and buffering controller # 2 1402b performs a buffering operation and a reliability marking operation on burst # 2.

The operation flow of the buffering controller 1402 will be described with reference to FIG. 16 below. The burst information (section parameters) 1450 and 1454 input from the MPE PID and the MPE section detector 1300a include MPE_FEC_EN information indicating whether a PID (Packet Identifier) and MPE-FEC have been used and an MPE-FEC frame size. N_ROW (number of rows), which is horizontal row number information.

The "burst information" further includes PID, MPE_FEC_EN, N_ROW, Priority, handover, etc. in addition to table_id, section_length, padding_columns, table_boundary, frame_boundary, and address, which are shown in Table 1. Table 2>.

Burst Information Contents table_id Indicates MPE section or MPE-FEC section. section_length The length in bytes from the fourth byte of the section to the end of the section containing the CRC32. padding_columns It represents the total number of zero padding columns in the application data table area of the MPE-FEC frame and has a value from 0 to 190. table_boundary When set to '1', it indicates that the current section is the last section in each data table area of the MPE-FEC frame. frame_boundary When set to '1', it indicates that the current section is the last section of the MPE-FEC frame. address The first byte of the section payload loaded by the current section indicates the byte position in each data table area of the MPE-FEC frame. PID Packet Identifier, an ID number assigned to a TS packet, used to identify a service (channel). MPE_FEC_EN Indicates whether MPE-FEC is applied. N_ROW Number of rows (0: 256 rows, 1: 512 rows, 2: 768 rows, 3: 1024 rows) Priority When operating in PIP or continuous reception mode, high priority can be given to the channel being watched. handover In case of handover to different FA, it may be impossible to distinguish each other by using the same PID number even though they are different channels. At this time, a handover, which is a FA switching or not, is used as an additional means for distinguishing channels.

Upon receiving the first and second burst information 1450 and 1454 at the start point of inputting the first and second section data 1452 and 1456, the buffering controller 1402a and 1402b receives a frame buffer and an eraser buffer of a required size. In order to receive the area, the horizontal row number information (N_ROW) 1458 and 1460 are transmitted to the segment allocator 1400. The segment allocator 1400 allocates an area of the frame buffer 1308 and the erasure buffer 1310 by a size corresponding to the received horizontal line number information (N_ROW) 1458 and 1460 and sets the horizontal line number information. The first and second frame segments 1462a and 1462b, which are address information of the area of the frame buffer 1308 allocated to store the section data of the first data, are notified to the buffering controller 1402. In addition, the first and second eraser segments 1464a and 1464b which are address information of an area of the eraser buffer 1310 allocated to store reliability information corresponding to the size of the horizontal line number information 1458 and 1460. It is also sent to the buffering controller 1402 together.

When the buffering controller 1402 receives the first and second frame segments 1462a and 1462b and the first and second erasure segments 1464a and 1464b, the first and second section data 1452 and 1456 are input. ) Is written in the frame buffer 1308 as shown by reference numeral 1466, and the eraser data is transmitted as indicated by reference numeral 1468 to indicate the corresponding position of the erasure buffer 1310 as "reliable".

The buffering controller 1402, which has performed section data buffering and erasure data buffering in the frame buffer 1308 and the eraser buffer 1310, respectively, is a respective burst for burst # 1 and burst # 2 to the RS queue 1404. Information 1470a and 1470b and buffer address information 1472a and 1472b are transmitted. The burst information 1470a and 1470b transmitted from the buffering controller 1402 to the RS queue 1402 are PIDs, MPE_FEC_EN, N_ROW, HANDOVER, and RS_ERASURE information of the burst, and buffer address information 1472a and 1472b are the segment allocator. Frame segment and erasure segment information received from 1400.

In this case, the RS_ERASURE information is obtained by compressing and storing reliability information of the MPE-FEC region of the erasure buffer 1310 in a register file 1608 of 1 column x 63 rows x 1 bit, and the reliability information must be maintained for each burst. The buffering controller 1402 obtains this from the received section data and transmits it to the RS decoder controller 1406 via the RS queue 1404 to be used for MPE-FEC RS decoding.

There are three ways the buffering controller 1402 determines the end of burst data input. If the first method detects frame boundaries by the MPE PID and MPE section detector 1300a, and the second method indicates that the time slicing processor 313 indicates exceeding the maximum burst period, the third method reduces the section address. If it is. After inputting the section data for one burst by each condition, the buffering controller 1402 receives the information received from the MPE PID and the MPE section detector 1300a, the frame buffer 1308 and the erasure buffer (for the corresponding burst). 1310) transmit the address information of the region within the RS queue (1404).

The R-S queue 1404 transmits burst information 1470a and 1470b and buffer address information 1472a and 1472b received from the buffering controller 1402 to the R-S decoding controller 1406 as indicated by reference numeral 1474. When the RS decoder controller 1406 receives the burst information and the buffer address information 1474 from the RS queue 1404, the arbiter 1 1302 performs error correction on the section data buffered in the frame buffer 1308. Third section data 1476 is obtained, and third erasure data 1490 is obtained via Arbitrator 2 (1304). In this case, the position in the frame buffer of the third section data is obtained from the buffer address information 1474 received from the R-S queue 1404.

The R-S decoder controller 1406 controls the R-S decoder 1312 to perform R-S decoding on the third section data 1476. If the decoding result of the RS decoder 1312 is capable of error correction, the RS decoder controller 1406 sends the modified section data 1478, which corrects the error of the third section data 1476, through the arbitrator 11302. It buffers the frame buffer 1310 again. The reason why the R-S decoder controller 1406 fetches the erasure data 1490 from the erasure buffer 1310 is to copy & paste the corresponding part to accurately indicate the position where the reliability information is marked. Since the RS decoder 1312 for MPE-FEC uses an erasure RS decoder, not an ordinary RS decoder, the RS decoder controller 1406 reads erasure information from the eraser buffer 1310 to the RS decoder 1312. Must be provided. Otherwise there will be no performance benefit resulting from performing R-S decoding.

In more detail, as described above with reference to FIG. 10, the RS decoder 1312 performs RS decoding in units of horizontal rows, and the RS decoder 1312 for MPE-FEC (N = 255, If 2V + P≤64 (V: number of errors, P: number of erasures) is satisfied as an erasure decoder of k = 191 and t = 32, the corresponding row can be decoded.

In addition to RS decoders, channel decoders such as Viterbi decoders and turbo decoders have the ability to correct errors on their own with only the received codeword data. Error correction of the RS decoder proceeds to the process of locating the error, finding the magnitude of the error, and finally correcting the error. The erasure RS decoder is a modified form of the RS decoder. If we know that is an error, the information to find the error location can be used in the process of determining the error size, thereby improving the error correction capability. That is, the R-S decoder 1312 may use not only data stored in the frame buffer 1308 but also erasure information, thereby improving error correction capability.

The RS decoder controller 1406 converts the sixth burst information (PID, MPE_FEC_EN, N_ROW) 1480 and the fourth buffer address information (frame segment information, erasure segment information) 1462 into the serial out queue 1408. Output The RS decoder controller 1406 loads the sixth burst information 1480 into a header of a packet transmitted when the serial output controller 1410, which will be described later, operates the serial output through the Local SSP 702 and transmits it to the application processor. The sixth burst information 1480 is transmitted to the serial out queue 1408. This information is used by the application processor to receive the packet and perform further processing. The fourth buffer address information 1462 sent together to the serial out queue 1408 is used by the serial output controller 1410 to calculate the correct position of the fourth section data 1484 within the frame buffer. The serial out queue 1408 transmits the sixth burst information 1480 and the fourth buffer address information 1462 to the serial output controller 1410 as shown by reference numeral 1486.

Since the RS decoder controller 1406 outputs the burst information 1480 and the buffer address information 1462 to the serial out queue 1408 after the RS decoding for the input string is finished, the reliability information is no longer needed. Eraser segment deallocation 1486 is requested to segment allocator 1400. After all transmissions for one burst are completed, the serial output controller 1410 requests the segment allocator 1400 to release the frame segment allocation 1488. It is also possible to output section data of the frame buffer 1308 to the CPU 708 via the bus interface 1306 as well as the serial output controller 1410. However, as shown in FIGS. 14 and 15, the frame buffer 1308 and the erasure buffer 1310 have a finite state such as a buffering controller 1402, an RS decoder controller 1406, and a serial output controller 1410. In addition to the machine, the bus interface controller 1306 must be connected so that it is connected to the arbiters 1302 and 130, which play an arbitration role so that each block is not accessed simultaneously. That is, read / write access to the frame buffer 1308 and erasure buffer 1310 is finally performed through the arbiters 1302 and 1304. This is because access to the frame buffer 1308 and erasure buffer 1310 is performed by the controllers 1402, 1406, 1410, which are a plurality of finite state machines. Arbitrators 1302, 1304 can control the access of each controller 1402, 1406, 1410 by allocating time to access each controller 1402, 1406, 1410.

In addition, as shown in FIGS. 14 and 15, in the third embodiment of the present invention, the three types of controllers 1402, 1406, and 1410 operate independently of each other in time, such that the MPE-FEC decoder 315 simultaneously operates. Multiple bursts can be processed. Since the operating speeds of the three types of controllers 1402, 1406, and 1410 are different from each other, RS queues 1404 and SOUT queues 1408 are provided between the controllers 1402, 1406, and 1410. This prevents any data loss that may occur.

 FIG. 16 illustrates a structure in which the segment allocator 1400 divides the frame buffer 1308 and the erasure buffer 1310 into segments having a predetermined size.

The segment allocator 1400 according to the third exemplary embodiment of the present invention may request a frame buffer 1308 and an erasure buffer 1310 at the request of the buffering controller 1402, the RS decoder controller 1406, and the serial output controller 1410. It also allocates and releases the realm of). As shown in FIG. 16, in the third embodiment of the present invention, the frame buffer 1308 and the erasure buffer 1310 are divided into segments of a predetermined size for efficient use of the buffer memory area.

One segment of frame buffer 1308 and erasure buffer 1310 is 256 columns x 64 rows in size. Since frame buffer 1308 is processed in bytes and erasure buffer 1310 is processed in bits, one segment size of frame buffer 1308 is 256 columns x 64 rows x 1 byte 1600. One segment size of the buffer buffer 1310 is 256 columns x 64 rows x 1 bit 1602. The size of frame buffer 1308 is 4Mb, which is twice the maximum size of 2Mb for one burst, thus having 32 segments in frame buffer 1308. Reference numeral 1604 shows that the segment allocator 1400 performs the segmentation of the frame buffer 1308 according to the third embodiment of the present invention.

According to the DVB-H standard, the value of N_ROW (the number of horizontal rows) may be 256,512,768,1024. Processing segment allocation in 256-row units allows the buffer to be used more efficiently when bursts with smaller rows, such as 256 or 512 columns, are received in succession. In the third embodiment of the present invention, as shown by reference numeral 1606, only the maximum size 0.25Mb for one burst is used for the erasure buffer 1310. As such, in the third embodiment of the present invention, the reason why the maximum size for one burst is 0.25 Mb in the erasure buffer 1310 is essentially 1 bit per byte of data in the frame buffer 1308. Because it is necessary. Therefore, if the size of the frame buffer 1308 is increased from 2Mb to 4Mb (when extending from the second embodiment to the third embodiment for continuous reception mode operation), the size of the erasure buffer 1310 is 2Mb x 1 /. It will increase from 8 = 0.25 Mb to 4 Mb x 1/8 = 0.5 Mb. By using the properties of the MPE-FEC section, however, the register file 1608 is used to reduce the size of the erasure buffer 1310 to three quarters of its original size and the serial output controller 1410 does not need erasure information. By further reducing the size of the eraser buffer 1310 by using the characteristic, it is possible to implement even using only 0.25Mb, which is half of the original required 0.5Mb.

 In order to operate in continuous receive mode without using additional memory for erasure buffer 1310, information about the first 192 rows (vertical lines) of reliability information for one burst is stored in erasure buffer memory 1606. Information about the remaining 63 rows is stored in a separate register file 1608 having a size of 1 column (horizontal lines) x 63 rows (vertical lines). The storage of reliability information in the one-sized storage area of reference 1608 is attributable to the characteristics of the DVB-H standard, which all have the same length of the MPE-FEC section. Among the sections for a burst, the MPE sections located in the application data region can have varying lengths of 32-4096 bytes, which is why storage of reliability information is needed for each byte. In contrast, all MPE-FEC sections located in an R-S data region have the same length as N_ROW. Therefore, the reliability information for one section is all the same, and the reliability information for one row can be stored using only one bit.

The first application data area is 191 rows and the last R-S data area is 64 rows. In the present invention, since the segment is processed in units of 64 rows, the first 192 rows are stored in the erasure buffer memory, and the remaining 63 rows are stored in a compressed storage having a size of one column. By using this method, we can save one segment per burst when N_ROW is 256 and 4 segments per burst when N_ROW is 1024.

The saved segments of the erasure buffer 1310 are used to store reliability information for the section of the next burst during the time of performing RS decoding on the current burst. Since the saved area is one quarter of the area for the original burst, continuous reception can be operated without overflowing the buffer if the RS decoding time for the burst is less than one quarter of the total input time of the burst. Reference numerals 1308 and 1310 of FIG. 13 of the present invention are an example of a case where an MPE-FEC frame having an N_ROW of 1024 is mapped to a frame buffer 1308 and an erasure buffer 1310, respectively. It is a block diagram which shows the division of. In FIG. 16, reference numerals 1604 and 1606 denote physical configurations in which segments are arranged in the order of segment numbers, respectively, in an actual frame buffer 1308 and erasure buffer 1310.

In more detail, as described above, the frame buffer 1308 is composed of two RAMs of 2 Mb, and each RAM of 2 Mb is divided into an area of 256 columns X 24 rows. Accordingly, as shown by reference numeral 1604, the 2Mb RAMs 1308a and 1308b constituting the frame buffer 1308 are allocated to each of 16 segments of 32 segments. That is, the area 1608 is allocated to the first segment 1600 in the frame buffer 1604 allocated to 32 segments. 16 segments, that is, 0 to 15 segments and 16 to 31 segments are segments to which section data stored in a frame buffer 1608 having a size of 2 Mb are allocated.

Among the reliability information buffered in the erasure buffer 1606, the region 1310a in which the reliability information of the section data buffered in the frame buffer 1308 is buffered is allocated in units of 12 segments as shown by reference numeral 1606. The portions marked with the reliability information on the R-S data of reference number 1310b may be stored in the register file 1608 without allocating a memory like reference numerals 1604 and 1606.

For example, assume that burst # 2 is received in sequence after burst # 1 is first received. If so, the reliability information of the section data of burst # 1 is allocated to segments 0 to 11 of erasure buffer 1606, and the reliability information of the RS data of burst # 1 is stored in register file 1608, RS decoding is performed on burst # 1. At this time, since the DVB-H receiver is in a continuous reception mode, burst # 2 is also continuously received. Therefore, reliability information of section data of burst # 2 is allocated to 12 to 15 segments of erasure buffer 1606, and segments 0 to 11 allocated to burst # 1 at the time when RS decoding of burst # 1 ends. Since the information is released, reliability information of burst # 2 to be allocated after the 12 to 15 segments starts to be allocated to the released 0 to 11 segments. Therefore, in the third embodiment of the present invention, even in the continuous reception mode, the section data of the continuous bursts and the reliability information about the section data can be buffered without being lost, so that the successive bursts can be successfully decoded and provided to the user.

17 is a flowchart illustrating an operation of a buffering controller 1402 according to a third embodiment of the present invention. In the third embodiment of the present invention, two buffering controllers 1402a and 1402b receive burst information and section data from two MPE PIDs and two section detectors 1300a.

In step 1700, the buffering controller 1402 checks whether a burst or section has started. Here, whether or not the burst has been started may be determined according to whether or not the burst start signal is input from the time slicing processor 313. When the section is input from the MPE PID and the section detector 1300a, it is determined that the section has started.

If the burst or section has been started in operation 1700, the buffering controller 1402 proceeds to operation 1702 and stores the first burst information 1450 and the second burst information 1454, which are section parameters. In operation 1704, the buffering controller 1402 transmits the horizontal row number (N_ROW) information of the section parameter stored in operation 1702 to the segment allocator 1400, and the frame buffer 1308 and the erasure buffer corresponding to the size thereof. Area 1310). That is, the segment allocator 1400 allocates an area of a frame buffer and an erasure buffer corresponding to the N_ROW value received in step 1704, and informs the buffering controller of address information of the corresponding area.

In step 1708, the buffering controller 1402 buffers the section data 1466 input to the address of the frame buffer 1308 area allocated from the segment allocator 1400, and marks reliability information in the erasure buffer 1310. do.

In step 1710, the buffering controller 1402 checks whether the last MPE section is input and the input of burst data is finished. At this time, there are three methods for the buffering controller 1402 to determine the termination of the burst data input. First, when the MPE PID and the MPE section detector 1300a detects a frame boundary, and when the time slicing processor 313 indicates that the maximum burst period is exceeded, the section address decreases.

After inputting section data for one burst under each condition as a result of the check in operation 1710, the buffering controller 1402 stores the last address of the frame buffer 1308 in which the section data is stored in step 1716. In operation 1722, the buffering controller 1402 checks whether a section input has been started. If the check result section of operation 1722 is started, the buffering controller 1402 proceeds to operation 1724 and stores a section parameter. In operation 1726, the buffering controller 1402 checks whether or not the burst boundary is determined by the address. If the buffering controller 1402 determines the burst boundary by the address, the buffering controller 1402 proceeds to operation 1720 to determine previous burst information. It queues to the RS queue 1404 and proceeds to step 1728 if it is not a burst boundary by address. In operation 1728, the buffering controller 1402 stores the section parameter again.

In operation 1726, the operation of checking whether the buffering controller 1402 is a burst boundary by an address is performed for the following reasons.

In the DVB-H receiver, when the last section of the burst is not detected due to an error or the like, the end signal of the burst, frame_boundary, does not occur. If the burst end signal is unknown, the DVB-H receiver does not proceed with MPE-FEC RS decoding for the current burst ("burst k") and the contents of the next burst ("burst k + 1") are over the current burst. It will be overwritten and eventually the value of burst k will be lost. Therefore, it is inevitable to determine the boundary of the burst with the address increase. The operation in operation 1726 is to determine the subsequent operation according to the determination. The time when the burst boundary by address is detected is the time when the first section for burst k + 1 starts to be input. Accordingly, the buffering controller 1402 puts information about the burst k into the RS queue 1404 (step 1720), stores the parameters of the first section for the burst k + 1 (step 1702), and proceeds with the buffering operation. do. If it is not a burst boundary by address, then the section for burst k is still input. Accordingly, the buffering controller 1402 stores the section parameters (step 1728) and performs a buffering operation.

If the result of the check in step 1710 is not the last MPE section, the buffering controller 1402 proceeds to step 1712 and checks whether a frame boundary exists.

If the result of the check in step 1712 is a frame boundary, the buffering controller 1402 proceeds to step 1714 to queue the burst information to the RS queue 1404, and if not, the buffering controller 1402 proceeds to step 1718 to time. It is checked whether the burst end signal is input from the slicing processor 313. In step 1718, when the burst end signal is received from the time slicing processor 313, the buffering controller 1402 proceeds to step 1714, and the information received from the MPE PID and the MPE section detector 1300a and the frame buffer for the burst. 1308 and address information of the region in erasure buffer 1310 are pushed into RS queue 1408.

18 is a flowchart illustrating an operation of the R-S decoder controller 1406 according to the third embodiment of the present invention. In step 1800, the R-S decoder controller 1406 checks whether the R-S queue 1404 is empty. If the R-S queue 1404 is not empty as a result of the check in step 1800, the process proceeds to step 1802 to extract one burst information from the R-S queue 1404 and perform R-S decoding according to the burst information.

In step 1804, the R-S decoder controller 1406 performs last row and padding row processing before performing actual decoding. Here, the last row processing indicates that the MPE PID and MPE section detector 1300a indicates reliability information on the last column of the row where the end of the last MPE section is located when the last MPE section is detected. In the MPE section, data for a predetermined number of padding rows is expressed as "0" and reliability information is expressed as "reliable". The number of padding rows is known at the time of MPE-FEC section detection.

Thus, in step 1806, the R-S decoder controller 1406 searches for a decodable column in a column set unit, and checks whether decoding is completed for all columns in step 1808.

If the decoding is not completed for all columns as a result of the checking in step 1808, the R-S decoder controller 1406 performs R-S decoding in units of one row in step 1810. In operation 1812, the R-S decoder controller 1406 checks whether error correction is required for the R-S decoded string after the R-S decoding. In step 1812, if the error correction is necessary, the R-S decoder controller 1406 proceeds to step 1814 to correct the error, and in step 1816, the reliability information is initialized in units of ten sets. That is, steps 1810 to 1816 are repeatedly performed until decoding of all columns is completed.

If the RS decoding of all the columns of the corresponding burst is completed as a result of the check in step 1808, the RS decoder controller 1406 proceeds to step 1818 and transmits the burst information and the address information of the frame buffer 1308 to the SOUT queue 1408. . Since the reliability information is not needed after the RS decoding is completed, the RS decoder controller 1406 no longer maintains the address information of the erasure buffer 1310 in the controller, and thus the segment allocator 1400 Requests to release the segment segment.

19 is a flowchart illustrating the operation of the serial output controller 1410 according to the third embodiment of the present invention.

In step 1900, the serial output controller 1410 checks whether the SOUT queue 1408 is empty. In operation 1900, if the SOUT queue 1408 is not empty, the process proceeds to step 1902 to pop out one burst information from the SOUT queue 1408. In step 1904, the serial output controller 1410 checks whether the serial interface 1704 is enabled. Here, the meaning that the serial interface 1704 is activated is the same as the meaning that the serial interface 1704 is set to send data to an application processor (not shown) through the serial interface 1704.

If the serial interface 1704 is activated as a result of the check in step 1904, the serial output controller 1410 proceeds to step 1906 to generate a packet header with the burst information taken out of the SOUT queue 1408 to generate the packet header in step 1908. Is output to the serial interface block 704.

The serial output controller 1410 generates the packet payload by transmitting the generated packet header to the serial interface block 704 and reading data from the frame buffer 1308 to the serial interface block 704 in step 1910. .

In step 1912, the serial output controller 1410 checks whether the output of one burst has ended. If the output of one burst has ended, the serial output controller 1410 proceeds to step 1916 to check whether the output of one packet is finished. If the output of one packet is not terminated as a result of the check in step 1916, the process proceeds to step 1918 and transmits by adding zero padding. The reason for performing the operations of steps 1912 to 1918 is that if the size of the packet and the size of the transmitted data do not match at the end of the burst, '0' is padded to match the size of the packet and then additionally transmitted. This is a necessary action.

The steps 1912 and 1914 will be described in more detail below.

In general, when the serial output controller 1410 is serially transmitted to the application processor, it may be very dangerous to send all of the burst data afterwards. If the burst data received by the application processor is pushed by one bit, one byte, or some unit due to an error in the transmission operation, recovery may not be possible forever. Therefore, the burst data is cut at regular intervals, and the burst information (PID, handover, mpe_fec_en, etc.) is transmitted with a header. The transmission unit at this time is called a packet. Since the contents are irrelevant to the present invention, a detailed description of the format and length of the packet will not be described. The length of the packet may be an appropriate length for the MPE-FEC frame structure, but it may also follow a certain length of transmission specification. In the latter case, the data in the burst may not be correctly divided into packets.

In this case, the DVB-H receiver according to the third embodiment of the present invention attaches " 0 " as much as the length of the missing data to the last packet of the burst to maintain the same packet length through the operation of step 1916. . According to a third embodiment of the present invention, in step 3914, the DVB-H receiver distinguishes packets of a predetermined length at a time point when output of data for a burst is continued (step 1908). ) do.

If the output of one burst is not terminated as a result of the checking of step 1912, the serial output controller 1410 proceeds to step 1914 and checks whether the output of one packet is terminated.

If the output of one packet is terminated as a result of the check in step 1914, the serial output controller 1410 proceeds to step 1908.

If the output of one packet is terminated in step 1916, the serial output controller 1410 proceeds to step 1920 and requests the segment allocator 1400 to release the segment allocation, and the CPU 708 as shown in steps 1922 and 1924. To generate an interrupt.

20 is a timing diagram of an MPE-FEC decoder 315 according to a third embodiment of the present invention.

Since the frame buffer 1308 and the erasure buffer 1310 are allocated in units of 64 rows, the new segment allocation is requested when the section input for the burst progresses by 1/4. The release of frame buffer allocation is performed in units of 64 lines as the serial interface output proceeds, and the release of erasure buffer allocation is performed at the end of R-S decoding. The above description will be described in detail with reference to FIG. 20 as follows.

Reference numeral 2000 denotes a time at which the main control unit 1300b receives the bursts # 1 to # 4 from the MPE PID and the MPE section detector 1300a, and reference numeral 2002 designates the main control unit 1300b to the reference numeral 2000. The time of buffering the input burst in the frame buffer 1308 is shown.

Reference numeral 2004 denotes a time for the R-S decoder 1312 to perform R-S decoding on the section data buffered at 2002 by the control of the main control unit 1300b. Reference numeral 2006 denotes a time for outputting burst # 1 to burst # 4 decoded by reference numeral 2004 through the serial interface 704, and reference numeral 2008 denotes a frame buffer for performing operations 2000 through 2006. 1308 represents the time occupied. Reference numeral 2010 denotes a time when the erasure buffer 1310 is allocated to mark reliability information for the bursts # 1 to # 4.

Reference numeral 2012 shows an address area of the frame buffer 1308 and is divided into two 2Mb. Reference numeral 2014 shows an address area of the erasure buffer 1310 and indicates a size of 0.5 Mb.

Reference numerals 2016, 2018, 2020, and 2024 indicate that the frame buffer 1308 and the erasure buffer 1310 are allocated in units of 64 rows, so that the section input for the burst from the MPE PID and the MPE section detector 1300a is 1/4 in progress. Each time, a new segment is allocated to a new frame buffer 1308 and an erasure buffer 1310. In reference numeral 2022, the input of burst # 1 is terminated and the RS decoder is controlled by the main control unit 1300b. 1313 is a time point when RS decoding is performed on the burst # 1, and at the same time, a new burst # 2 received in succession to the burst # 1 is input, and a time point when the burst # 2 is buffered in the frame buffer 1308. . The frame buffer allocation 2008 is new at the time 2020, but there is no erasure buffer allocation 2010. Since the last quarter (row 63) is stored in the RS erasure area, no new allocation of the erasure buffer for the last quarter of the burst is performed.

Reference numeral 2024 denotes a time point at which burst # 1 data is output through the serial interface 704 after RS decoding of the burst # 1 is completed, and at the same time, the allocation of the buffer 1310 to the burst # 1 is performed. Is released. Also, as shown by reference numeral 2026, burst # 1 is allocated to the frame buffer 1308 until burst # 1 is output through the serial I / F 704. Therefore, after burst # 1 is all output to serial I / F 704, burst # 1 is deallocated from frame buffer 1308, and as new burst # 3 is inputted, as shown at 2028, the frame buffer 1308 ), Burst # 3 is buffered in the area where burst # 1 was buffered.

Reference numeral 2030 denotes a time point at which the R-S decoding for the burst # 2 is completed, and at the same time, the allocation of the burst # 2 in the erasure buffer 1310 is also released. Reference numeral 2032 denotes a time point at which burst # 2 buffered in the frame buffer 1308 is output through the serial I / F 704, and is also a time point in which the region for burst # 2 in the frame buffer 108 is deallocated. .

As shown in FIG. 20, the MPE-FEC decoder 315 according to the third embodiment of the present invention can operate in the continuous reception mode even when the N_ROW changes by efficiently allocating / releasing the buffer memory.

21 is an operation flowchart of the main control unit 1300b according to the third embodiment of the present invention.

In operation 2100, the main control unit 1300b checks whether burst data from the MPE PID and the MPE section detector 1300a is received. If the test result of step 2100 receives the section data of the burst from the MPE PID and the MPE section detector 1300a, the main control unit 1300b proceeds to step 2102, and the frame buffer 130 for the section data of the burst is input. ) Segments and erasure buffer 1310 segments.

In operation 2104, the main control unit 1300b buffers the input burst according to the frame buffer 1308 segment and the erasure buffer 1310 segment allocated in operation 2102. In operation 2106, the R-S decoding is performed on the buffered burst. After RS decoding is completed, in step 2108, the main control unit 1300b releases the allocation of the erasure buffer 1310 allocated to the burst in which the RS decoding is completed, and in step 2110, the RS decoded burst is assigned to the serial I / F ( 704).

After outputting the RS decoded burst to the serial I / F 704 in step 2110, the main control unit 1300b assigns the frame buffer 1308 allocated to the burst output to the serial I / F 704 in step 2112. ) Deallocate the segment.

In order for the receiver of the DVB-H system to decode the IP datagram from the TS packet received through the physical layer, it is necessary to detect section data from the TS packet. The payloads of each section must be reconstructed into MPE-FEC frames and can be restored to an IP datagram when the R-S decoding process is performed. As described above, the DVB-H receiver according to the third embodiment of the present invention can perform the processing on two consecutive bursts in time. The DVB-H receiver decodes two consecutive bursts, enabling the DVB-H receiver to support PIP functions and parallel services, and minimize the channel switching time by storing bursts consecutively.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the appended claims, but also by the equivalents of the claims.

As described above, according to the present invention, a continuous burst is received and decoded by a receiver of a DVB-H system, thereby preventing time delay during channel switching and providing a PIP function.

Claims (10)

A method for decoding a multi-protocol encapsulated forward error correction (MPE-FEC) frame at a receiver of a digital broadcasting system, Assigning and buffering a predetermined area to the frame buffer and the erasure buffer for the burst received from the wireless network; Performing Reed-Solomon decoding on the burst when buffering of the burst is completed in the frame buffer; Releasing the region of the erasure buffer allocated for the burst after the Reed-Solomon decoding; Outputting the burst buffered to the frame buffer through an interface after the allocation of the area of the erasure buffer to the burst is released; And releasing the area of the frame buffer allocated for the burst after the output of the burst is completed through the interface. According to claim 1, Allocating a predetermined area of a frame buffer and an erasure buffer when a burst is received from the wireless network, Receiving a segment for buffering the frame buffer based on the received burst size information; Buffering the burst in the frame buffer according to the allocated segment; Allocating an erasure buffer segment for marking reliability information of the received burst to mark reliability information of the burst in the erasure buffer; And marking reliability information of the burst in the erasure buffer according to the allocated erasure buffer segment. The method of claim 2, The frame buffer has a size of twice the maximum size that can buffer the section data contained in one burst broadcast data receiving method in a digital video broadcasting system. According to claim 1, When buffering of the burst is completed in the frame buffer, a process of performing Reed-Solomon decoding on the burst may be performed. Searching for a column to be decoded in units of a column set from the buffered burst; Correcting an error by performing Reed-Solomon decoding on a column-by-column basis after searching for the column to be decoded; And initializing the reliability information for each burst in the column set unit after the error correction. An apparatus for decoding a multi-protocol encapsulated forward error correction (MPE-FEC) frame in a receiver of a digital broadcasting system, A frame buffer for buffering section data of the burst received from the wireless network; An erasure buffer for buffering reliability information of the received burst; A Reed-Solomon decoder which performs Reed-Solomon decoding on the burst when buffering of the burst is completed in the frame buffer; Allocate a predetermined area to the frame buffer to control the received burst, and allocate a predetermined area to the erasure buffer to buffer the reliability information of the burst, and after the Reed-Solomon decoding is completed Releases an area of the erasure buffer allocated for the burst, outputs a burst buffered to the frame buffer through an interface after the area of the erasure buffer is released for the burst, and And a main control unit releasing an area of the frame buffer allocated for the burst after outputting of the burst. The method of claim 5, A first arbiter for allocating time for access when the main control unit accesses the frame buffer; And a second arbiter for allocating time to be accessed when the main control unit accesses the erasure buffer. The method of claim 5, The main control unit, A buffering controller for buffering section data of the received burst in the frame buffer and buffering reliability information of the received burst in the erasure buffer; A reed-solomon decoder controller which controls to perform Reed-Solomon decoding on the burst if the buffering is completed by the buffering controller in the frame buffer; A serial output controller for outputting a burst buffered in the frame buffer through a serial interface when the Reed-Solomon decoding is completed; And a segment allocator for allocating a predetermined area for buffering the burst in the frame buffer and a predetermined area for buffering reliability information of the burst in the erasure buffer at the request of the buffering controller. Broadcast data receiving apparatus in a broadcasting system. The method of claim 7, wherein The buffering controller, Receives the size information of the received burst and allocates a segment of the frame buffer from the segment allocator to buffer the burst in the frame buffer and buffers the section data of the burst in the frame buffer according to the allocated segment. And allocating segments of the erasure buffer from the segment allocator to buffer the reliability information of the burst and buffering the reliability information in the eraser buffer according to the allocated segment. Broadcast data reception device. The method of claim 8, The frame buffer, Broadcast data receiving apparatus in a digital video broadcasting system, characterized in that it has a size twice the maximum size that can buffer the section data contained in one burst. The method of claim 5, The Reed-Solomon decoder, Search for a column to decode in a column set unit in the burst buffered in the frame buffer, correct the error by performing Reed-Solomon decoding on a column basis after the search, and correct the error in the column set unit for the burst after the error correction. Broadcast data receiving apparatus in a digital video broadcasting system, characterized in that for initializing the reliability information.

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